cayman_accel.c revision c4ae5be6 
1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Alex Deucher <alexander.deucher@amd.com>
24 *
25 */
26#ifdef HAVE_CONFIG_H
27#include "config.h"
28#endif
29
30#ifdef XF86DRM_MODE
31
32#include "xf86.h"
33
34#include <errno.h>
35
36#include "radeon.h"
37#include "radeon_reg.h"
38#include "cayman_reg.h"
39#include "evergreen_state.h"
40
41#include "radeon_drm.h"
42#include "radeon_vbo.h"
43#include "radeon_exa_shared.h"
44
45/*
46 * Setup of default state
47 */
48
49void
50cayman_set_default_state(ScrnInfoPtr pScrn)
51{
52    tex_resource_t tex_res;
53    shader_config_t fs_conf;
54    int i;
55    RADEONInfoPtr info = RADEONPTR(pScrn);
56    struct radeon_accel_state *accel_state = info->accel_state;
57
58    if (accel_state->XInited3D)
59	return;
60
61    memset(&tex_res, 0, sizeof(tex_resource_t));
62    memset(&fs_conf, 0, sizeof(shader_config_t));
63
64    accel_state->XInited3D = TRUE;
65
66    evergreen_start_3d(pScrn);
67
68    BEGIN_BATCH(21);
69    EREG(SQ_LDS_ALLOC_PS, 0);
70
71    PACK0(SQ_ESGS_RING_ITEMSIZE, 6);
72    E32(0);
73    E32(0);
74    E32(0);
75    E32(0);
76    E32(0);
77    E32(0);
78
79    PACK0(SQ_GS_VERT_ITEMSIZE, 4);
80    E32(0);
81    E32(0);
82    E32(0);
83    E32(0);
84
85    PACK0(SQ_VTX_BASE_VTX_LOC, 2);
86    E32(0);
87    E32(0);
88    END_BATCH();
89
90    /* DB */
91    BEGIN_BATCH(3 + 2);
92    EREG(DB_Z_INFO,                           0);
93    RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
94    END_BATCH();
95
96    BEGIN_BATCH(3 + 2);
97    EREG(DB_STENCIL_INFO,                     0);
98    RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
99    END_BATCH();
100
101    BEGIN_BATCH(3 + 2);
102    EREG(DB_HTILE_DATA_BASE,                    0);
103    RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
104    END_BATCH();
105
106    BEGIN_BATCH(52);
107    EREG(DB_DEPTH_INFO,                       0);
108    EREG(DB_DEPTH_CONTROL,                    0);
109
110    PACK0(PA_SC_VPORT_ZMIN_0, 2);
111    EFLOAT(0.0); // PA_SC_VPORT_ZMIN_0
112    EFLOAT(1.0); // PA_SC_VPORT_ZMAX_0
113
114    PACK0(DB_RENDER_CONTROL, 5);
115    E32(STENCIL_COMPRESS_DISABLE_bit | DEPTH_COMPRESS_DISABLE_bit); // DB_RENDER_CONTROL
116    E32(0); // DB_COUNT_CONTROL
117    E32(0); // DB_DEPTH_VIEW
118    E32(0x2a); // DB_RENDER_OVERRIDE
119    E32(0); // DB_RENDER_OVERRIDE2
120
121    PACK0(DB_STENCIL_CLEAR, 2);
122    E32(0); // DB_STENCIL_CLEAR
123    E32(0); // DB_DEPTH_CLEAR
124
125    EREG(DB_ALPHA_TO_MASK,                    ((2 << ALPHA_TO_MASK_OFFSET0_shift)	|
126					       (2 << ALPHA_TO_MASK_OFFSET1_shift)	|
127					       (2 << ALPHA_TO_MASK_OFFSET2_shift)	|
128					       (2 << ALPHA_TO_MASK_OFFSET3_shift)));
129
130    EREG(DB_SHADER_CONTROL, ((EARLY_Z_THEN_LATE_Z << Z_ORDER_shift) |
131			     DUAL_EXPORT_ENABLE_bit)); /* Only useful if no depth export */
132
133    // SX
134    EREG(SX_MISC,               0);
135
136    // CB
137    PACK0(SX_ALPHA_TEST_CONTROL, 5);
138    E32(0); // SX_ALPHA_TEST_CONTROL
139    E32(0x00000000); //CB_BLEND_RED
140    E32(0x00000000); //CB_BLEND_GREEN
141    E32(0x00000000); //CB_BLEND_BLUE
142    E32(0x00000000); //CB_BLEND_ALPHA
143
144    EREG(CB_SHADER_MASK,                      OUTPUT0_ENABLE_mask);
145
146    // SC
147    EREG(PA_SC_WINDOW_OFFSET,                 ((0 << WINDOW_X_OFFSET_shift) |
148					       (0 << WINDOW_Y_OFFSET_shift)));
149    EREG(PA_SC_CLIPRECT_RULE,                 CLIP_RULE_mask);
150    EREG(PA_SC_EDGERULE,             0xAAAAAAAA);
151    EREG(PA_SU_HARDWARE_SCREEN_OFFSET, 0);
152    END_BATCH();
153
154    /* clip boolean is set to always visible -> doesn't matter */
155    for (i = 0; i < PA_SC_CLIPRECT_0_TL_num; i++)
156	evergreen_set_clip_rect (pScrn, i, 0, 0, 8192, 8192);
157
158    for (i = 0; i < PA_SC_VPORT_SCISSOR_0_TL_num; i++)
159	evergreen_set_vport_scissor (pScrn, i, 0, 0, 8192, 8192);
160
161    BEGIN_BATCH(73);
162    PACK0(PA_SC_MODE_CNTL_0, 2);
163    E32(0); // PA_SC_MODE_CNTL_0
164    E32(0); // PA_SC_MODE_CNTL_1
165
166    PACK0(PA_SC_CENTROID_PRIORITY_0, 27);
167    E32((0 << DISTANCE_0_shift) |
168	(1 << DISTANCE_1_shift) |
169	(2 << DISTANCE_2_shift) |
170	(3 << DISTANCE_3_shift) |
171	(4 << DISTANCE_4_shift) |
172	(5 << DISTANCE_5_shift) |
173	(6 << DISTANCE_6_shift) |
174	(7 << DISTANCE_7_shift)); // PA_SC_CENTROID_PRIORITY_0
175    E32((8 << DISTANCE_8_shift) |
176	(9 << DISTANCE_9_shift) |
177	(10 << DISTANCE_10_shift) |
178	(11 << DISTANCE_11_shift) |
179	(12 << DISTANCE_12_shift) |
180	(13 << DISTANCE_13_shift) |
181	(14 << DISTANCE_14_shift) |
182	(15 << DISTANCE_15_shift)); // PA_SC_CENTROID_PRIORITY_1
183    E32(0); // PA_SC_LINE_CNTL
184    E32(0); // PA_SC_AA_CONFIG
185    E32(((X_ROUND_TO_EVEN << PA_SU_VTX_CNTL__ROUND_MODE_shift) |
186	 PIX_CENTER_bit)); // PA_SU_VTX_CNTL
187    EFLOAT(1.0);						// PA_CL_GB_VERT_CLIP_ADJ
188    EFLOAT(1.0);						// PA_CL_GB_VERT_DISC_ADJ
189    EFLOAT(1.0);						// PA_CL_GB_HORZ_CLIP_ADJ
190    EFLOAT(1.0);						// PA_CL_GB_HORZ_DISC_ADJ
191    E32(0); // PA_SC_AA_SAMPLE_LOCS_PIXEL_*
192    E32(0);
193    E32(0);
194    E32(0);
195    E32(0);
196    E32(0);
197    E32(0);
198    E32(0);
199    E32(0);
200    E32(0);
201    E32(0);
202    E32(0);
203    E32(0);
204    E32(0);
205    E32(0);
206    E32(0); // PA_SC_AA_SAMPLE_LOCS__PIXEL_*
207    E32(0xFFFFFFFF); // PA_SC_AA_MASK_*
208    E32(0xFFFFFFFF); // PA_SC_AA_MASK_*
209
210    // CL
211    PACK0(PA_CL_CLIP_CNTL, 8);
212    E32(CLIP_DISABLE_bit); // PA_CL_CLIP_CNTL
213    E32(FACE_bit); // PA_SU_SC_MODE_CNTL
214    E32(VTX_XY_FMT_bit); // PA_CL_VTE_CNTL
215    E32(0); // PA_CL_VS_OUT_CNTL
216    E32(0); // PA_CL_NANINF_CNTL
217    E32(0); // PA_SU_LINE_STIPPLE_CNTL
218    E32(0); // PA_SU_LINE_STIPPLE_SCALE
219    E32(0); // PA_SU_PRIM_FILTER_CNTL
220
221    // SU
222    PACK0(PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6);
223    E32(0);
224    E32(0);
225    E32(0);
226    E32(0);
227    E32(0);
228    E32(0);
229
230    /* src = semantic id 0; mask = semantic id 1 */
231    EREG(SPI_VS_OUT_ID_0, ((0 << SEMANTIC_0_shift) |
232			   (1 << SEMANTIC_1_shift)));
233    PACK0(SPI_PS_INPUT_CNTL_0 + (0 << 2), 2);
234    /* SPI_PS_INPUT_CNTL_0 maps to GPR[0] - load with semantic id 0 */
235    E32(((0    << SEMANTIC_shift)	|
236	 (0x01 << DEFAULT_VAL_shift)));
237    /* SPI_PS_INPUT_CNTL_1 maps to GPR[1] - load with semantic id 1 */
238    E32(((1    << SEMANTIC_shift)	|
239	 (0x01 << DEFAULT_VAL_shift)));
240
241    PACK0(SPI_INPUT_Z, 13);
242    E32(0); // SPI_INPUT_Z
243    E32(0); // SPI_FOG_CNTL
244    E32(LINEAR_CENTROID_ENA__X_ON_AT_CENTROID << LINEAR_CENTROID_ENA_shift); // SPI_BARYC_CNTL
245    E32(0); // SPI_PS_IN_CONTROL_2
246    E32(0);
247    E32(0);
248    E32(0);
249    E32(0);
250    E32(0); // SPI_GPR_MGMT
251    E32(0); // SPI_LDS_MGMT
252    E32(0); // SPI_STACK_MGMT
253    E32(0); // SPI_WAVE_MGMT_1
254    E32(0); // SPI_WAVE_MGMT_2
255    END_BATCH();
256
257    // clear FS
258    fs_conf.bo = accel_state->shaders_bo;
259    evergreen_fs_setup(pScrn, &fs_conf, RADEON_GEM_DOMAIN_VRAM);
260
261    // VGT
262    BEGIN_BATCH(46);
263
264    PACK0(VGT_MAX_VTX_INDX, 4);
265    E32(0xffffff);
266    E32(0);
267    E32(0);
268    E32(0);
269
270    PACK0(VGT_INSTANCE_STEP_RATE_0, 2);
271    E32(0);
272    E32(0);
273
274    PACK0(VGT_REUSE_OFF, 2);
275    E32(0);
276    E32(0);
277
278    PACK0(PA_SU_POINT_SIZE, 17);
279    E32(0); // PA_SU_POINT_SIZE
280    E32(0); // PA_SU_POINT_MINMAX
281    E32((8 << PA_SU_LINE_CNTL__WIDTH_shift)); /* Line width 1 pixel */ // PA_SU_LINE_CNTL
282    E32(0); // PA_SC_LINE_STIPPLE
283    E32(0); // VGT_OUTPUT_PATH_CNTL
284    E32(0); // VGT_HOS_CNTL
285    E32(0);
286    E32(0);
287    E32(0);
288    E32(0);
289    E32(0);
290    E32(0);
291    E32(0);
292    E32(0);
293    E32(0);
294    E32(0);
295    E32(0); // VGT_GS_MODE
296
297    EREG(VGT_PRIMITIVEID_EN,                  0);
298    EREG(VGT_MULTI_PRIM_IB_RESET_EN,          0);
299    EREG(VGT_SHADER_STAGES_EN,          0);
300
301    PACK0(VGT_STRMOUT_CONFIG, 2);
302    E32(0);
303    E32(0);
304    END_BATCH();
305}
306
307#endif
308