evergreen_state.h revision 43df4709 
1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Alex Deucher <alexander.deucher@amd.com>
24 *
25 */
26
27#ifndef __EVERGREEN_STATE_H__
28#define __EVERGREEN_STATE_H__
29
30typedef int bool_t;
31
32#define CLEAR(x) memset (&x, 0, sizeof(x))
33
34/* Sequencer / thread handling */
35typedef struct {
36    int ps_prio;
37    int vs_prio;
38    int gs_prio;
39    int es_prio;
40    int hs_prio;
41    int ls_prio;
42    int cs_prio;
43    int num_ps_gprs;
44    int num_vs_gprs;
45    int num_gs_gprs;
46    int num_es_gprs;
47    int num_hs_gprs;
48    int num_ls_gprs;
49    int num_cs_gprs;
50    int num_temp_gprs;
51    int num_ps_threads;
52    int num_vs_threads;
53    int num_gs_threads;
54    int num_es_threads;
55    int num_hs_threads;
56    int num_ls_threads;
57    int num_ps_stack_entries;
58    int num_vs_stack_entries;
59    int num_gs_stack_entries;
60    int num_es_stack_entries;
61    int num_hs_stack_entries;
62    int num_ls_stack_entries;
63} sq_config_t;
64
65/* Color buffer / render target */
66typedef struct {
67    int id;
68    int w;
69    int h;
70    uint64_t base;
71    int format;
72    int endian;
73    int array_mode;						// tiling
74    int non_disp_tiling;
75    int number_type;
76    int read_size;
77    int comp_swap;
78    int tile_mode;
79    int blend_clamp;
80    int clear_color;
81    int blend_bypass;
82    int simple_float;
83    int round_mode;
84    int tile_compact;
85    int source_format;
86    int resource_type;
87    int fast_clear;
88    int compression;
89    int rat;
90    /* 2D related CB state */
91    uint32_t pmask;
92    int rop;
93    int blend_enable;
94    uint32_t blendcntl;
95    struct radeon_bo *bo;
96#ifdef XF86DRM_MODE
97    struct radeon_surface *surface;
98#endif
99} cb_config_t;
100
101/* Shader */
102typedef struct {
103    uint64_t shader_addr;
104    uint32_t shader_size;
105    int num_gprs;
106    int stack_size;
107    int dx10_clamp;
108    int clamp_consts;
109    int export_mode;
110    int uncached_first_inst;
111    int single_round;
112    int double_round;
113    int allow_sdi;
114    int allow_sd0;
115    int allow_ddi;
116    int allow_ddo;
117    struct radeon_bo *bo;
118} shader_config_t;
119
120/* Shader consts */
121typedef struct {
122    int type;
123    int size_bytes;
124    uint64_t const_addr;
125    struct radeon_bo *bo;
126    uint32_t *cpu_ptr;
127} const_config_t;
128
129/* Vertex buffer / vtx resource */
130typedef struct {
131    int id;
132    uint64_t vb_addr;
133    uint32_t vtx_num_entries;
134    uint32_t vtx_size_dw;
135    int clamp_x;
136    int format;
137    int num_format_all;
138    int format_comp_all;
139    int srf_mode_all;
140    int endian;
141    int mem_req_size;
142    int dst_sel_x;
143    int dst_sel_y;
144    int dst_sel_z;
145    int dst_sel_w;
146    int uncached;
147    struct radeon_bo *bo;
148} vtx_resource_t;
149
150/* Texture resource */
151typedef struct {
152    int id;
153    int w;
154    int h;
155    int pitch;
156    int depth;
157    int dim;
158    int array_mode;
159    int tile_type;
160    int format;
161    uint64_t base;
162    uint64_t mip_base;
163    uint32_t size;
164    int format_comp_x;
165    int format_comp_y;
166    int format_comp_z;
167    int format_comp_w;
168    int num_format_all;
169    int srf_mode_all;
170    int force_degamma;
171    int endian;
172    int dst_sel_x;
173    int dst_sel_y;
174    int dst_sel_z;
175    int dst_sel_w;
176    int base_level;
177    int last_level;
178    int base_array;
179    int last_array;
180    int perf_modulation;
181    int interlaced;
182    int min_lod;
183    struct radeon_bo *bo;
184    struct radeon_bo *mip_bo;
185#ifdef XF86DRM_MODE
186    struct radeon_surface *surface;
187#endif
188} tex_resource_t;
189
190/* Texture sampler */
191typedef struct {
192    int				id;
193    /* Clamping */
194    int				clamp_x, clamp_y, clamp_z;
195    int		       		border_color;
196    /* Filtering */
197    int				xy_mag_filter, xy_min_filter;
198    int				z_filter;
199    int				mip_filter;
200    bool_t			high_precision_filter;	/* ? */
201    int				perf_mip;		/* ? 0-7 */
202    int				perf_z;			/* ? 3 */
203    /* LoD selection */
204    int				min_lod, max_lod;	/* 0-0x3ff */
205    int                         lod_bias;		/* 0-0xfff (signed?) */
206    int                         lod_bias2;		/* ? 0-0xfff (signed?) */
207    bool_t			lod_uses_minor_axis;	/* ? */
208    /* Other stuff */
209    bool_t			point_sampling_clamp;	/* ? */
210    bool_t			tex_array_override;	/* ? */
211    bool_t                      mc_coord_truncate;	/* ? */
212    bool_t			force_degamma;		/* ? */
213    bool_t			fetch_4;		/* ? */
214    bool_t			sample_is_pcf;		/* ? */
215    bool_t			type;			/* ? */
216    int				depth_compare;		/* only depth textures? */
217    int				chroma_key;
218    int                         truncate_coord;
219    bool_t                      disable_cube_wrap;
220} tex_sampler_t;
221
222/* Draw command */
223typedef struct {
224    uint32_t prim_type;
225    uint32_t vgt_draw_initiator;
226    uint32_t index_type;
227    uint32_t num_instances;
228    uint32_t num_indices;
229} draw_config_t;
230
231#define BEGIN_BATCH(n)			\
232do {								\
233    radeon_ddx_cs_start(pScrn, (n), __FILE__, __func__, __LINE__);	\
234} while(0)
235#define END_BATCH()			\
236do {					\
237    radeon_cs_end(info->cs, __FILE__, __func__, __LINE__);	\
238} while(0)
239#define RELOC_BATCH(bo, rd, wd)				\
240do {							\
241    int _ret;								\
242    _ret = radeon_cs_write_reloc(info->cs, (bo), (rd), (wd), 0);	\
243    if (_ret) ErrorF("reloc emit failure %d (%s %d)\n", _ret, __func__, __LINE__); \
244} while(0)
245#define E32(dword)                                                  \
246do {                                                                    \
247    radeon_cs_write_dword(info->cs, (dword));				\
248} while (0)
249
250#define EFLOAT(val)							\
251do {								\
252    union { float f; uint32_t d; } a;                                   \
253    a.f = (val);							\
254    E32(a.d);							\
255} while (0)
256
257#define PACK3(cmd, num)	       					\
258do {                                                                    \
259    E32(RADEON_CP_PACKET3 | ((cmd) << 8) | ((((num) - 1) & 0x3fff) << 16)); \
260} while (0)
261
262/* write num registers, start at reg */
263/* If register falls in a special area, special commands are issued */
264#define PACK0(reg, num)                                             \
265do {                                                                    \
266    if ((reg) >= SET_CONFIG_REG_offset && (reg) < SET_CONFIG_REG_end) {	\
267	PACK3(IT_SET_CONFIG_REG, (num) + 1);			\
268	E32(((reg) - SET_CONFIG_REG_offset) >> 2);                  \
269    } else if ((reg) >= SET_CONTEXT_REG_offset && (reg) < SET_CONTEXT_REG_end) { \
270	PACK3(IT_SET_CONTEXT_REG, (num) + 1);			\
271	E32(((reg) - SET_CONTEXT_REG_offset) >> 2);			\
272    } else if ((reg) >= SET_RESOURCE_offset && (reg) < SET_RESOURCE_end) { \
273	PACK3(IT_SET_RESOURCE, num + 1);				\
274	E32(((reg) - SET_RESOURCE_offset) >> 2);			\
275    } else if ((reg) >= SET_SAMPLER_offset && (reg) < SET_SAMPLER_end) { \
276	PACK3(IT_SET_SAMPLER, (num) + 1);				\
277	E32((reg - SET_SAMPLER_offset) >> 2);			\
278    } else if ((reg) >= SET_CTL_CONST_offset && (reg) < SET_CTL_CONST_end) { \
279	PACK3(IT_SET_CTL_CONST, (num) + 1);			\
280	E32(((reg) - SET_CTL_CONST_offset) >> 2);		\
281    } else if ((reg) >= SET_LOOP_CONST_offset && (reg) < SET_LOOP_CONST_end) { \
282	PACK3(IT_SET_LOOP_CONST, (num) + 1);			\
283	E32(((reg) - SET_LOOP_CONST_offset) >> 2);		\
284    } else if ((reg) >= SET_BOOL_CONST_offset && (reg) < SET_BOOL_CONST_end) { \
285	PACK3(IT_SET_BOOL_CONST, (num) + 1);			\
286	E32(((reg) - SET_BOOL_CONST_offset) >> 2);		\
287    } else {								\
288	E32(CP_PACKET0 ((reg), (num) - 1));			\
289    }									\
290} while (0)
291
292/* write a single register */
293#define EREG(reg, val)                                              \
294do {								        \
295    PACK0((reg), 1);						\
296    E32((val));							\
297} while (0)
298
299void
300evergreen_start_3d(ScrnInfoPtr pScrn);
301void
302evergreen_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t domain);
303void
304evergreen_cp_wait_vline_sync(ScrnInfoPtr pScrn, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop);
305void
306evergreen_set_spi(ScrnInfoPtr pScrn, int vs_export_count, int num_interp);
307void
308evergreen_fs_setup(ScrnInfoPtr pScrn, shader_config_t *fs_conf, uint32_t domain);
309void
310evergreen_vs_setup(ScrnInfoPtr pScrn, shader_config_t *vs_conf, uint32_t domain);
311void
312evergreen_ps_setup(ScrnInfoPtr pScrn, shader_config_t *ps_conf, uint32_t domain);
313void
314evergreen_set_alu_consts(ScrnInfoPtr pScrn, const_config_t *const_conf, uint32_t domain);
315void
316evergreen_set_bool_consts(ScrnInfoPtr pScrn, int offset, uint32_t val);
317void
318evergreen_set_tex_resource(ScrnInfoPtr pScrn, tex_resource_t *tex_res, uint32_t domain);
319void
320evergreen_set_tex_sampler(ScrnInfoPtr pScrn, tex_sampler_t *s);
321void
322evergreen_set_screen_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
323void
324evergreen_set_vport_scissor(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2);
325void
326evergreen_set_generic_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
327void
328evergreen_set_window_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
329void
330evergreen_set_clip_rect(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2);
331void
332evergreen_set_default_state(ScrnInfoPtr pScrn);
333void
334cayman_set_default_state(ScrnInfoPtr pScrn);
335void
336evergreen_draw_auto(ScrnInfoPtr pScrn, draw_config_t *draw_conf);
337
338void evergreen_finish_op(ScrnInfoPtr pScrn, int vtx_size);
339
340extern Bool
341R600SetAccelState(ScrnInfoPtr pScrn,
342		  struct r600_accel_object *src0,
343		  struct r600_accel_object *src1,
344		  struct r600_accel_object *dst,
345		  uint32_t vs_offset, uint32_t ps_offset,
346		  int rop, Pixel planemask);
347
348extern Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index);
349extern void RADEONFinishAccess_CS(PixmapPtr pPix, int index);
350extern void *RADEONEXACreatePixmap(ScreenPtr pScreen, int size, int align);
351extern void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
352				    int depth, int usage_hint, int bitsPerPixel,
353				    int *new_pitch);
354extern void RADEONEXADestroyPixmap(ScreenPtr pScreen, void *driverPriv);
355extern struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix);
356extern Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix);
357
358#endif
359