evergreen_state.h revision 921a55d8 
1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Alex Deucher <alexander.deucher@amd.com>
24 *
25 */
26
27#ifndef __EVERGREEN_STATE_H__
28#define __EVERGREEN_STATE_H__
29
30typedef int bool_t;
31
32#define CLEAR(x) memset (&x, 0, sizeof(x))
33
34/* Sequencer / thread handling */
35typedef struct {
36    int ps_prio;
37    int vs_prio;
38    int gs_prio;
39    int es_prio;
40    int hs_prio;
41    int ls_prio;
42    int cs_prio;
43    int num_ps_gprs;
44    int num_vs_gprs;
45    int num_gs_gprs;
46    int num_es_gprs;
47    int num_hs_gprs;
48    int num_ls_gprs;
49    int num_cs_gprs;
50    int num_temp_gprs;
51    int num_ps_threads;
52    int num_vs_threads;
53    int num_gs_threads;
54    int num_es_threads;
55    int num_hs_threads;
56    int num_ls_threads;
57    int num_ps_stack_entries;
58    int num_vs_stack_entries;
59    int num_gs_stack_entries;
60    int num_es_stack_entries;
61    int num_hs_stack_entries;
62    int num_ls_stack_entries;
63} sq_config_t;
64
65/* Color buffer / render target */
66typedef struct {
67    int id;
68    int w;
69    int h;
70    uint64_t base;
71    int format;
72    int endian;
73    int array_mode;						// tiling
74    int number_type;
75    int read_size;
76    int comp_swap;
77    int tile_mode;
78    int blend_clamp;
79    int clear_color;
80    int blend_bypass;
81    int simple_float;
82    int round_mode;
83    int tile_compact;
84    int source_format;
85    int resource_type;
86    int fast_clear;
87    int compression;
88    int rat;
89    struct radeon_bo *bo;
90} cb_config_t;
91
92/* Shader */
93typedef struct {
94    uint64_t shader_addr;
95    uint32_t shader_size;
96    int num_gprs;
97    int stack_size;
98    int dx10_clamp;
99    int clamp_consts;
100    int export_mode;
101    int uncached_first_inst;
102    int single_round;
103    int double_round;
104    int allow_sdi;
105    int allow_sd0;
106    int allow_ddi;
107    int allow_ddo;
108    struct radeon_bo *bo;
109} shader_config_t;
110
111/* Shader consts */
112typedef struct {
113    int type;
114    int size_bytes;
115    uint64_t const_addr;
116    struct radeon_bo *bo;
117} const_config_t;
118
119/* Vertex buffer / vtx resource */
120typedef struct {
121    int id;
122    uint64_t vb_addr;
123    uint32_t vtx_num_entries;
124    uint32_t vtx_size_dw;
125    int clamp_x;
126    int format;
127    int num_format_all;
128    int format_comp_all;
129    int srf_mode_all;
130    int endian;
131    int mem_req_size;
132    int dst_sel_x;
133    int dst_sel_y;
134    int dst_sel_z;
135    int dst_sel_w;
136    int uncached;
137    struct radeon_bo *bo;
138} vtx_resource_t;
139
140/* Texture resource */
141typedef struct {
142    int id;
143    int w;
144    int h;
145    int pitch;
146    int depth;
147    int dim;
148    int array_mode;
149    int tile_type;
150    int format;
151    uint64_t base;
152    uint64_t mip_base;
153    uint32_t size;
154    int format_comp_x;
155    int format_comp_y;
156    int format_comp_z;
157    int format_comp_w;
158    int num_format_all;
159    int srf_mode_all;
160    int force_degamma;
161    int endian;
162    int dst_sel_x;
163    int dst_sel_y;
164    int dst_sel_z;
165    int dst_sel_w;
166    int base_level;
167    int last_level;
168    int base_array;
169    int last_array;
170    int perf_modulation;
171    int interlaced;
172    int min_lod;
173    struct radeon_bo *bo;
174    struct radeon_bo *mip_bo;
175} tex_resource_t;
176
177/* Texture sampler */
178typedef struct {
179    int				id;
180    /* Clamping */
181    int				clamp_x, clamp_y, clamp_z;
182    int		       		border_color;
183    /* Filtering */
184    int				xy_mag_filter, xy_min_filter;
185    int				z_filter;
186    int				mip_filter;
187    bool_t			high_precision_filter;	/* ? */
188    int				perf_mip;		/* ? 0-7 */
189    int				perf_z;			/* ? 3 */
190    /* LoD selection */
191    int				min_lod, max_lod;	/* 0-0x3ff */
192    int                         lod_bias;		/* 0-0xfff (signed?) */
193    int                         lod_bias2;		/* ? 0-0xfff (signed?) */
194    bool_t			lod_uses_minor_axis;	/* ? */
195    /* Other stuff */
196    bool_t			point_sampling_clamp;	/* ? */
197    bool_t			tex_array_override;	/* ? */
198    bool_t                      mc_coord_truncate;	/* ? */
199    bool_t			force_degamma;		/* ? */
200    bool_t			fetch_4;		/* ? */
201    bool_t			sample_is_pcf;		/* ? */
202    bool_t			type;			/* ? */
203    int				depth_compare;		/* only depth textures? */
204    int				chroma_key;
205    int                         truncate_coord;
206    bool_t                      disable_cube_wrap;
207} tex_sampler_t;
208
209/* Draw command */
210typedef struct {
211    uint32_t prim_type;
212    uint32_t vgt_draw_initiator;
213    uint32_t index_type;
214    uint32_t num_instances;
215    uint32_t num_indices;
216} draw_config_t;
217
218#define BEGIN_BATCH(n)			\
219do {								\
220    radeon_ddx_cs_start(pScrn, (n), __FILE__, __func__, __LINE__);	\
221} while(0)
222#define END_BATCH()			\
223do {					\
224    radeon_cs_end(info->cs, __FILE__, __func__, __LINE__);	\
225} while(0)
226#define RELOC_BATCH(bo, rd, wd)				\
227do {							\
228    int _ret;								\
229    _ret = radeon_cs_write_reloc(info->cs, (bo), (rd), (wd), 0);	\
230    if (_ret) ErrorF("reloc emit failure %d (%s %d)\n", _ret, __func__, __LINE__); \
231} while(0)
232#define E32(dword)                                                  \
233do {                                                                    \
234    radeon_cs_write_dword(info->cs, (dword));				\
235} while (0)
236
237#define EFLOAT(val)							\
238do {								\
239    union { float f; uint32_t d; } a;                                   \
240    a.f = (val);							\
241    E32(a.d);							\
242} while (0)
243
244#define PACK3(cmd, num)	       					\
245do {                                                                    \
246    E32(RADEON_CP_PACKET3 | ((cmd) << 8) | ((((num) - 1) & 0x3fff) << 16)); \
247} while (0)
248
249/* write num registers, start at reg */
250/* If register falls in a special area, special commands are issued */
251#define PACK0(reg, num)                                             \
252do {                                                                    \
253    if ((reg) >= SET_CONFIG_REG_offset && (reg) < SET_CONFIG_REG_end) {	\
254	PACK3(IT_SET_CONFIG_REG, (num) + 1);			\
255	E32(((reg) - SET_CONFIG_REG_offset) >> 2);                  \
256    } else if ((reg) >= SET_CONTEXT_REG_offset && (reg) < SET_CONTEXT_REG_end) { \
257	PACK3(IT_SET_CONTEXT_REG, (num) + 1);			\
258	E32(((reg) - SET_CONTEXT_REG_offset) >> 2);			\
259    } else if ((reg) >= SET_RESOURCE_offset && (reg) < SET_RESOURCE_end) { \
260	PACK3(IT_SET_RESOURCE, num + 1);				\
261	E32(((reg) - SET_RESOURCE_offset) >> 2);			\
262    } else if ((reg) >= SET_SAMPLER_offset && (reg) < SET_SAMPLER_end) { \
263	PACK3(IT_SET_SAMPLER, (num) + 1);				\
264	E32((reg - SET_SAMPLER_offset) >> 2);			\
265    } else if ((reg) >= SET_CTL_CONST_offset && (reg) < SET_CTL_CONST_end) { \
266	PACK3(IT_SET_CTL_CONST, (num) + 1);			\
267	E32(((reg) - SET_CTL_CONST_offset) >> 2);		\
268    } else if ((reg) >= SET_LOOP_CONST_offset && (reg) < SET_LOOP_CONST_end) { \
269	PACK3(IT_SET_LOOP_CONST, (num) + 1);			\
270	E32(((reg) - SET_LOOP_CONST_offset) >> 2);		\
271    } else if ((reg) >= SET_BOOL_CONST_offset && (reg) < SET_BOOL_CONST_end) { \
272	PACK3(IT_SET_BOOL_CONST, (num) + 1);			\
273	E32(((reg) - SET_BOOL_CONST_offset) >> 2);		\
274    } else {								\
275	E32(CP_PACKET0 ((reg), (num) - 1));			\
276    }									\
277} while (0)
278
279/* write a single register */
280#define EREG(reg, val)                                              \
281do {								        \
282    PACK0((reg), 1);						\
283    E32((val));							\
284} while (0)
285
286void
287evergreen_start_3d(ScrnInfoPtr pScrn);
288void
289evergreen_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t domain);
290void
291evergreen_cp_wait_vline_sync(ScrnInfoPtr pScrn, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop);
292void
293evergreen_fs_setup(ScrnInfoPtr pScrn, shader_config_t *fs_conf, uint32_t domain);
294void
295evergreen_vs_setup(ScrnInfoPtr pScrn, shader_config_t *vs_conf, uint32_t domain);
296void
297evergreen_ps_setup(ScrnInfoPtr pScrn, shader_config_t *ps_conf, uint32_t domain);
298void
299evergreen_set_alu_consts(ScrnInfoPtr pScrn, const_config_t *const_conf, uint32_t domain);
300void
301evergreen_set_bool_consts(ScrnInfoPtr pScrn, int offset, uint32_t val);
302void
303evergreen_set_tex_resource(ScrnInfoPtr pScrn, tex_resource_t *tex_res, uint32_t domain);
304void
305evergreen_set_tex_sampler(ScrnInfoPtr pScrn, tex_sampler_t *s);
306void
307evergreen_set_screen_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
308void
309evergreen_set_vport_scissor(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2);
310void
311evergreen_set_generic_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
312void
313evergreen_set_window_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
314void
315evergreen_set_clip_rect(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2);
316void
317evergreen_set_default_state(ScrnInfoPtr pScrn);
318void
319evergreen_draw_auto(ScrnInfoPtr pScrn, draw_config_t *draw_conf);
320
321void evergreen_finish_op(ScrnInfoPtr pScrn, int vtx_size);
322
323Bool
324EVERGREENSetAccelState(ScrnInfoPtr pScrn,
325		       struct r600_accel_object *src0,
326		       struct r600_accel_object *src1,
327		       struct r600_accel_object *dst,
328		       uint32_t vs_offset, uint32_t ps_offset,
329		       int rop, Pixel planemask);
330
331extern Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index);
332extern void RADEONFinishAccess_CS(PixmapPtr pPix, int index);
333extern void *RADEONEXACreatePixmap(ScreenPtr pScreen, int size, int align);
334extern void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
335				    int depth, int usage_hint, int bitsPerPixel,
336				    int *new_pitch);
337extern void RADEONEXADestroyPixmap(ScreenPtr pScreen, void *driverPriv);
338extern struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix);
339extern Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix);
340
341#endif
342