evergreen_state.h revision c4ae5be6 
1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Alex Deucher <alexander.deucher@amd.com>
24 *
25 */
26
27#ifndef __EVERGREEN_STATE_H__
28#define __EVERGREEN_STATE_H__
29
30typedef int bool_t;
31
32#define CLEAR(x) memset (&x, 0, sizeof(x))
33
34/* Sequencer / thread handling */
35typedef struct {
36    int ps_prio;
37    int vs_prio;
38    int gs_prio;
39    int es_prio;
40    int hs_prio;
41    int ls_prio;
42    int cs_prio;
43    int num_ps_gprs;
44    int num_vs_gprs;
45    int num_gs_gprs;
46    int num_es_gprs;
47    int num_hs_gprs;
48    int num_ls_gprs;
49    int num_cs_gprs;
50    int num_temp_gprs;
51    int num_ps_threads;
52    int num_vs_threads;
53    int num_gs_threads;
54    int num_es_threads;
55    int num_hs_threads;
56    int num_ls_threads;
57    int num_ps_stack_entries;
58    int num_vs_stack_entries;
59    int num_gs_stack_entries;
60    int num_es_stack_entries;
61    int num_hs_stack_entries;
62    int num_ls_stack_entries;
63} sq_config_t;
64
65/* Color buffer / render target */
66typedef struct {
67    int id;
68    int w;
69    int h;
70    uint64_t base;
71    int format;
72    int endian;
73    int array_mode;						// tiling
74    int non_disp_tiling;
75    int number_type;
76    int read_size;
77    int comp_swap;
78    int tile_mode;
79    int blend_clamp;
80    int clear_color;
81    int blend_bypass;
82    int simple_float;
83    int round_mode;
84    int tile_compact;
85    int source_format;
86    int resource_type;
87    int fast_clear;
88    int compression;
89    int rat;
90    /* 2D related CB state */
91    uint32_t pmask;
92    int rop;
93    int blend_enable;
94    uint32_t blendcntl;
95    struct radeon_bo *bo;
96} cb_config_t;
97
98/* Shader */
99typedef struct {
100    uint64_t shader_addr;
101    uint32_t shader_size;
102    int num_gprs;
103    int stack_size;
104    int dx10_clamp;
105    int clamp_consts;
106    int export_mode;
107    int uncached_first_inst;
108    int single_round;
109    int double_round;
110    int allow_sdi;
111    int allow_sd0;
112    int allow_ddi;
113    int allow_ddo;
114    struct radeon_bo *bo;
115} shader_config_t;
116
117/* Shader consts */
118typedef struct {
119    int type;
120    int size_bytes;
121    uint64_t const_addr;
122    struct radeon_bo *bo;
123} const_config_t;
124
125/* Vertex buffer / vtx resource */
126typedef struct {
127    int id;
128    uint64_t vb_addr;
129    uint32_t vtx_num_entries;
130    uint32_t vtx_size_dw;
131    int clamp_x;
132    int format;
133    int num_format_all;
134    int format_comp_all;
135    int srf_mode_all;
136    int endian;
137    int mem_req_size;
138    int dst_sel_x;
139    int dst_sel_y;
140    int dst_sel_z;
141    int dst_sel_w;
142    int uncached;
143    struct radeon_bo *bo;
144} vtx_resource_t;
145
146/* Texture resource */
147typedef struct {
148    int id;
149    int w;
150    int h;
151    int pitch;
152    int depth;
153    int dim;
154    int array_mode;
155    int tile_type;
156    int format;
157    uint64_t base;
158    uint64_t mip_base;
159    uint32_t size;
160    int format_comp_x;
161    int format_comp_y;
162    int format_comp_z;
163    int format_comp_w;
164    int num_format_all;
165    int srf_mode_all;
166    int force_degamma;
167    int endian;
168    int dst_sel_x;
169    int dst_sel_y;
170    int dst_sel_z;
171    int dst_sel_w;
172    int base_level;
173    int last_level;
174    int base_array;
175    int last_array;
176    int perf_modulation;
177    int interlaced;
178    int min_lod;
179    struct radeon_bo *bo;
180    struct radeon_bo *mip_bo;
181} tex_resource_t;
182
183/* Texture sampler */
184typedef struct {
185    int				id;
186    /* Clamping */
187    int				clamp_x, clamp_y, clamp_z;
188    int		       		border_color;
189    /* Filtering */
190    int				xy_mag_filter, xy_min_filter;
191    int				z_filter;
192    int				mip_filter;
193    bool_t			high_precision_filter;	/* ? */
194    int				perf_mip;		/* ? 0-7 */
195    int				perf_z;			/* ? 3 */
196    /* LoD selection */
197    int				min_lod, max_lod;	/* 0-0x3ff */
198    int                         lod_bias;		/* 0-0xfff (signed?) */
199    int                         lod_bias2;		/* ? 0-0xfff (signed?) */
200    bool_t			lod_uses_minor_axis;	/* ? */
201    /* Other stuff */
202    bool_t			point_sampling_clamp;	/* ? */
203    bool_t			tex_array_override;	/* ? */
204    bool_t                      mc_coord_truncate;	/* ? */
205    bool_t			force_degamma;		/* ? */
206    bool_t			fetch_4;		/* ? */
207    bool_t			sample_is_pcf;		/* ? */
208    bool_t			type;			/* ? */
209    int				depth_compare;		/* only depth textures? */
210    int				chroma_key;
211    int                         truncate_coord;
212    bool_t                      disable_cube_wrap;
213} tex_sampler_t;
214
215/* Draw command */
216typedef struct {
217    uint32_t prim_type;
218    uint32_t vgt_draw_initiator;
219    uint32_t index_type;
220    uint32_t num_instances;
221    uint32_t num_indices;
222} draw_config_t;
223
224#define BEGIN_BATCH(n)			\
225do {								\
226    radeon_ddx_cs_start(pScrn, (n), __FILE__, __func__, __LINE__);	\
227} while(0)
228#define END_BATCH()			\
229do {					\
230    radeon_cs_end(info->cs, __FILE__, __func__, __LINE__);	\
231} while(0)
232#define RELOC_BATCH(bo, rd, wd)				\
233do {							\
234    int _ret;								\
235    _ret = radeon_cs_write_reloc(info->cs, (bo), (rd), (wd), 0);	\
236    if (_ret) ErrorF("reloc emit failure %d (%s %d)\n", _ret, __func__, __LINE__); \
237} while(0)
238#define E32(dword)                                                  \
239do {                                                                    \
240    radeon_cs_write_dword(info->cs, (dword));				\
241} while (0)
242
243#define EFLOAT(val)							\
244do {								\
245    union { float f; uint32_t d; } a;                                   \
246    a.f = (val);							\
247    E32(a.d);							\
248} while (0)
249
250#define PACK3(cmd, num)	       					\
251do {                                                                    \
252    E32(RADEON_CP_PACKET3 | ((cmd) << 8) | ((((num) - 1) & 0x3fff) << 16)); \
253} while (0)
254
255/* write num registers, start at reg */
256/* If register falls in a special area, special commands are issued */
257#define PACK0(reg, num)                                             \
258do {                                                                    \
259    if ((reg) >= SET_CONFIG_REG_offset && (reg) < SET_CONFIG_REG_end) {	\
260	PACK3(IT_SET_CONFIG_REG, (num) + 1);			\
261	E32(((reg) - SET_CONFIG_REG_offset) >> 2);                  \
262    } else if ((reg) >= SET_CONTEXT_REG_offset && (reg) < SET_CONTEXT_REG_end) { \
263	PACK3(IT_SET_CONTEXT_REG, (num) + 1);			\
264	E32(((reg) - SET_CONTEXT_REG_offset) >> 2);			\
265    } else if ((reg) >= SET_RESOURCE_offset && (reg) < SET_RESOURCE_end) { \
266	PACK3(IT_SET_RESOURCE, num + 1);				\
267	E32(((reg) - SET_RESOURCE_offset) >> 2);			\
268    } else if ((reg) >= SET_SAMPLER_offset && (reg) < SET_SAMPLER_end) { \
269	PACK3(IT_SET_SAMPLER, (num) + 1);				\
270	E32((reg - SET_SAMPLER_offset) >> 2);			\
271    } else if ((reg) >= SET_CTL_CONST_offset && (reg) < SET_CTL_CONST_end) { \
272	PACK3(IT_SET_CTL_CONST, (num) + 1);			\
273	E32(((reg) - SET_CTL_CONST_offset) >> 2);		\
274    } else if ((reg) >= SET_LOOP_CONST_offset && (reg) < SET_LOOP_CONST_end) { \
275	PACK3(IT_SET_LOOP_CONST, (num) + 1);			\
276	E32(((reg) - SET_LOOP_CONST_offset) >> 2);		\
277    } else if ((reg) >= SET_BOOL_CONST_offset && (reg) < SET_BOOL_CONST_end) { \
278	PACK3(IT_SET_BOOL_CONST, (num) + 1);			\
279	E32(((reg) - SET_BOOL_CONST_offset) >> 2);		\
280    } else {								\
281	E32(CP_PACKET0 ((reg), (num) - 1));			\
282    }									\
283} while (0)
284
285/* write a single register */
286#define EREG(reg, val)                                              \
287do {								        \
288    PACK0((reg), 1);						\
289    E32((val));							\
290} while (0)
291
292void
293evergreen_start_3d(ScrnInfoPtr pScrn);
294void
295evergreen_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t domain);
296void
297evergreen_cp_wait_vline_sync(ScrnInfoPtr pScrn, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop);
298void
299evergreen_set_spi(ScrnInfoPtr pScrn, int vs_export_count, int num_interp);
300void
301evergreen_fs_setup(ScrnInfoPtr pScrn, shader_config_t *fs_conf, uint32_t domain);
302void
303evergreen_vs_setup(ScrnInfoPtr pScrn, shader_config_t *vs_conf, uint32_t domain);
304void
305evergreen_ps_setup(ScrnInfoPtr pScrn, shader_config_t *ps_conf, uint32_t domain);
306void
307evergreen_set_alu_consts(ScrnInfoPtr pScrn, const_config_t *const_conf, uint32_t domain);
308void
309evergreen_set_bool_consts(ScrnInfoPtr pScrn, int offset, uint32_t val);
310void
311evergreen_set_tex_resource(ScrnInfoPtr pScrn, tex_resource_t *tex_res, uint32_t domain);
312void
313evergreen_set_tex_sampler(ScrnInfoPtr pScrn, tex_sampler_t *s);
314void
315evergreen_set_screen_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
316void
317evergreen_set_vport_scissor(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2);
318void
319evergreen_set_generic_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
320void
321evergreen_set_window_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
322void
323evergreen_set_clip_rect(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2);
324void
325evergreen_set_default_state(ScrnInfoPtr pScrn);
326void
327cayman_set_default_state(ScrnInfoPtr pScrn);
328void
329evergreen_draw_auto(ScrnInfoPtr pScrn, draw_config_t *draw_conf);
330
331void evergreen_finish_op(ScrnInfoPtr pScrn, int vtx_size);
332
333extern Bool
334R600SetAccelState(ScrnInfoPtr pScrn,
335		  struct r600_accel_object *src0,
336		  struct r600_accel_object *src1,
337		  struct r600_accel_object *dst,
338		  uint32_t vs_offset, uint32_t ps_offset,
339		  int rop, Pixel planemask);
340
341extern Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index);
342extern void RADEONFinishAccess_CS(PixmapPtr pPix, int index);
343extern void *RADEONEXACreatePixmap(ScreenPtr pScreen, int size, int align);
344extern void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
345				    int depth, int usage_hint, int bitsPerPixel,
346				    int *new_pitch);
347extern void RADEONEXADestroyPixmap(ScreenPtr pScreen, void *driverPriv);
348extern struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix);
349extern Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix);
350
351#endif
352