evergreen_textured_videofuncs.c revision c4ae5be6
1/* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Author: Alex Deucher <alexander.deucher@amd.com> 24 * 25 */ 26 27#ifdef HAVE_CONFIG_H 28#include "config.h" 29#endif 30 31#ifdef XF86DRM_MODE 32 33#include "xf86.h" 34 35#include "exa.h" 36 37#include "radeon.h" 38#include "radeon_reg.h" 39#include "evergreen_shader.h" 40#include "evergreen_reg.h" 41#include "evergreen_state.h" 42 43#include "radeon_video.h" 44 45#include <X11/extensions/Xv.h> 46#include "fourcc.h" 47 48#include "damage.h" 49 50#include "radeon_exa_shared.h" 51#include "radeon_vbo.h" 52 53/* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces 54 note the difference to the parameters used in overlay are due 55 to 10bit vs. float calcs */ 56static REF_TRANSFORM trans[2] = 57{ 58 {1.1643, 0.0, 1.5960, -0.3918, -0.8129, 2.0172, 0.0}, /* BT.601 */ 59 {1.1643, 0.0, 1.7927, -0.2132, -0.5329, 2.1124, 0.0} /* BT.709 */ 60}; 61 62void 63EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) 64{ 65 RADEONInfoPtr info = RADEONPTR(pScrn); 66 struct radeon_accel_state *accel_state = info->accel_state; 67 PixmapPtr pPixmap = pPriv->pPixmap; 68 BoxPtr pBox = REGION_RECTS(&pPriv->clip); 69 int nBox = REGION_NUM_RECTS(&pPriv->clip); 70 int dstxoff, dstyoff; 71 struct r600_accel_object src_obj, dst_obj; 72 cb_config_t cb_conf; 73 tex_resource_t tex_res; 74 tex_sampler_t tex_samp; 75 shader_config_t vs_conf, ps_conf; 76 /* 77 * y' = y - .0625 78 * u' = u - .5 79 * v' = v - .5; 80 * 81 * r = 1.1643 * y' + 0.0 * u' + 1.5958 * v' 82 * g = 1.1643 * y' - 0.39173 * u' - 0.81290 * v' 83 * b = 1.1643 * y' + 2.017 * u' + 0.0 * v' 84 * 85 * DP3 might look like the straightforward solution 86 * but we'd need to move the texture yuv values in 87 * the same reg for this to work. Therefore use MADs. 88 * Brightness just adds to the off constant. 89 * Contrast is multiplication of luminance. 90 * Saturation and hue change the u and v coeffs. 91 * Default values (before adjustments - depend on colorspace): 92 * yco = 1.1643 93 * uco = 0, -0.39173, 2.017 94 * vco = 1.5958, -0.8129, 0 95 * off = -0.0625 * yco + -0.5 * uco[r] + -0.5 * vco[r], 96 * -0.0625 * yco + -0.5 * uco[g] + -0.5 * vco[g], 97 * -0.0625 * yco + -0.5 * uco[b] + -0.5 * vco[b], 98 * 99 * temp = MAD(yco, yuv.yyyy, off) 100 * temp = MAD(uco, yuv.uuuu, temp) 101 * result = MAD(vco, yuv.vvvv, temp) 102 */ 103 /* TODO: calc consts in the shader */ 104 const float Loff = -0.0627; 105 const float Coff = -0.502; 106 float uvcosf, uvsinf; 107 float yco; 108 float uco[3], vco[3], off[3]; 109 float bright, cont, gamma; 110 int ref = pPriv->transform_index; 111 Bool needgamma = FALSE; 112 float *ps_alu_consts; 113 const_config_t ps_const_conf; 114 float *vs_alu_consts; 115 const_config_t vs_const_conf; 116 117 cont = RTFContrast(pPriv->contrast); 118 bright = RTFBrightness(pPriv->brightness); 119 gamma = (float)pPriv->gamma / 1000.0; 120 uvcosf = RTFSaturation(pPriv->saturation) * cos(RTFHue(pPriv->hue)); 121 uvsinf = RTFSaturation(pPriv->saturation) * sin(RTFHue(pPriv->hue)); 122 /* overlay video also does pre-gamma contrast/sat adjust, should we? */ 123 124 yco = trans[ref].RefLuma * cont; 125 uco[0] = -trans[ref].RefRCr * uvsinf; 126 uco[1] = trans[ref].RefGCb * uvcosf - trans[ref].RefGCr * uvsinf; 127 uco[2] = trans[ref].RefBCb * uvcosf; 128 vco[0] = trans[ref].RefRCr * uvcosf; 129 vco[1] = trans[ref].RefGCb * uvsinf + trans[ref].RefGCr * uvcosf; 130 vco[2] = trans[ref].RefBCb * uvsinf; 131 off[0] = Loff * yco + Coff * (uco[0] + vco[0]) + bright; 132 off[1] = Loff * yco + Coff * (uco[1] + vco[1]) + bright; 133 off[2] = Loff * yco + Coff * (uco[2] + vco[2]) + bright; 134 135 // XXX 136 gamma = 1.0; 137 138 if (gamma != 1.0) { 139 needgamma = TRUE; 140 /* note: gamma correction is out = in ^ gamma; 141 gpu can only do LG2/EX2 therefore we transform into 142 in ^ gamma = 2 ^ (log2(in) * gamma). 143 Lots of scalar ops, unfortunately (better solution?) - 144 without gamma that's 3 inst, with gamma it's 10... 145 could use different gamma factors per channel, 146 if that's of any use. */ 147 } 148 149 CLEAR (cb_conf); 150 CLEAR (tex_res); 151 CLEAR (tex_samp); 152 CLEAR (vs_conf); 153 CLEAR (ps_conf); 154 CLEAR (vs_const_conf); 155 CLEAR (ps_const_conf); 156 157 dst_obj.offset = 0; 158 src_obj.offset = 0; 159 dst_obj.bo = radeon_get_pixmap_bo(pPixmap); 160 dst_obj.tiling_flags = radeon_get_pixmap_tiling(pPixmap); 161 162 dst_obj.pitch = exaGetPixmapPitch(pPixmap) / (pPixmap->drawable.bitsPerPixel / 8); 163 164 src_obj.pitch = pPriv->src_pitch; 165 src_obj.width = pPriv->w; 166 src_obj.height = pPriv->h; 167 src_obj.bpp = 16; 168 src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT; 169 src_obj.bo = pPriv->src_bo[pPriv->currentBuffer]; 170 src_obj.tiling_flags = 0; 171 172 dst_obj.width = pPixmap->drawable.width; 173 dst_obj.height = pPixmap->drawable.height; 174 dst_obj.bpp = pPixmap->drawable.bitsPerPixel; 175 dst_obj.domain = RADEON_GEM_DOMAIN_VRAM; 176 177 if (!R600SetAccelState(pScrn, 178 &src_obj, 179 NULL, 180 &dst_obj, 181 accel_state->xv_vs_offset, accel_state->xv_ps_offset, 182 3, 0xffffffff)) 183 return; 184 185#ifdef COMPOSITE 186 dstxoff = -pPixmap->screen_x + pPixmap->drawable.x; 187 dstyoff = -pPixmap->screen_y + pPixmap->drawable.y; 188#else 189 dstxoff = 0; 190 dstyoff = 0; 191#endif 192 193 radeon_vbo_check(pScrn, &accel_state->vbo, 16); 194 radeon_vbo_check(pScrn, &accel_state->cbuf, 512); 195 radeon_cp_start(pScrn); 196 197 evergreen_set_default_state(pScrn); 198 199 evergreen_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); 200 evergreen_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); 201 evergreen_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); 202 203 /* PS bool constant */ 204 switch(pPriv->id) { 205 case FOURCC_YV12: 206 case FOURCC_I420: 207 evergreen_set_bool_consts(pScrn, SQ_BOOL_CONST_ps, (1 << 0)); 208 break; 209 case FOURCC_UYVY: 210 case FOURCC_YUY2: 211 default: 212 evergreen_set_bool_consts(pScrn, SQ_BOOL_CONST_ps, (0 << 0)); 213 break; 214 } 215 216 /* Shader */ 217 vs_conf.shader_addr = accel_state->vs_mc_addr; 218 vs_conf.shader_size = accel_state->vs_size; 219 vs_conf.num_gprs = 2; 220 vs_conf.stack_size = 0; 221 vs_conf.bo = accel_state->shaders_bo; 222 evergreen_vs_setup(pScrn, &vs_conf, RADEON_GEM_DOMAIN_VRAM); 223 224 ps_conf.shader_addr = accel_state->ps_mc_addr; 225 ps_conf.shader_size = accel_state->ps_size; 226 ps_conf.num_gprs = 3; 227 ps_conf.stack_size = 1; 228 ps_conf.clamp_consts = 0; 229 ps_conf.export_mode = 2; 230 ps_conf.bo = accel_state->shaders_bo; 231 evergreen_ps_setup(pScrn, &ps_conf, RADEON_GEM_DOMAIN_VRAM); 232 233 /* Texture */ 234 switch(pPriv->id) { 235 case FOURCC_YV12: 236 case FOURCC_I420: 237 accel_state->src_size[0] = accel_state->src_obj[0].pitch * pPriv->h; 238 239 /* Y texture */ 240 tex_res.id = 0; 241 tex_res.w = accel_state->src_obj[0].width; 242 tex_res.h = accel_state->src_obj[0].height; 243 tex_res.pitch = accel_state->src_obj[0].pitch; 244 tex_res.depth = 0; 245 tex_res.dim = SQ_TEX_DIM_2D; 246 tex_res.base = accel_state->src_obj[0].offset; 247 tex_res.mip_base = accel_state->src_obj[0].offset; 248 tex_res.size = accel_state->src_size[0]; 249 tex_res.bo = accel_state->src_obj[0].bo; 250 tex_res.mip_bo = accel_state->src_obj[0].bo; 251 252 tex_res.format = FMT_8; 253 tex_res.dst_sel_x = SQ_SEL_X; /* Y */ 254 tex_res.dst_sel_y = SQ_SEL_1; 255 tex_res.dst_sel_z = SQ_SEL_1; 256 tex_res.dst_sel_w = SQ_SEL_1; 257 258 tex_res.base_level = 0; 259 tex_res.last_level = 0; 260 tex_res.perf_modulation = 0; 261 tex_res.interlaced = 0; 262 if (accel_state->src_obj[0].tiling_flags == 0) 263 tex_res.array_mode = 1; 264 evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); 265 266 /* Y sampler */ 267 tex_samp.id = 0; 268 tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL; 269 tex_samp.clamp_y = SQ_TEX_CLAMP_LAST_TEXEL; 270 tex_samp.clamp_z = SQ_TEX_WRAP; 271 272 /* xxx: switch to bicubic */ 273 tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_BILINEAR; 274 tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_BILINEAR; 275 276 tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE; 277 tex_samp.mip_filter = 0; /* no mipmap */ 278 evergreen_set_tex_sampler(pScrn, &tex_samp); 279 280 /* U or V texture */ 281 tex_res.id = 1; 282 tex_res.format = FMT_8; 283 tex_res.w = accel_state->src_obj[0].width >> 1; 284 tex_res.h = accel_state->src_obj[0].height >> 1; 285 tex_res.pitch = RADEON_ALIGN(accel_state->src_obj[0].pitch >> 1, pPriv->hw_align); 286 tex_res.dst_sel_x = SQ_SEL_X; /* V or U */ 287 tex_res.dst_sel_y = SQ_SEL_1; 288 tex_res.dst_sel_z = SQ_SEL_1; 289 tex_res.dst_sel_w = SQ_SEL_1; 290 tex_res.interlaced = 0; 291 292 tex_res.base = accel_state->src_obj[0].offset + pPriv->planev_offset; 293 tex_res.mip_base = accel_state->src_obj[0].offset + pPriv->planev_offset; 294 tex_res.size = tex_res.pitch * (pPriv->h >> 1); 295 if (accel_state->src_obj[0].tiling_flags == 0) 296 tex_res.array_mode = 1; 297 evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); 298 299 /* U or V sampler */ 300 tex_samp.id = 1; 301 evergreen_set_tex_sampler(pScrn, &tex_samp); 302 303 /* U or V texture */ 304 tex_res.id = 2; 305 tex_res.format = FMT_8; 306 tex_res.w = accel_state->src_obj[0].width >> 1; 307 tex_res.h = accel_state->src_obj[0].height >> 1; 308 tex_res.pitch = RADEON_ALIGN(accel_state->src_obj[0].pitch >> 1, pPriv->hw_align); 309 tex_res.dst_sel_x = SQ_SEL_X; /* V or U */ 310 tex_res.dst_sel_y = SQ_SEL_1; 311 tex_res.dst_sel_z = SQ_SEL_1; 312 tex_res.dst_sel_w = SQ_SEL_1; 313 tex_res.interlaced = 0; 314 315 tex_res.base = accel_state->src_obj[0].offset + pPriv->planeu_offset; 316 tex_res.mip_base = accel_state->src_obj[0].offset + pPriv->planeu_offset; 317 tex_res.size = tex_res.pitch * (pPriv->h >> 1); 318 if (accel_state->src_obj[0].tiling_flags == 0) 319 tex_res.array_mode = 1; 320 evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); 321 322 /* UV sampler */ 323 tex_samp.id = 2; 324 evergreen_set_tex_sampler(pScrn, &tex_samp); 325 break; 326 case FOURCC_UYVY: 327 case FOURCC_YUY2: 328 default: 329 accel_state->src_size[0] = accel_state->src_obj[0].pitch * pPriv->h; 330 331 /* Y texture */ 332 tex_res.id = 0; 333 tex_res.w = accel_state->src_obj[0].width; 334 tex_res.h = accel_state->src_obj[0].height; 335 tex_res.pitch = accel_state->src_obj[0].pitch >> 1; 336 tex_res.depth = 0; 337 tex_res.dim = SQ_TEX_DIM_2D; 338 tex_res.base = accel_state->src_obj[0].offset; 339 tex_res.mip_base = accel_state->src_obj[0].offset; 340 tex_res.size = accel_state->src_size[0]; 341 tex_res.bo = accel_state->src_obj[0].bo; 342 tex_res.mip_bo = accel_state->src_obj[0].bo; 343 344 tex_res.format = FMT_8_8; 345 if (pPriv->id == FOURCC_UYVY) 346 tex_res.dst_sel_x = SQ_SEL_Y; /* Y */ 347 else 348 tex_res.dst_sel_x = SQ_SEL_X; /* Y */ 349 tex_res.dst_sel_y = SQ_SEL_1; 350 tex_res.dst_sel_z = SQ_SEL_1; 351 tex_res.dst_sel_w = SQ_SEL_1; 352 353 tex_res.base_level = 0; 354 tex_res.last_level = 0; 355 tex_res.perf_modulation = 0; 356 tex_res.interlaced = 0; 357 if (accel_state->src_obj[0].tiling_flags == 0) 358 tex_res.array_mode = 1; 359 evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); 360 361 /* Y sampler */ 362 tex_samp.id = 0; 363 tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL; 364 tex_samp.clamp_y = SQ_TEX_CLAMP_LAST_TEXEL; 365 tex_samp.clamp_z = SQ_TEX_WRAP; 366 367 tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_BILINEAR; 368 tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_BILINEAR; 369 370 tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE; 371 tex_samp.mip_filter = 0; /* no mipmap */ 372 evergreen_set_tex_sampler(pScrn, &tex_samp); 373 374 /* UV texture */ 375 tex_res.id = 1; 376 tex_res.format = FMT_8_8_8_8; 377 tex_res.w = accel_state->src_obj[0].width >> 1; 378 tex_res.h = accel_state->src_obj[0].height; 379 tex_res.pitch = accel_state->src_obj[0].pitch >> 2; 380 if (pPriv->id == FOURCC_UYVY) { 381 tex_res.dst_sel_x = SQ_SEL_X; /* V */ 382 tex_res.dst_sel_y = SQ_SEL_Z; /* U */ 383 } else { 384 tex_res.dst_sel_x = SQ_SEL_Y; /* V */ 385 tex_res.dst_sel_y = SQ_SEL_W; /* U */ 386 } 387 tex_res.dst_sel_z = SQ_SEL_1; 388 tex_res.dst_sel_w = SQ_SEL_1; 389 tex_res.interlaced = 0; 390 391 tex_res.base = accel_state->src_obj[0].offset; 392 tex_res.mip_base = accel_state->src_obj[0].offset; 393 tex_res.size = accel_state->src_size[0]; 394 if (accel_state->src_obj[0].tiling_flags == 0) 395 tex_res.array_mode = 1; 396 evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); 397 398 /* UV sampler */ 399 tex_samp.id = 1; 400 evergreen_set_tex_sampler(pScrn, &tex_samp); 401 break; 402 } 403 404 cb_conf.id = 0; 405 cb_conf.w = accel_state->dst_obj.pitch; 406 cb_conf.h = accel_state->dst_obj.height; 407 cb_conf.base = accel_state->dst_obj.offset; 408 cb_conf.bo = accel_state->dst_obj.bo; 409 410 switch (accel_state->dst_obj.bpp) { 411 case 16: 412 if (pPixmap->drawable.depth == 15) { 413 cb_conf.format = COLOR_1_5_5_5; 414 cb_conf.comp_swap = 1; /* ARGB */ 415 } else { 416 cb_conf.format = COLOR_5_6_5; 417 cb_conf.comp_swap = 2; /* RGB */ 418 } 419#if X_BYTE_ORDER == X_BIG_ENDIAN 420 cb_conf.endian = ENDIAN_8IN16; 421#endif 422 break; 423 case 32: 424 cb_conf.format = COLOR_8_8_8_8; 425 cb_conf.comp_swap = 1; /* ARGB */ 426#if X_BYTE_ORDER == X_BIG_ENDIAN 427 cb_conf.endian = ENDIAN_8IN32; 428#endif 429 break; 430 default: 431 return; 432 } 433 434 cb_conf.source_format = EXPORT_4C_16BPC; 435 cb_conf.blend_clamp = 1; 436 cb_conf.pmask = 0xf; 437 cb_conf.rop = 3; 438 if (accel_state->dst_obj.tiling_flags == 0) { 439 cb_conf.array_mode = 1; 440 cb_conf.non_disp_tiling = 1; 441 } 442 evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain); 443 444 evergreen_set_spi(pScrn, (1 - 1), 1); 445 446 /* PS alu constants */ 447 ps_const_conf.size_bytes = 256; 448 ps_const_conf.type = SHADER_TYPE_PS; 449 ps_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256); 450 ps_const_conf.bo = accel_state->cbuf.vb_bo; 451 ps_const_conf.const_addr = accel_state->cbuf.vb_mc_addr + accel_state->cbuf.vb_offset; 452 453 ps_alu_consts[0] = off[0]; 454 ps_alu_consts[1] = off[1]; 455 ps_alu_consts[2] = off[2]; 456 ps_alu_consts[3] = yco; 457 458 ps_alu_consts[4] = uco[0]; 459 ps_alu_consts[5] = uco[1]; 460 ps_alu_consts[6] = uco[2]; 461 ps_alu_consts[7] = gamma; 462 463 ps_alu_consts[8] = vco[0]; 464 ps_alu_consts[9] = vco[1]; 465 ps_alu_consts[10] = vco[2]; 466 ps_alu_consts[11] = 0.0; 467 468 radeon_vbo_commit(pScrn, &accel_state->cbuf); 469 evergreen_set_alu_consts(pScrn, &ps_const_conf, RADEON_GEM_DOMAIN_GTT); 470 471 /* VS alu constants */ 472 vs_const_conf.size_bytes = 256; 473 vs_const_conf.type = SHADER_TYPE_VS; 474 vs_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256); 475 vs_const_conf.bo = accel_state->cbuf.vb_bo; 476 vs_const_conf.const_addr = accel_state->cbuf.vb_mc_addr + accel_state->cbuf.vb_offset; 477 478 vs_alu_consts[0] = 1.0 / pPriv->w; 479 vs_alu_consts[1] = 1.0 / pPriv->h; 480 vs_alu_consts[2] = 0.0; 481 vs_alu_consts[3] = 0.0; 482 483 radeon_vbo_commit(pScrn, &accel_state->cbuf); 484 evergreen_set_alu_consts(pScrn, &vs_const_conf, RADEON_GEM_DOMAIN_GTT); 485 486 if (pPriv->vsync) { 487 xf86CrtcPtr crtc; 488 if (pPriv->desired_crtc) 489 crtc = pPriv->desired_crtc; 490 else 491 crtc = radeon_pick_best_crtc(pScrn, 492 pPriv->drw_x, 493 pPriv->drw_x + pPriv->dst_w, 494 pPriv->drw_y, 495 pPriv->drw_y + pPriv->dst_h); 496 if (crtc) 497 evergreen_cp_wait_vline_sync(pScrn, pPixmap, 498 crtc, 499 pPriv->drw_y - crtc->y, 500 (pPriv->drw_y - crtc->y) + pPriv->dst_h); 501 } 502 503 while (nBox--) { 504 int srcX, srcY, srcw, srch; 505 int dstX, dstY, dstw, dsth; 506 float *vb; 507 508 509 dstX = pBox->x1 + dstxoff; 510 dstY = pBox->y1 + dstyoff; 511 dstw = pBox->x2 - pBox->x1; 512 dsth = pBox->y2 - pBox->y1; 513 514 srcX = pPriv->src_x; 515 srcX += ((pBox->x1 - pPriv->drw_x) * 516 pPriv->src_w) / pPriv->dst_w; 517 srcY = pPriv->src_y; 518 srcY += ((pBox->y1 - pPriv->drw_y) * 519 pPriv->src_h) / pPriv->dst_h; 520 521 srcw = (pPriv->src_w * dstw) / pPriv->dst_w; 522 srch = (pPriv->src_h * dsth) / pPriv->dst_h; 523 524 vb = radeon_vbo_space(pScrn, &accel_state->vbo, 16); 525 526 vb[0] = (float)dstX; 527 vb[1] = (float)dstY; 528 vb[2] = (float)srcX; 529 vb[3] = (float)srcY; 530 531 vb[4] = (float)dstX; 532 vb[5] = (float)(dstY + dsth); 533 vb[6] = (float)srcX; 534 vb[7] = (float)(srcY + srch); 535 536 vb[8] = (float)(dstX + dstw); 537 vb[9] = (float)(dstY + dsth); 538 vb[10] = (float)(srcX + srcw); 539 vb[11] = (float)(srcY + srch); 540 541 radeon_vbo_commit(pScrn, &accel_state->vbo); 542 543 pBox++; 544 } 545 546 evergreen_finish_op(pScrn, 16); 547 548 DamageDamageRegion(pPriv->pDraw, &pPriv->clip); 549} 550 551#endif 552