r6xx_accel.c revision cea7510d
1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: Alex Deucher <alexander.deucher@amd.com> 24 * Matthias Hopf <mhopf@suse.de> 25 */ 26#ifdef HAVE_CONFIG_H 27#include "config.h" 28#endif 29 30#include "xf86.h" 31 32#include <errno.h> 33 34#include "radeon.h" 35#include "r600_shader.h" 36#include "radeon_reg.h" 37#include "r600_reg.h" 38#include "r600_state.h" 39 40#include "radeon_drm.h" 41#include "radeon_vbo.h" 42#include "radeon_exa_shared.h" 43 44static const uint32_t R600_ROP[16] = { 45 RADEON_ROP3_ZERO, /* GXclear */ 46 RADEON_ROP3_DSa, /* Gxand */ 47 RADEON_ROP3_SDna, /* GXandReverse */ 48 RADEON_ROP3_S, /* GXcopy */ 49 RADEON_ROP3_DSna, /* GXandInverted */ 50 RADEON_ROP3_D, /* GXnoop */ 51 RADEON_ROP3_DSx, /* GXxor */ 52 RADEON_ROP3_DSo, /* GXor */ 53 RADEON_ROP3_DSon, /* GXnor */ 54 RADEON_ROP3_DSxn, /* GXequiv */ 55 RADEON_ROP3_Dn, /* GXinvert */ 56 RADEON_ROP3_SDno, /* GXorReverse */ 57 RADEON_ROP3_Sn, /* GXcopyInverted */ 58 RADEON_ROP3_DSno, /* GXorInverted */ 59 RADEON_ROP3_DSan, /* GXnand */ 60 RADEON_ROP3_ONE, /* GXset */ 61}; 62 63/* we try and batch operations together under KMS - 64 but it doesn't work yet without misrendering */ 65#define KMS_MULTI_OP 1 66 67/* Flush the indirect buffer to the kernel for submission to the card */ 68void R600CPFlushIndirect(ScrnInfoPtr pScrn, drmBufPtr ib) 69{ 70 RADEONInfoPtr info = RADEONPTR(pScrn); 71 drmBufPtr buffer = ib; 72 int start = 0; 73 drm_radeon_indirect_t indirect; 74 75#if defined(XF86DRM_MODE) 76 if (info->cs) { 77 radeon_cs_flush_indirect(pScrn); 78 return; 79 } 80#endif 81 82 if (!buffer) return; 83 84 //xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Flushing buffer %d\n", 85 // buffer->idx); 86 87 while (buffer->used & 0x3c){ 88 BEGIN_BATCH(1); 89 E32(buffer, CP_PACKET2()); /* fill up to multiple of 16 dwords */ 90 END_BATCH(); 91 } 92 93 info->accel_state->vbo.vb_offset = 0; 94 info->accel_state->vbo.vb_start_op = -1; 95 96 //ErrorF("buffer bytes: %d\n", buffer->used); 97 98 indirect.idx = buffer->idx; 99 indirect.start = start; 100 indirect.end = buffer->used; 101 indirect.discard = 1; 102 103 drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INDIRECT, 104 &indirect, sizeof(drm_radeon_indirect_t)); 105 106} 107 108void R600IBDiscard(ScrnInfoPtr pScrn, drmBufPtr ib) 109{ 110#if defined(XF86DRM_MODE) 111 RADEONInfoPtr info = RADEONPTR(pScrn); 112 if (info->cs) { 113 radeon_ib_discard(pScrn); 114 } 115#endif 116 if (!ib) return; 117 118 ib->used = 0; 119 R600CPFlushIndirect(pScrn, ib); 120} 121 122void 123r600_wait_3d_idle_clean(ScrnInfoPtr pScrn, drmBufPtr ib) 124{ 125 RADEONInfoPtr info = RADEONPTR(pScrn); 126 127 //flush caches, don't generate timestamp 128 BEGIN_BATCH(5); 129 PACK3(ib, IT_EVENT_WRITE, 1); 130 E32(ib, CACHE_FLUSH_AND_INV_EVENT); 131 // wait for 3D idle clean 132 EREG(ib, WAIT_UNTIL, (WAIT_3D_IDLE_bit | 133 WAIT_3D_IDLECLEAN_bit)); 134 END_BATCH(); 135} 136 137void 138r600_wait_3d_idle(ScrnInfoPtr pScrn, drmBufPtr ib) 139{ 140 RADEONInfoPtr info = RADEONPTR(pScrn); 141 142 BEGIN_BATCH(3); 143 EREG(ib, WAIT_UNTIL, WAIT_3D_IDLE_bit); 144 END_BATCH(); 145} 146 147void 148r600_start_3d(ScrnInfoPtr pScrn, drmBufPtr ib) 149{ 150 RADEONInfoPtr info = RADEONPTR(pScrn); 151 152 if (info->ChipFamily < CHIP_FAMILY_RV770) { 153 BEGIN_BATCH(5); 154 PACK3(ib, IT_START_3D_CMDBUF, 1); 155 E32(ib, 0); 156 } else 157 BEGIN_BATCH(3); 158 159 PACK3(ib, IT_CONTEXT_CONTROL, 2); 160 E32(ib, 0x80000000); 161 E32(ib, 0x80000000); 162 END_BATCH(); 163 164} 165 166/* 167 * Setup of functional groups 168 */ 169 170// asic stack/thread/gpr limits - need to query the drm 171static void 172r600_sq_setup(ScrnInfoPtr pScrn, drmBufPtr ib, sq_config_t *sq_conf) 173{ 174 uint32_t sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; 175 uint32_t sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2; 176 RADEONInfoPtr info = RADEONPTR(pScrn); 177 178 if ((info->ChipFamily == CHIP_FAMILY_RV610) || 179 (info->ChipFamily == CHIP_FAMILY_RV620) || 180 (info->ChipFamily == CHIP_FAMILY_RS780) || 181 (info->ChipFamily == CHIP_FAMILY_RS880) || 182 (info->ChipFamily == CHIP_FAMILY_RV710)) 183 sq_config = 0; // no VC 184 else 185 sq_config = VC_ENABLE_bit; 186 187 sq_config |= (DX9_CONSTS_bit | 188 ALU_INST_PREFER_VECTOR_bit | 189 (sq_conf->ps_prio << PS_PRIO_shift) | 190 (sq_conf->vs_prio << VS_PRIO_shift) | 191 (sq_conf->gs_prio << GS_PRIO_shift) | 192 (sq_conf->es_prio << ES_PRIO_shift)); 193 194 sq_gpr_resource_mgmt_1 = ((sq_conf->num_ps_gprs << NUM_PS_GPRS_shift) | 195 (sq_conf->num_vs_gprs << NUM_VS_GPRS_shift) | 196 (sq_conf->num_temp_gprs << NUM_CLAUSE_TEMP_GPRS_shift)); 197 sq_gpr_resource_mgmt_2 = ((sq_conf->num_gs_gprs << NUM_GS_GPRS_shift) | 198 (sq_conf->num_es_gprs << NUM_ES_GPRS_shift)); 199 200 sq_thread_resource_mgmt = ((sq_conf->num_ps_threads << NUM_PS_THREADS_shift) | 201 (sq_conf->num_vs_threads << NUM_VS_THREADS_shift) | 202 (sq_conf->num_gs_threads << NUM_GS_THREADS_shift) | 203 (sq_conf->num_es_threads << NUM_ES_THREADS_shift)); 204 205 sq_stack_resource_mgmt_1 = ((sq_conf->num_ps_stack_entries << NUM_PS_STACK_ENTRIES_shift) | 206 (sq_conf->num_vs_stack_entries << NUM_VS_STACK_ENTRIES_shift)); 207 208 sq_stack_resource_mgmt_2 = ((sq_conf->num_gs_stack_entries << NUM_GS_STACK_ENTRIES_shift) | 209 (sq_conf->num_es_stack_entries << NUM_ES_STACK_ENTRIES_shift)); 210 211 BEGIN_BATCH(8); 212 PACK0(ib, SQ_CONFIG, 6); 213 E32(ib, sq_config); 214 E32(ib, sq_gpr_resource_mgmt_1); 215 E32(ib, sq_gpr_resource_mgmt_2); 216 E32(ib, sq_thread_resource_mgmt); 217 E32(ib, sq_stack_resource_mgmt_1); 218 E32(ib, sq_stack_resource_mgmt_2); 219 END_BATCH(); 220} 221 222void 223r600_set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_t domain) 224{ 225 uint32_t cb_color_info, cb_color_control; 226 int pitch, slice, h; 227 RADEONInfoPtr info = RADEONPTR(pScrn); 228 229 cb_color_info = ((cb_conf->endian << ENDIAN_shift) | 230 (cb_conf->format << CB_COLOR0_INFO__FORMAT_shift) | 231 (cb_conf->array_mode << CB_COLOR0_INFO__ARRAY_MODE_shift) | 232 (cb_conf->number_type << NUMBER_TYPE_shift) | 233 (cb_conf->comp_swap << COMP_SWAP_shift) | 234 (cb_conf->tile_mode << CB_COLOR0_INFO__TILE_MODE_shift)); 235 if (cb_conf->read_size) 236 cb_color_info |= CB_COLOR0_INFO__READ_SIZE_bit; 237 if (cb_conf->blend_clamp) 238 cb_color_info |= BLEND_CLAMP_bit; 239 if (cb_conf->clear_color) 240 cb_color_info |= CLEAR_COLOR_bit; 241 if (cb_conf->blend_bypass) 242 cb_color_info |= BLEND_BYPASS_bit; 243 if (cb_conf->blend_float32) 244 cb_color_info |= BLEND_FLOAT32_bit; 245 if (cb_conf->simple_float) 246 cb_color_info |= SIMPLE_FLOAT_bit; 247 if (cb_conf->round_mode) 248 cb_color_info |= CB_COLOR0_INFO__ROUND_MODE_bit; 249 if (cb_conf->tile_compact) 250 cb_color_info |= TILE_COMPACT_bit; 251 if (cb_conf->source_format) 252 cb_color_info |= SOURCE_FORMAT_bit; 253 254 pitch = (cb_conf->w / 8) - 1; 255 h = RADEON_ALIGN(cb_conf->h, 8); 256 slice = ((cb_conf->w * h) / 64) - 1; 257 258 BEGIN_BATCH(3 + 2); 259 EREG(ib, (CB_COLOR0_BASE + (4 * cb_conf->id)), (cb_conf->base >> 8)); 260 RELOC_BATCH(cb_conf->bo, 0, domain); 261 END_BATCH(); 262 263 // rv6xx workaround 264 if ((info->ChipFamily > CHIP_FAMILY_R600) && 265 (info->ChipFamily < CHIP_FAMILY_RV770)) { 266 BEGIN_BATCH(2); 267 PACK3(ib, IT_SURFACE_BASE_UPDATE, 1); 268 E32(ib, (2 << cb_conf->id)); 269 END_BATCH(); 270 } 271 /* Set CMASK & TILE buffer to the offset of color buffer as 272 * we don't use those this shouldn't cause any issue and we 273 * then have a valid cmd stream 274 */ 275 BEGIN_BATCH(3 + 2); 276 EREG(ib, (CB_COLOR0_TILE + (4 * cb_conf->id)), (0 >> 8)); // CMASK per-tile data base/256 277 RELOC_BATCH(cb_conf->bo, 0, domain); 278 END_BATCH(); 279 BEGIN_BATCH(3 + 2); 280 EREG(ib, (CB_COLOR0_FRAG + (4 * cb_conf->id)), (0 >> 8)); // FMASK per-tile data base/256 281 RELOC_BATCH(cb_conf->bo, 0, domain); 282 END_BATCH(); 283 BEGIN_BATCH(9); 284 // pitch only for ARRAY_LINEAR_GENERAL, other tiling modes require addrlib 285 EREG(ib, (CB_COLOR0_SIZE + (4 * cb_conf->id)), ((pitch << PITCH_TILE_MAX_shift) | 286 (slice << SLICE_TILE_MAX_shift))); 287 EREG(ib, (CB_COLOR0_VIEW + (4 * cb_conf->id)), ((0 << SLICE_START_shift) | 288 (0 << SLICE_MAX_shift))); 289 EREG(ib, (CB_COLOR0_MASK + (4 * cb_conf->id)), ((0 << CMASK_BLOCK_MAX_shift) | 290 (0 << FMASK_TILE_MAX_shift))); 291 END_BATCH(); 292 293 BEGIN_BATCH(3 + 2); 294 EREG(ib, (CB_COLOR0_INFO + (4 * cb_conf->id)), cb_color_info); 295 RELOC_BATCH(cb_conf->bo, 0, domain); 296 END_BATCH(); 297 298 BEGIN_BATCH(9); 299 EREG(ib, CB_TARGET_MASK, (cb_conf->pmask << TARGET0_ENABLE_shift)); 300 cb_color_control = R600_ROP[cb_conf->rop] | 301 (cb_conf->blend_enable << TARGET_BLEND_ENABLE_shift); 302 if (info->ChipFamily == CHIP_FAMILY_R600) { 303 /* no per-MRT blend on R600 */ 304 EREG(ib, CB_COLOR_CONTROL, cb_color_control); 305 EREG(ib, CB_BLEND_CONTROL, cb_conf->blendcntl); 306 } else { 307 if (cb_conf->blend_enable) 308 cb_color_control |= PER_MRT_BLEND_bit; 309 EREG(ib, CB_COLOR_CONTROL, cb_color_control); 310 EREG(ib, CB_BLEND0_CONTROL, cb_conf->blendcntl); 311 } 312 END_BATCH(); 313} 314 315static void 316r600_cp_set_surface_sync(ScrnInfoPtr pScrn, drmBufPtr ib, uint32_t sync_type, 317 uint32_t size, uint64_t mc_addr, 318 struct radeon_bo *bo, uint32_t rdomains, uint32_t wdomain) 319{ 320 RADEONInfoPtr info = RADEONPTR(pScrn); 321 uint32_t cp_coher_size; 322 if (size == 0xffffffff) 323 cp_coher_size = 0xffffffff; 324 else 325 cp_coher_size = ((size + 255) >> 8); 326 327 BEGIN_BATCH(5 + 2); 328 PACK3(ib, IT_SURFACE_SYNC, 4); 329 E32(ib, sync_type); 330 E32(ib, cp_coher_size); 331 E32(ib, (mc_addr >> 8)); 332 E32(ib, 10); /* poll interval */ 333 RELOC_BATCH(bo, rdomains, wdomain); 334 END_BATCH(); 335} 336 337/* inserts a wait for vline in the command stream */ 338void 339r600_cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix, 340 xf86CrtcPtr crtc, int start, int stop) 341{ 342 RADEONInfoPtr info = RADEONPTR(pScrn); 343 uint32_t offset; 344 345 if (!crtc) 346 return; 347 348 if (stop < start) 349 return; 350 351 if (!crtc->enabled) 352 return; 353 354 if (info->cs) { 355 if (pPix != pScrn->pScreen->GetScreenPixmap(pScrn->pScreen)) 356 return; 357 } else { 358#ifdef USE_EXA 359 if (info->useEXA) 360 offset = exaGetPixmapOffset(pPix); 361 else 362#endif 363 offset = pPix->devPrivate.ptr - info->FB; 364 365 /* if drawing to front buffer */ 366 if (offset != 0) 367 return; 368 } 369 370 start = max(start, 0); 371 stop = min(stop, crtc->mode.VDisplay); 372 373 if (start > crtc->mode.VDisplay) 374 return; 375 376#if defined(XF86DRM_MODE) 377 if (info->cs) { 378 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 379 380 BEGIN_BATCH(11); 381 /* set the VLINE range */ 382 EREG(ib, AVIVO_D1MODE_VLINE_START_END, /* this is just a marker */ 383 (start << AVIVO_D1MODE_VLINE_START_SHIFT) | 384 (stop << AVIVO_D1MODE_VLINE_END_SHIFT)); 385 386 /* tell the CP to poll the VLINE state register */ 387 PACK3(ib, IT_WAIT_REG_MEM, 6); 388 E32(ib, IT_WAIT_REG | IT_WAIT_EQ); 389 E32(ib, IT_WAIT_ADDR(AVIVO_D1MODE_VLINE_STATUS)); 390 E32(ib, 0); 391 E32(ib, 0); // Ref value 392 E32(ib, AVIVO_D1MODE_VLINE_STAT); // Mask 393 E32(ib, 10); // Wait interval 394 /* add crtc reloc */ 395 PACK3(ib, IT_NOP, 1); 396 E32(ib, drmmode_crtc->mode_crtc->crtc_id); 397 END_BATCH(); 398 } else 399#endif 400 { 401 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 402 403 BEGIN_BATCH(9); 404 /* set the VLINE range */ 405 EREG(ib, AVIVO_D1MODE_VLINE_START_END + radeon_crtc->crtc_offset, 406 (start << AVIVO_D1MODE_VLINE_START_SHIFT) | 407 (stop << AVIVO_D1MODE_VLINE_END_SHIFT)); 408 409 /* tell the CP to poll the VLINE state register */ 410 PACK3(ib, IT_WAIT_REG_MEM, 6); 411 E32(ib, IT_WAIT_REG | IT_WAIT_EQ); 412 E32(ib, IT_WAIT_ADDR(AVIVO_D1MODE_VLINE_STATUS + radeon_crtc->crtc_offset)); 413 E32(ib, 0); 414 E32(ib, 0); // Ref value 415 E32(ib, AVIVO_D1MODE_VLINE_STAT); // Mask 416 E32(ib, 10); // Wait interval 417 END_BATCH(); 418 } 419} 420 421void 422r600_set_spi(ScrnInfoPtr pScrn, drmBufPtr ib, int vs_export_count, int num_interp) 423{ 424 RADEONInfoPtr info = RADEONPTR(pScrn); 425 426 BEGIN_BATCH(8); 427 /* Interpolator setup */ 428 EREG(ib, SPI_VS_OUT_CONFIG, (vs_export_count << VS_EXPORT_COUNT_shift)); 429 PACK0(ib, SPI_PS_IN_CONTROL_0, 3); 430 E32(ib, (num_interp << NUM_INTERP_shift)); 431 E32(ib, 0); 432 E32(ib, 0); 433 END_BATCH(); 434} 435 436void 437r600_fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf, uint32_t domain) 438{ 439 RADEONInfoPtr info = RADEONPTR(pScrn); 440 uint32_t sq_pgm_resources; 441 442 sq_pgm_resources = ((fs_conf->num_gprs << NUM_GPRS_shift) | 443 (fs_conf->stack_size << STACK_SIZE_shift)); 444 445 if (fs_conf->dx10_clamp) 446 sq_pgm_resources |= SQ_PGM_RESOURCES_FS__DX10_CLAMP_bit; 447 448 BEGIN_BATCH(3 + 2); 449 EREG(ib, SQ_PGM_START_FS, fs_conf->shader_addr >> 8); 450 RELOC_BATCH(fs_conf->bo, domain, 0); 451 END_BATCH(); 452 453 BEGIN_BATCH(6); 454 EREG(ib, SQ_PGM_RESOURCES_FS, sq_pgm_resources); 455 EREG(ib, SQ_PGM_CF_OFFSET_FS, 0); 456 END_BATCH(); 457} 458 459void 460r600_vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf, uint32_t domain) 461{ 462 RADEONInfoPtr info = RADEONPTR(pScrn); 463 uint32_t sq_pgm_resources; 464 465 sq_pgm_resources = ((vs_conf->num_gprs << NUM_GPRS_shift) | 466 (vs_conf->stack_size << STACK_SIZE_shift)); 467 468 if (vs_conf->dx10_clamp) 469 sq_pgm_resources |= SQ_PGM_RESOURCES_VS__DX10_CLAMP_bit; 470 if (vs_conf->fetch_cache_lines) 471 sq_pgm_resources |= (vs_conf->fetch_cache_lines << FETCH_CACHE_LINES_shift); 472 if (vs_conf->uncached_first_inst) 473 sq_pgm_resources |= UNCACHED_FIRST_INST_bit; 474 475 /* flush SQ cache */ 476 r600_cp_set_surface_sync(pScrn, ib, SH_ACTION_ENA_bit, 477 vs_conf->shader_size, vs_conf->shader_addr, 478 vs_conf->bo, domain, 0); 479 480 BEGIN_BATCH(3 + 2); 481 EREG(ib, SQ_PGM_START_VS, vs_conf->shader_addr >> 8); 482 RELOC_BATCH(vs_conf->bo, domain, 0); 483 END_BATCH(); 484 485 BEGIN_BATCH(6); 486 EREG(ib, SQ_PGM_RESOURCES_VS, sq_pgm_resources); 487 EREG(ib, SQ_PGM_CF_OFFSET_VS, 0); 488 END_BATCH(); 489} 490 491void 492r600_ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf, uint32_t domain) 493{ 494 RADEONInfoPtr info = RADEONPTR(pScrn); 495 uint32_t sq_pgm_resources; 496 497 sq_pgm_resources = ((ps_conf->num_gprs << NUM_GPRS_shift) | 498 (ps_conf->stack_size << STACK_SIZE_shift)); 499 500 if (ps_conf->dx10_clamp) 501 sq_pgm_resources |= SQ_PGM_RESOURCES_PS__DX10_CLAMP_bit; 502 if (ps_conf->fetch_cache_lines) 503 sq_pgm_resources |= (ps_conf->fetch_cache_lines << FETCH_CACHE_LINES_shift); 504 if (ps_conf->uncached_first_inst) 505 sq_pgm_resources |= UNCACHED_FIRST_INST_bit; 506 if (ps_conf->clamp_consts) 507 sq_pgm_resources |= CLAMP_CONSTS_bit; 508 509 /* flush SQ cache */ 510 r600_cp_set_surface_sync(pScrn, ib, SH_ACTION_ENA_bit, 511 ps_conf->shader_size, ps_conf->shader_addr, 512 ps_conf->bo, domain, 0); 513 514 BEGIN_BATCH(3 + 2); 515 EREG(ib, SQ_PGM_START_PS, ps_conf->shader_addr >> 8); 516 RELOC_BATCH(ps_conf->bo, domain, 0); 517 END_BATCH(); 518 519 BEGIN_BATCH(9); 520 EREG(ib, SQ_PGM_RESOURCES_PS, sq_pgm_resources); 521 EREG(ib, SQ_PGM_EXPORTS_PS, ps_conf->export_mode); 522 EREG(ib, SQ_PGM_CF_OFFSET_PS, 0); 523 END_BATCH(); 524} 525 526void 527r600_set_alu_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, int count, float *const_buf) 528{ 529 RADEONInfoPtr info = RADEONPTR(pScrn); 530 int i; 531 const int countreg = count * (SQ_ALU_CONSTANT_offset >> 2); 532 533 BEGIN_BATCH(2 + countreg); 534 PACK0(ib, SQ_ALU_CONSTANT + offset * SQ_ALU_CONSTANT_offset, countreg); 535 for (i = 0; i < countreg; i++) 536 EFLOAT(ib, const_buf[i]); 537 END_BATCH(); 538} 539 540void 541r600_set_bool_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val) 542{ 543 RADEONInfoPtr info = RADEONPTR(pScrn); 544 /* bool register order is: ps, vs, gs; one register each 545 * 1 bits per bool; 32 bools each for ps, vs, gs. 546 */ 547 BEGIN_BATCH(3); 548 EREG(ib, SQ_BOOL_CONST + offset * SQ_BOOL_CONST_offset, val); 549 END_BATCH(); 550} 551 552static void 553r600_set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res, uint32_t domain) 554{ 555 RADEONInfoPtr info = RADEONPTR(pScrn); 556 struct radeon_accel_state *accel_state = info->accel_state; 557 uint32_t sq_vtx_constant_word2; 558 559 sq_vtx_constant_word2 = ((((res->vb_addr) >> 32) & BASE_ADDRESS_HI_mask) | 560 ((res->vtx_size_dw << 2) << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift) | 561 (res->format << SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift) | 562 (res->num_format_all << SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift) | 563 (res->endian << SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift)); 564 if (res->clamp_x) 565 sq_vtx_constant_word2 |= SQ_VTX_CONSTANT_WORD2_0__CLAMP_X_bit; 566 567 if (res->format_comp_all) 568 sq_vtx_constant_word2 |= SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit; 569 570 if (res->srf_mode_all) 571 sq_vtx_constant_word2 |= SQ_VTX_CONSTANT_WORD2_0__SRF_MODE_ALL_bit; 572 573 /* flush vertex cache */ 574 if ((info->ChipFamily == CHIP_FAMILY_RV610) || 575 (info->ChipFamily == CHIP_FAMILY_RV620) || 576 (info->ChipFamily == CHIP_FAMILY_RS780) || 577 (info->ChipFamily == CHIP_FAMILY_RS880) || 578 (info->ChipFamily == CHIP_FAMILY_RV710)) 579 r600_cp_set_surface_sync(pScrn, ib, TC_ACTION_ENA_bit, 580 accel_state->vbo.vb_offset, accel_state->vbo.vb_mc_addr, 581 res->bo, 582 domain, 0); 583 else 584 r600_cp_set_surface_sync(pScrn, ib, VC_ACTION_ENA_bit, 585 accel_state->vbo.vb_offset, accel_state->vbo.vb_mc_addr, 586 res->bo, 587 domain, 0); 588 589 BEGIN_BATCH(9 + 2); 590 PACK0(ib, SQ_VTX_RESOURCE + res->id * SQ_VTX_RESOURCE_offset, 7); 591 E32(ib, res->vb_addr & 0xffffffff); // 0: BASE_ADDRESS 592 E32(ib, (res->vtx_num_entries << 2) - 1); // 1: SIZE 593 E32(ib, sq_vtx_constant_word2); // 2: BASE_HI, STRIDE, CLAMP, FORMAT, ENDIAN 594 E32(ib, res->mem_req_size << MEM_REQUEST_SIZE_shift); // 3: MEM_REQUEST_SIZE ?!? 595 E32(ib, 0); // 4: n/a 596 E32(ib, 0); // 5: n/a 597 E32(ib, SQ_TEX_VTX_VALID_BUFFER << SQ_VTX_CONSTANT_WORD6_0__TYPE_shift); // 6: TYPE 598 RELOC_BATCH(res->bo, domain, 0); 599 END_BATCH(); 600} 601 602void 603r600_set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res, uint32_t domain) 604{ 605 RADEONInfoPtr info = RADEONPTR(pScrn); 606 uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4; 607 uint32_t sq_tex_resource_word5, sq_tex_resource_word6; 608 609 sq_tex_resource_word0 = ((tex_res->dim << DIM_shift) | 610 (tex_res->tile_mode << SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift)); 611 612 if (tex_res->w) 613 sq_tex_resource_word0 |= (((((tex_res->pitch + 7) >> 3) - 1) << PITCH_shift) | 614 ((tex_res->w - 1) << TEX_WIDTH_shift)); 615 616 if (tex_res->tile_type) 617 sq_tex_resource_word0 |= TILE_TYPE_bit; 618 619 sq_tex_resource_word1 = (tex_res->format << SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift); 620 621 if (tex_res->h) 622 sq_tex_resource_word1 |= ((tex_res->h - 1) << TEX_HEIGHT_shift); 623 if (tex_res->depth) 624 sq_tex_resource_word1 |= ((tex_res->depth - 1) << TEX_DEPTH_shift); 625 626 sq_tex_resource_word4 = ((tex_res->format_comp_x << FORMAT_COMP_X_shift) | 627 (tex_res->format_comp_y << FORMAT_COMP_Y_shift) | 628 (tex_res->format_comp_z << FORMAT_COMP_Z_shift) | 629 (tex_res->format_comp_w << FORMAT_COMP_W_shift) | 630 (tex_res->num_format_all << SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_shift) | 631 (tex_res->endian << SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_shift) | 632 (tex_res->request_size << REQUEST_SIZE_shift) | 633 (tex_res->dst_sel_x << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift) | 634 (tex_res->dst_sel_y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift) | 635 (tex_res->dst_sel_z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift) | 636 (tex_res->dst_sel_w << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift) | 637 (tex_res->base_level << BASE_LEVEL_shift)); 638 639 if (tex_res->srf_mode_all) 640 sq_tex_resource_word4 |= SQ_TEX_RESOURCE_WORD4_0__SRF_MODE_ALL_bit; 641 if (tex_res->force_degamma) 642 sq_tex_resource_word4 |= SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit; 643 644 sq_tex_resource_word5 = ((tex_res->last_level << LAST_LEVEL_shift) | 645 (tex_res->base_array << BASE_ARRAY_shift) | 646 (tex_res->last_array << LAST_ARRAY_shift)); 647 648 sq_tex_resource_word6 = ((tex_res->mpeg_clamp << MPEG_CLAMP_shift) | 649 (tex_res->perf_modulation << PERF_MODULATION_shift) | 650 (SQ_TEX_VTX_VALID_TEXTURE << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift)); 651 652 if (tex_res->interlaced) 653 sq_tex_resource_word6 |= INTERLACED_bit; 654 655 /* flush texture cache */ 656 r600_cp_set_surface_sync(pScrn, ib, TC_ACTION_ENA_bit, 657 tex_res->size, tex_res->base, 658 tex_res->bo, domain, 0); 659 660 BEGIN_BATCH(9 + 4); 661 PACK0(ib, SQ_TEX_RESOURCE + tex_res->id * SQ_TEX_RESOURCE_offset, 7); 662 E32(ib, sq_tex_resource_word0); 663 E32(ib, sq_tex_resource_word1); 664 E32(ib, ((tex_res->base) >> 8)); 665 E32(ib, ((tex_res->mip_base) >> 8)); 666 E32(ib, sq_tex_resource_word4); 667 E32(ib, sq_tex_resource_word5); 668 E32(ib, sq_tex_resource_word6); 669 RELOC_BATCH(tex_res->bo, domain, 0); 670 RELOC_BATCH(tex_res->mip_bo, domain, 0); 671 END_BATCH(); 672} 673 674void 675r600_set_tex_sampler (ScrnInfoPtr pScrn, drmBufPtr ib, tex_sampler_t *s) 676{ 677 RADEONInfoPtr info = RADEONPTR(pScrn); 678 uint32_t sq_tex_sampler_word0, sq_tex_sampler_word1, sq_tex_sampler_word2; 679 680 sq_tex_sampler_word0 = ((s->clamp_x << SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift) | 681 (s->clamp_y << CLAMP_Y_shift) | 682 (s->clamp_z << CLAMP_Z_shift) | 683 (s->xy_mag_filter << XY_MAG_FILTER_shift) | 684 (s->xy_min_filter << XY_MIN_FILTER_shift) | 685 (s->z_filter << Z_FILTER_shift) | 686 (s->mip_filter << MIP_FILTER_shift) | 687 (s->border_color << BORDER_COLOR_TYPE_shift) | 688 (s->depth_compare << DEPTH_COMPARE_FUNCTION_shift) | 689 (s->chroma_key << CHROMA_KEY_shift)); 690 if (s->point_sampling_clamp) 691 sq_tex_sampler_word0 |= POINT_SAMPLING_CLAMP_bit; 692 if (s->tex_array_override) 693 sq_tex_sampler_word0 |= TEX_ARRAY_OVERRIDE_bit; 694 if (s->lod_uses_minor_axis) 695 sq_tex_sampler_word0 |= LOD_USES_MINOR_AXIS_bit; 696 697 sq_tex_sampler_word1 = ((s->min_lod << MIN_LOD_shift) | 698 (s->max_lod << MAX_LOD_shift) | 699 (s->lod_bias << SQ_TEX_SAMPLER_WORD1_0__LOD_BIAS_shift)); 700 701 sq_tex_sampler_word2 = ((s->lod_bias2 << LOD_BIAS_SEC_shift) | 702 (s->perf_mip << PERF_MIP_shift) | 703 (s->perf_z << PERF_Z_shift)); 704 if (s->mc_coord_truncate) 705 sq_tex_sampler_word2 |= MC_COORD_TRUNCATE_bit; 706 if (s->force_degamma) 707 sq_tex_sampler_word2 |= SQ_TEX_SAMPLER_WORD2_0__FORCE_DEGAMMA_bit; 708 if (s->high_precision_filter) 709 sq_tex_sampler_word2 |= HIGH_PRECISION_FILTER_bit; 710 if (s->fetch_4) 711 sq_tex_sampler_word2 |= FETCH_4_bit; 712 if (s->sample_is_pcf) 713 sq_tex_sampler_word2 |= SAMPLE_IS_PCF_bit; 714 if (s->type) 715 sq_tex_sampler_word2 |= SQ_TEX_SAMPLER_WORD2_0__TYPE_bit; 716 717 BEGIN_BATCH(5); 718 PACK0(ib, SQ_TEX_SAMPLER_WORD + s->id * SQ_TEX_SAMPLER_WORD_offset, 3); 719 E32(ib, sq_tex_sampler_word0); 720 E32(ib, sq_tex_sampler_word1); 721 E32(ib, sq_tex_sampler_word2); 722 END_BATCH(); 723} 724 725//XXX deal with clip offsets in clip setup 726void 727r600_set_screen_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2) 728{ 729 RADEONInfoPtr info = RADEONPTR(pScrn); 730 731 BEGIN_BATCH(4); 732 PACK0(ib, PA_SC_SCREEN_SCISSOR_TL, 2); 733 E32(ib, ((x1 << PA_SC_SCREEN_SCISSOR_TL__TL_X_shift) | 734 (y1 << PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift))); 735 E32(ib, ((x2 << PA_SC_SCREEN_SCISSOR_BR__BR_X_shift) | 736 (y2 << PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift))); 737 END_BATCH(); 738} 739 740void 741r600_set_vport_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2) 742{ 743 RADEONInfoPtr info = RADEONPTR(pScrn); 744 745 BEGIN_BATCH(4); 746 PACK0(ib, PA_SC_VPORT_SCISSOR_0_TL + id * PA_SC_VPORT_SCISSOR_0_TL_offset, 2); 747 E32(ib, ((x1 << PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift) | 748 (y1 << PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift) | 749 WINDOW_OFFSET_DISABLE_bit)); 750 E32(ib, ((x2 << PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift) | 751 (y2 << PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift))); 752 END_BATCH(); 753} 754 755void 756r600_set_generic_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2) 757{ 758 RADEONInfoPtr info = RADEONPTR(pScrn); 759 760 BEGIN_BATCH(4); 761 PACK0(ib, PA_SC_GENERIC_SCISSOR_TL, 2); 762 E32(ib, ((x1 << PA_SC_GENERIC_SCISSOR_TL__TL_X_shift) | 763 (y1 << PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift) | 764 WINDOW_OFFSET_DISABLE_bit)); 765 E32(ib, ((x2 << PA_SC_GENERIC_SCISSOR_BR__BR_X_shift) | 766 (y2 << PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift))); 767 END_BATCH(); 768} 769 770void 771r600_set_window_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2) 772{ 773 RADEONInfoPtr info = RADEONPTR(pScrn); 774 775 BEGIN_BATCH(4); 776 PACK0(ib, PA_SC_WINDOW_SCISSOR_TL, 2); 777 E32(ib, ((x1 << PA_SC_WINDOW_SCISSOR_TL__TL_X_shift) | 778 (y1 << PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift) | 779 WINDOW_OFFSET_DISABLE_bit)); 780 E32(ib, ((x2 << PA_SC_WINDOW_SCISSOR_BR__BR_X_shift) | 781 (y2 << PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift))); 782 END_BATCH(); 783} 784 785void 786r600_set_clip_rect(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2) 787{ 788 RADEONInfoPtr info = RADEONPTR(pScrn); 789 790 BEGIN_BATCH(4); 791 PACK0(ib, PA_SC_CLIPRECT_0_TL + id * PA_SC_CLIPRECT_0_TL_offset, 2); 792 E32(ib, ((x1 << PA_SC_CLIPRECT_0_TL__TL_X_shift) | 793 (y1 << PA_SC_CLIPRECT_0_TL__TL_Y_shift))); 794 E32(ib, ((x2 << PA_SC_CLIPRECT_0_BR__BR_X_shift) | 795 (y2 << PA_SC_CLIPRECT_0_BR__BR_Y_shift))); 796 END_BATCH(); 797} 798 799/* 800 * Setup of default state 801 */ 802 803void 804r600_set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib) 805{ 806 tex_resource_t tex_res; 807 shader_config_t fs_conf; 808 sq_config_t sq_conf; 809 int i; 810 RADEONInfoPtr info = RADEONPTR(pScrn); 811 struct radeon_accel_state *accel_state = info->accel_state; 812 813 if (accel_state->XInited3D) 814 return; 815 816 memset(&tex_res, 0, sizeof(tex_resource_t)); 817 memset(&fs_conf, 0, sizeof(shader_config_t)); 818 819 accel_state->XInited3D = TRUE; 820 821 r600_start_3d(pScrn, accel_state->ib); 822 823 // SQ 824 sq_conf.ps_prio = 0; 825 sq_conf.vs_prio = 1; 826 sq_conf.gs_prio = 2; 827 sq_conf.es_prio = 3; 828 // need to set stack/thread/gpr limits based on the asic 829 // for now just set them low enough so any card will work 830 // see r600_cp.c in the drm 831 switch (info->ChipFamily) { 832 case CHIP_FAMILY_R600: 833 sq_conf.num_ps_gprs = 192; 834 sq_conf.num_vs_gprs = 56; 835 sq_conf.num_temp_gprs = 4; 836 sq_conf.num_gs_gprs = 0; 837 sq_conf.num_es_gprs = 0; 838 sq_conf.num_ps_threads = 136; 839 sq_conf.num_vs_threads = 48; 840 sq_conf.num_gs_threads = 4; 841 sq_conf.num_es_threads = 4; 842 sq_conf.num_ps_stack_entries = 128; 843 sq_conf.num_vs_stack_entries = 128; 844 sq_conf.num_gs_stack_entries = 0; 845 sq_conf.num_es_stack_entries = 0; 846 break; 847 case CHIP_FAMILY_RV630: 848 case CHIP_FAMILY_RV635: 849 sq_conf.num_ps_gprs = 84; 850 sq_conf.num_vs_gprs = 36; 851 sq_conf.num_temp_gprs = 4; 852 sq_conf.num_gs_gprs = 0; 853 sq_conf.num_es_gprs = 0; 854 sq_conf.num_ps_threads = 144; 855 sq_conf.num_vs_threads = 40; 856 sq_conf.num_gs_threads = 4; 857 sq_conf.num_es_threads = 4; 858 sq_conf.num_ps_stack_entries = 40; 859 sq_conf.num_vs_stack_entries = 40; 860 sq_conf.num_gs_stack_entries = 32; 861 sq_conf.num_es_stack_entries = 16; 862 break; 863 case CHIP_FAMILY_RV610: 864 case CHIP_FAMILY_RV620: 865 case CHIP_FAMILY_RS780: 866 case CHIP_FAMILY_RS880: 867 default: 868 sq_conf.num_ps_gprs = 84; 869 sq_conf.num_vs_gprs = 36; 870 sq_conf.num_temp_gprs = 4; 871 sq_conf.num_gs_gprs = 0; 872 sq_conf.num_es_gprs = 0; 873 sq_conf.num_ps_threads = 136; 874 sq_conf.num_vs_threads = 48; 875 sq_conf.num_gs_threads = 4; 876 sq_conf.num_es_threads = 4; 877 sq_conf.num_ps_stack_entries = 40; 878 sq_conf.num_vs_stack_entries = 40; 879 sq_conf.num_gs_stack_entries = 32; 880 sq_conf.num_es_stack_entries = 16; 881 break; 882 case CHIP_FAMILY_RV670: 883 sq_conf.num_ps_gprs = 144; 884 sq_conf.num_vs_gprs = 40; 885 sq_conf.num_temp_gprs = 4; 886 sq_conf.num_gs_gprs = 0; 887 sq_conf.num_es_gprs = 0; 888 sq_conf.num_ps_threads = 136; 889 sq_conf.num_vs_threads = 48; 890 sq_conf.num_gs_threads = 4; 891 sq_conf.num_es_threads = 4; 892 sq_conf.num_ps_stack_entries = 40; 893 sq_conf.num_vs_stack_entries = 40; 894 sq_conf.num_gs_stack_entries = 32; 895 sq_conf.num_es_stack_entries = 16; 896 break; 897 case CHIP_FAMILY_RV770: 898 sq_conf.num_ps_gprs = 192; 899 sq_conf.num_vs_gprs = 56; 900 sq_conf.num_temp_gprs = 4; 901 sq_conf.num_gs_gprs = 0; 902 sq_conf.num_es_gprs = 0; 903 sq_conf.num_ps_threads = 188; 904 sq_conf.num_vs_threads = 60; 905 sq_conf.num_gs_threads = 0; 906 sq_conf.num_es_threads = 0; 907 sq_conf.num_ps_stack_entries = 256; 908 sq_conf.num_vs_stack_entries = 256; 909 sq_conf.num_gs_stack_entries = 0; 910 sq_conf.num_es_stack_entries = 0; 911 break; 912 case CHIP_FAMILY_RV730: 913 case CHIP_FAMILY_RV740: 914 sq_conf.num_ps_gprs = 84; 915 sq_conf.num_vs_gprs = 36; 916 sq_conf.num_temp_gprs = 4; 917 sq_conf.num_gs_gprs = 0; 918 sq_conf.num_es_gprs = 0; 919 sq_conf.num_ps_threads = 188; 920 sq_conf.num_vs_threads = 60; 921 sq_conf.num_gs_threads = 0; 922 sq_conf.num_es_threads = 0; 923 sq_conf.num_ps_stack_entries = 128; 924 sq_conf.num_vs_stack_entries = 128; 925 sq_conf.num_gs_stack_entries = 0; 926 sq_conf.num_es_stack_entries = 0; 927 break; 928 case CHIP_FAMILY_RV710: 929 sq_conf.num_ps_gprs = 192; 930 sq_conf.num_vs_gprs = 56; 931 sq_conf.num_temp_gprs = 4; 932 sq_conf.num_gs_gprs = 0; 933 sq_conf.num_es_gprs = 0; 934 sq_conf.num_ps_threads = 144; 935 sq_conf.num_vs_threads = 48; 936 sq_conf.num_gs_threads = 0; 937 sq_conf.num_es_threads = 0; 938 sq_conf.num_ps_stack_entries = 128; 939 sq_conf.num_vs_stack_entries = 128; 940 sq_conf.num_gs_stack_entries = 0; 941 sq_conf.num_es_stack_entries = 0; 942 break; 943 } 944 945 r600_sq_setup(pScrn, ib, &sq_conf); 946 947 /* set fake reloc for unused depth */ 948 BEGIN_BATCH(3 + 2); 949 EREG(ib, DB_DEPTH_INFO, 0); 950 RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0); 951 END_BATCH(); 952 953 BEGIN_BATCH(80); 954 if (info->ChipFamily < CHIP_FAMILY_RV770) { 955 EREG(ib, TA_CNTL_AUX, (( 3 << GRADIENT_CREDIT_shift) | 956 (28 << TD_FIFO_CREDIT_shift))); 957 EREG(ib, VC_ENHANCE, 0); 958 EREG(ib, R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0); 959 EREG(ib, DB_DEBUG, 0x82000000); /* ? */ 960 EREG(ib, DB_WATERMARKS, ((4 << DEPTH_FREE_shift) | 961 (16 << DEPTH_FLUSH_shift) | 962 (0 << FORCE_SUMMARIZE_shift) | 963 (4 << DEPTH_PENDING_FREE_shift) | 964 (16 << DEPTH_CACHELINE_FREE_shift) | 965 0)); 966 } else { 967 EREG(ib, TA_CNTL_AUX, (( 2 << GRADIENT_CREDIT_shift) | 968 (28 << TD_FIFO_CREDIT_shift))); 969 EREG(ib, VC_ENHANCE, 0); 970 EREG(ib, R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, VS_PC_LIMIT_ENABLE_bit); 971 EREG(ib, DB_DEBUG, 0); 972 EREG(ib, DB_WATERMARKS, ((4 << DEPTH_FREE_shift) | 973 (16 << DEPTH_FLUSH_shift) | 974 (0 << FORCE_SUMMARIZE_shift) | 975 (4 << DEPTH_PENDING_FREE_shift) | 976 (4 << DEPTH_CACHELINE_FREE_shift) | 977 0)); 978 } 979 980 PACK0(ib, SQ_VTX_BASE_VTX_LOC, 2); 981 E32(ib, 0); 982 E32(ib, 0); 983 984 PACK0(ib, SQ_ESGS_RING_ITEMSIZE, 9); 985 E32(ib, 0); // SQ_ESGS_RING_ITEMSIZE 986 E32(ib, 0); // SQ_GSVS_RING_ITEMSIZE 987 E32(ib, 0); // SQ_ESTMP_RING_ITEMSIZE 988 E32(ib, 0); // SQ_GSTMP_RING_ITEMSIZE 989 E32(ib, 0); // SQ_VSTMP_RING_ITEMSIZE 990 E32(ib, 0); // SQ_PSTMP_RING_ITEMSIZE 991 E32(ib, 0); // SQ_FBUF_RING_ITEMSIZE 992 E32(ib, 0); // SQ_REDUC_RING_ITEMSIZE 993 E32(ib, 0); // SQ_GS_VERT_ITEMSIZE 994 995 // DB 996 EREG(ib, DB_DEPTH_CONTROL, 0); 997 PACK0(ib, DB_RENDER_CONTROL, 2); 998 E32(ib, STENCIL_COMPRESS_DISABLE_bit | DEPTH_COMPRESS_DISABLE_bit); 999 if (info->ChipFamily < CHIP_FAMILY_RV770) 1000 E32(ib, FORCE_SHADER_Z_ORDER_bit); 1001 else 1002 E32(ib, 0); 1003 EREG(ib, DB_ALPHA_TO_MASK, ((2 << ALPHA_TO_MASK_OFFSET0_shift) | 1004 (2 << ALPHA_TO_MASK_OFFSET1_shift) | 1005 (2 << ALPHA_TO_MASK_OFFSET2_shift) | 1006 (2 << ALPHA_TO_MASK_OFFSET3_shift))); 1007 EREG(ib, DB_SHADER_CONTROL, ((1 << Z_ORDER_shift) | /* EARLY_Z_THEN_LATE_Z */ 1008 DUAL_EXPORT_ENABLE_bit)); /* Only useful if no depth export */ 1009 1010 PACK0(ib, DB_STENCIL_CLEAR, 2); 1011 E32(ib, 0); // DB_STENCIL_CLEAR 1012 E32(ib, 0); // DB_DEPTH_CLEAR 1013 1014 PACK0(ib, DB_STENCILREFMASK, 3); 1015 E32(ib, 0); // DB_STENCILREFMASK 1016 E32(ib, 0); // DB_STENCILREFMASK_BF 1017 E32(ib, 0); // SX_ALPHA_REF 1018 1019 PACK0(ib, CB_CLRCMP_CONTROL, 4); 1020 E32(ib, 1 << CLRCMP_FCN_SEL_shift); // CB_CLRCMP_CONTROL: use CLRCMP_FCN_SRC 1021 E32(ib, 0); // CB_CLRCMP_SRC 1022 E32(ib, 0); // CB_CLRCMP_DST 1023 E32(ib, 0); // CB_CLRCMP_MSK 1024 1025 EREG(ib, CB_SHADER_MASK, OUTPUT0_ENABLE_mask); 1026 EREG(ib, R7xx_CB_SHADER_CONTROL, (RT0_ENABLE_bit)); 1027 1028 PACK0(ib, SX_ALPHA_TEST_CONTROL, 5); 1029 E32(ib, 0); // SX_ALPHA_TEST_CONTROL 1030 E32(ib, 0x00000000); // CB_BLEND_RED 1031 E32(ib, 0x00000000); // CB_BLEND_GREEN 1032 E32(ib, 0x00000000); // CB_BLEND_BLUE 1033 E32(ib, 0x00000000); // CB_BLEND_ALPHA 1034 1035 EREG(ib, PA_SC_WINDOW_OFFSET, ((0 << WINDOW_X_OFFSET_shift) | 1036 (0 << WINDOW_Y_OFFSET_shift))); 1037 1038 if (info->ChipFamily < CHIP_FAMILY_RV770) 1039 EREG(ib, R7xx_PA_SC_EDGERULE, 0x00000000); 1040 else 1041 EREG(ib, R7xx_PA_SC_EDGERULE, 0xAAAAAAAA); 1042 1043 EREG(ib, PA_SC_CLIPRECT_RULE, CLIP_RULE_mask); 1044 1045 END_BATCH(); 1046 1047 /* clip boolean is set to always visible -> doesn't matter */ 1048 for (i = 0; i < PA_SC_CLIPRECT_0_TL_num; i++) 1049 r600_set_clip_rect(pScrn, ib, i, 0, 0, 8192, 8192); 1050 1051 for (i = 0; i < PA_SC_VPORT_SCISSOR_0_TL_num; i++) 1052 r600_set_vport_scissor(pScrn, ib, i, 0, 0, 8192, 8192); 1053 1054 BEGIN_BATCH(49); 1055 PACK0(ib, PA_SC_MPASS_PS_CNTL, 2); 1056 E32(ib, 0); 1057 if (info->ChipFamily < CHIP_FAMILY_RV770) 1058 E32(ib, (WALK_ORDER_ENABLE_bit | FORCE_EOV_CNTDWN_ENABLE_bit)); 1059 else 1060 E32(ib, (FORCE_EOV_CNTDWN_ENABLE_bit | FORCE_EOV_REZ_ENABLE_bit | 1061 0x00500000)); /* ? */ 1062 1063 PACK0(ib, PA_SC_LINE_CNTL, 9); 1064 E32(ib, 0); // PA_SC_LINE_CNTL 1065 E32(ib, 0); // PA_SC_AA_CONFIG 1066 E32(ib, ((2 << PA_SU_VTX_CNTL__ROUND_MODE_shift) | PIX_CENTER_bit | // PA_SU_VTX_CNTL 1067 (5 << QUANT_MODE_shift))); /* Round to Even, fixed point 1/256 */ 1068 EFLOAT(ib, 1.0); // PA_CL_GB_VERT_CLIP_ADJ 1069 EFLOAT(ib, 1.0); // PA_CL_GB_VERT_DISC_ADJ 1070 EFLOAT(ib, 1.0); // PA_CL_GB_HORZ_CLIP_ADJ 1071 EFLOAT(ib, 1.0); // PA_CL_GB_HORZ_DISC_ADJ 1072 E32(ib, 0); // PA_SC_AA_SAMPLE_LOCS_MCTX 1073 E32(ib, 0); // PA_SC_AA_SAMPLE_LOCS_8S_WD1_M 1074 1075 EREG(ib, PA_SC_AA_MASK, 0xFFFFFFFF); 1076 1077 PACK0(ib, PA_CL_CLIP_CNTL, 5); 1078 E32(ib, CLIP_DISABLE_bit); // PA_CL_CLIP_CNTL 1079 E32(ib, FACE_bit); // PA_SU_SC_MODE_CNTL 1080 E32(ib, VTX_XY_FMT_bit); // PA_CL_VTE_CNTL 1081 E32(ib, 0); // PA_CL_VS_OUT_CNTL 1082 E32(ib, 0); // PA_CL_NANINF_CNTL 1083 1084 PACK0(ib, PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6); 1085 E32(ib, 0); // PA_SU_POLY_OFFSET_DB_FMT_CNTL 1086 E32(ib, 0); // PA_SU_POLY_OFFSET_CLAMP 1087 E32(ib, 0); // PA_SU_POLY_OFFSET_FRONT_SCALE 1088 E32(ib, 0); // PA_SU_POLY_OFFSET_FRONT_OFFSET 1089 E32(ib, 0); // PA_SU_POLY_OFFSET_BACK_SCALE 1090 E32(ib, 0); // PA_SU_POLY_OFFSET_BACK_OFFSET 1091 1092 // SPI 1093 if (info->ChipFamily < CHIP_FAMILY_RV770) 1094 EREG(ib, R7xx_SPI_THREAD_GROUPING, 0); 1095 else 1096 EREG(ib, R7xx_SPI_THREAD_GROUPING, (1 << PS_GROUPING_shift)); 1097 1098 /* default Interpolator setup */ 1099 EREG(ib, SPI_VS_OUT_ID_0, ((0 << SEMANTIC_0_shift) | 1100 (1 << SEMANTIC_1_shift))); 1101 PACK0(ib, SPI_PS_INPUT_CNTL_0 + (0 << 2), 2); 1102 /* SPI_PS_INPUT_CNTL_0 maps to GPR[0] - load with semantic id 0 */ 1103 E32(ib, ((0 << SEMANTIC_shift) | 1104 (0x01 << DEFAULT_VAL_shift) | 1105 SEL_CENTROID_bit)); 1106 /* SPI_PS_INPUT_CNTL_1 maps to GPR[1] - load with semantic id 1 */ 1107 E32(ib, ((1 << SEMANTIC_shift) | 1108 (0x01 << DEFAULT_VAL_shift) | 1109 SEL_CENTROID_bit)); 1110 1111 PACK0(ib, SPI_INPUT_Z, 4); 1112 E32(ib, 0); // SPI_INPUT_Z 1113 E32(ib, 0); // SPI_FOG_CNTL 1114 E32(ib, 0); // SPI_FOG_FUNC_SCALE 1115 E32(ib, 0); // SPI_FOG_FUNC_BIAS 1116 1117 END_BATCH(); 1118 1119 // clear FS 1120 fs_conf.bo = accel_state->shaders_bo; 1121 r600_fs_setup(pScrn, ib, &fs_conf, RADEON_GEM_DOMAIN_VRAM); 1122 1123 // VGT 1124 BEGIN_BATCH(43); 1125 PACK0(ib, VGT_MAX_VTX_INDX, 4); 1126 E32(ib, 0xffffff); // VGT_MAX_VTX_INDX 1127 E32(ib, 0); // VGT_MIN_VTX_INDX 1128 E32(ib, 0); // VGT_INDX_OFFSET 1129 E32(ib, 0); // VGT_MULTI_PRIM_IB_RESET_INDX 1130 1131 EREG(ib, VGT_PRIMITIVEID_EN, 0); 1132 EREG(ib, VGT_MULTI_PRIM_IB_RESET_EN, 0); 1133 1134 PACK0(ib, VGT_INSTANCE_STEP_RATE_0, 2); 1135 E32(ib, 0); // VGT_INSTANCE_STEP_RATE_0 1136 E32(ib, 0); // VGT_INSTANCE_STEP_RATE_1 1137 1138 PACK0(ib, PA_SU_POINT_SIZE, 17); 1139 E32(ib, 0); // PA_SU_POINT_SIZE 1140 E32(ib, 0); // PA_SU_POINT_MINMAX 1141 E32(ib, (8 << PA_SU_LINE_CNTL__WIDTH_shift)); /* Line width 1 pixel */ // PA_SU_LINE_CNTL 1142 E32(ib, 0); // PA_SC_LINE_STIPPLE 1143 E32(ib, 0); // VGT_OUTPUT_PATH_CNTL 1144 E32(ib, 0); // VGT_HOS_CNTL 1145 E32(ib, 0); // VGT_HOS_MAX_TESS_LEVEL 1146 E32(ib, 0); // VGT_HOS_MIN_TESS_LEVEL 1147 E32(ib, 0); // VGT_HOS_REUSE_DEPTH 1148 E32(ib, 0); // VGT_GROUP_PRIM_TYPE 1149 E32(ib, 0); // VGT_GROUP_FIRST_DECR 1150 E32(ib, 0); // VGT_GROUP_DECR 1151 E32(ib, 0); // VGT_GROUP_VECT_0_CNTL 1152 E32(ib, 0); // VGT_GROUP_VECT_1_CNTL 1153 E32(ib, 0); // VGT_GROUP_VECT_0_FMT_CNTL 1154 E32(ib, 0); // VGT_GROUP_VECT_1_FMT_CNTL 1155 E32(ib, 0); // VGT_GS_MODE 1156 1157 PACK0(ib, VGT_STRMOUT_EN, 3); 1158 E32(ib, 0); // VGT_STRMOUT_EN 1159 E32(ib, 0); // VGT_REUSE_OFF 1160 E32(ib, 0); // VGT_VTX_CNT_EN 1161 1162 EREG(ib, VGT_STRMOUT_BUFFER_EN, 0); 1163 END_BATCH(); 1164} 1165 1166 1167/* 1168 * Commands 1169 */ 1170 1171void 1172r600_draw_immd(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf, uint32_t *indices) 1173{ 1174 RADEONInfoPtr info = RADEONPTR(pScrn); 1175 uint32_t i, count; 1176 1177 // calculate num of packets 1178 count = 2; 1179 if (draw_conf->index_type == DI_INDEX_SIZE_16_BIT) 1180 count += (draw_conf->num_indices + 1) / 2; 1181 else 1182 count += draw_conf->num_indices; 1183 1184 BEGIN_BATCH(8 + count); 1185 EREG(ib, VGT_PRIMITIVE_TYPE, draw_conf->prim_type); 1186 PACK3(ib, IT_INDEX_TYPE, 1); 1187#if X_BYTE_ORDER == X_BIG_ENDIAN 1188 E32(ib, IT_INDEX_TYPE_SWAP_MODE(ENDIAN_8IN32) | draw_conf->index_type); 1189#else 1190 E32(ib, draw_conf->index_type); 1191#endif 1192 PACK3(ib, IT_NUM_INSTANCES, 1); 1193 E32(ib, draw_conf->num_instances); 1194 1195 PACK3(ib, IT_DRAW_INDEX_IMMD, count); 1196 E32(ib, draw_conf->num_indices); 1197 E32(ib, draw_conf->vgt_draw_initiator); 1198 1199 if (draw_conf->index_type == DI_INDEX_SIZE_16_BIT) { 1200 for (i = 0; i < draw_conf->num_indices; i += 2) { 1201 if ((i + 1) == draw_conf->num_indices) 1202 E32(ib, indices[i]); 1203 else 1204 E32(ib, (indices[i] | (indices[i + 1] << 16))); 1205 } 1206 } else { 1207 for (i = 0; i < draw_conf->num_indices; i++) 1208 E32(ib, indices[i]); 1209 } 1210 END_BATCH(); 1211} 1212 1213void 1214r600_draw_auto(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf) 1215{ 1216 RADEONInfoPtr info = RADEONPTR(pScrn); 1217 1218 BEGIN_BATCH(10); 1219 EREG(ib, VGT_PRIMITIVE_TYPE, draw_conf->prim_type); 1220 PACK3(ib, IT_INDEX_TYPE, 1); 1221#if X_BYTE_ORDER == X_BIG_ENDIAN 1222 E32(ib, IT_INDEX_TYPE_SWAP_MODE(ENDIAN_8IN32) | draw_conf->index_type); 1223#else 1224 E32(ib, draw_conf->index_type); 1225#endif 1226 PACK3(ib, IT_NUM_INSTANCES, 1); 1227 E32(ib, draw_conf->num_instances); 1228 PACK3(ib, IT_DRAW_INDEX_AUTO, 2); 1229 E32(ib, draw_conf->num_indices); 1230 E32(ib, draw_conf->vgt_draw_initiator); 1231 END_BATCH(); 1232} 1233 1234void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size) 1235{ 1236 RADEONInfoPtr info = RADEONPTR(pScrn); 1237 struct radeon_accel_state *accel_state = info->accel_state; 1238 draw_config_t draw_conf; 1239 vtx_resource_t vtx_res; 1240 1241 if (accel_state->vbo.vb_start_op == -1) 1242 return; 1243 1244 CLEAR (draw_conf); 1245 CLEAR (vtx_res); 1246 1247 if (accel_state->vbo.vb_offset == accel_state->vbo.vb_start_op) { 1248 R600IBDiscard(pScrn, accel_state->ib); 1249 return; 1250 } 1251 1252 /* Vertex buffer setup */ 1253 accel_state->vbo.vb_size = accel_state->vbo.vb_offset - accel_state->vbo.vb_start_op; 1254 vtx_res.id = SQ_VTX_RESOURCE_vs; 1255 vtx_res.vtx_size_dw = vtx_size / 4; 1256 vtx_res.vtx_num_entries = accel_state->vbo.vb_size / 4; 1257 vtx_res.mem_req_size = 1; 1258 vtx_res.vb_addr = accel_state->vbo.vb_mc_addr + accel_state->vbo.vb_start_op; 1259 vtx_res.bo = accel_state->vbo.vb_bo; 1260#if X_BYTE_ORDER == X_BIG_ENDIAN 1261 vtx_res.endian = SQ_ENDIAN_8IN32; 1262#endif 1263 r600_set_vtx_resource(pScrn, accel_state->ib, &vtx_res, RADEON_GEM_DOMAIN_GTT); 1264 1265 /* Draw */ 1266 draw_conf.prim_type = DI_PT_RECTLIST; 1267 draw_conf.vgt_draw_initiator = DI_SRC_SEL_AUTO_INDEX; 1268 draw_conf.num_instances = 1; 1269 draw_conf.num_indices = vtx_res.vtx_num_entries / vtx_res.vtx_size_dw; 1270 draw_conf.index_type = DI_INDEX_SIZE_16_BIT; 1271 1272 r600_draw_auto(pScrn, accel_state->ib, &draw_conf); 1273 1274 /* XXX drm should handle this in fence submit */ 1275 r600_wait_3d_idle_clean(pScrn, accel_state->ib); 1276 1277 /* sync dst surface */ 1278 r600_cp_set_surface_sync(pScrn, accel_state->ib, (CB_ACTION_ENA_bit | CB0_DEST_BASE_ENA_bit), 1279 accel_state->dst_size, accel_state->dst_obj.offset, 1280 accel_state->dst_obj.bo, 0, accel_state->dst_obj.domain); 1281 1282 accel_state->vbo.vb_start_op = -1; 1283 accel_state->ib_reset_op = 0; 1284 1285#if KMS_MULTI_OP 1286 if (!info->cs) 1287#endif 1288 R600CPFlushIndirect(pScrn, accel_state->ib); 1289} 1290 1291