radeon.h revision 209ff23f 
1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 *                VA Linux Systems Inc., Fremont, California.
4 *
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation on the rights to use, copy, modify, merge,
11 * publish, distribute, sublicense, and/or sell copies of the Software,
12 * and to permit persons to whom the Software is furnished to do so,
13 * subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial
17 * portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
22 * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 */
28
29/*
30 * Authors:
31 *   Kevin E. Martin <martin@xfree86.org>
32 *   Rickard E. Faith <faith@valinux.com>
33 *   Alan Hourihane <alanh@fairlite.demon.co.uk>
34 *
35 */
36
37#ifndef _RADEON_H_
38#define _RADEON_H_
39
40#include <stdlib.h>		/* For abs() */
41#include <unistd.h>		/* For usleep() */
42#include <sys/time.h>		/* For gettimeofday() */
43
44#include "config.h"
45#include "xf86str.h"
46#include "compiler.h"
47#include "xf86fbman.h"
48
49				/* PCI support */
50#include "xf86Pci.h"
51
52#ifdef USE_EXA
53#include "exa.h"
54#endif
55#ifdef USE_XAA
56#include "xaa.h"
57#endif
58
59				/* Exa and Cursor Support */
60#include "vbe.h"
61#include "xf86Cursor.h"
62
63				/* DDC support */
64#include "xf86DDC.h"
65
66				/* Xv support */
67#include "xf86xv.h"
68
69#include "radeon_probe.h"
70#include "radeon_tv.h"
71
72				/* DRI support */
73#ifdef XF86DRI
74#define _XF86DRI_SERVER_
75#include "radeon_dripriv.h"
76#include "dri.h"
77#include "GL/glxint.h"
78#ifdef DAMAGE
79#include "damage.h"
80#include "globals.h"
81#endif
82#endif
83
84#include "xf86Crtc.h"
85#include "X11/Xatom.h"
86
87				/* Render support */
88#ifdef RENDER
89#include "picturestr.h"
90#endif
91
92#include "atipcirename.h"
93
94#ifndef MAX
95#define MAX(a,b) ((a)>(b)?(a):(b))
96#endif
97#ifndef MIN
98#define MIN(a,b) ((a)>(b)?(b):(a))
99#endif
100
101/* Provide substitutes for gcc's __FUNCTION__ on other compilers */
102#if !defined(__GNUC__) && !defined(__FUNCTION__)
103# define __FUNCTION__ __func__		/* C99 */
104#endif
105
106#ifndef HAVE_XF86MODEBANDWIDTH
107extern unsigned int xf86ModeBandwidth(DisplayModePtr mode, int depth);
108#define MODE_BANDWIDTH MODE_BAD
109#endif
110
111typedef enum {
112    OPTION_NOACCEL,
113    OPTION_SW_CURSOR,
114    OPTION_DAC_6BIT,
115    OPTION_DAC_8BIT,
116#ifdef XF86DRI
117    OPTION_BUS_TYPE,
118    OPTION_CP_PIO,
119    OPTION_USEC_TIMEOUT,
120    OPTION_AGP_MODE,
121    OPTION_AGP_FW,
122    OPTION_GART_SIZE,
123    OPTION_GART_SIZE_OLD,
124    OPTION_RING_SIZE,
125    OPTION_BUFFER_SIZE,
126    OPTION_DEPTH_MOVE,
127    OPTION_PAGE_FLIP,
128    OPTION_NO_BACKBUFFER,
129    OPTION_XV_DMA,
130    OPTION_FBTEX_PERCENT,
131    OPTION_DEPTH_BITS,
132    OPTION_PCIAPER_SIZE,
133#ifdef USE_EXA
134    OPTION_ACCEL_DFS,
135#endif
136#endif
137    OPTION_DDC_MODE,
138    OPTION_IGNORE_EDID,
139    OPTION_DISP_PRIORITY,
140    OPTION_PANEL_SIZE,
141    OPTION_MIN_DOTCLOCK,
142    OPTION_COLOR_TILING,
143#ifdef XvExtension
144    OPTION_VIDEO_KEY,
145    OPTION_RAGE_THEATRE_CRYSTAL,
146    OPTION_RAGE_THEATRE_TUNER_PORT,
147    OPTION_RAGE_THEATRE_COMPOSITE_PORT,
148    OPTION_RAGE_THEATRE_SVIDEO_PORT,
149    OPTION_TUNER_TYPE,
150    OPTION_RAGE_THEATRE_MICROC_PATH,
151    OPTION_RAGE_THEATRE_MICROC_TYPE,
152    OPTION_SCALER_WIDTH,
153#endif
154#ifdef RENDER
155    OPTION_RENDER_ACCEL,
156    OPTION_SUBPIXEL_ORDER,
157#endif
158    OPTION_SHOWCACHE,
159    OPTION_DYNAMIC_CLOCKS,
160    OPTION_BIOS_HOTKEYS,
161    OPTION_VGA_ACCESS,
162    OPTION_REVERSE_DDC,
163    OPTION_LVDS_PROBE_PLL,
164    OPTION_ACCELMETHOD,
165    OPTION_CONNECTORTABLE,
166    OPTION_DRI,
167    OPTION_DEFAULT_CONNECTOR_TABLE,
168#if defined(__powerpc__)
169    OPTION_MAC_MODEL,
170#endif
171    OPTION_DEFAULT_TMDS_PLL,
172    OPTION_TVDAC_LOAD_DETECT,
173    OPTION_FORCE_TVOUT,
174    OPTION_TVSTD,
175    OPTION_IGNORE_LID_STATUS,
176    OPTION_DEFAULT_TVDAC_ADJ,
177    OPTION_INT10
178} RADEONOpts;
179
180
181#define RADEON_IDLE_RETRY      16 /* Fall out of idle loops after this count */
182#define RADEON_TIMEOUT    2000000 /* Fall out of wait loops after this count */
183
184#define RADEON_VSYNC_TIMEOUT	20000 /* Maximum wait for VSYNC (in usecs) */
185
186/* Buffer are aligned on 4096 byte boundaries */
187#define RADEON_BUFFER_ALIGN 0x00000fff
188#define RADEON_VBIOS_SIZE 0x00010000
189#define RADEON_USE_RMX 0x80000000 /* mode flag for using RMX
190				   * Need to comfirm this is not used
191				   * for something else.
192				   */
193
194#define xFixedToFloat(f) (((float) (f)) / 65536)
195
196#define RADEON_LOGLEVEL_DEBUG 4
197
198/* for Xv, outputs */
199#define MAKE_ATOM(a) MakeAtom(a, sizeof(a) - 1, TRUE)
200
201/* Other macros */
202#define RADEON_ARRAY_SIZE(x)  (sizeof(x)/sizeof(x[0]))
203#define RADEON_ALIGN(x,bytes) (((x) + ((bytes) - 1)) & ~((bytes) - 1))
204#define RADEONPTR(pScrn)      ((RADEONInfoPtr)(pScrn)->driverPrivate)
205
206typedef struct {
207    int    revision;
208    uint16_t rr1_offset;
209    uint16_t rr2_offset;
210    uint16_t dyn_clk_offset;
211    uint16_t pll_offset;
212    uint16_t mem_config_offset;
213    uint16_t mem_reset_offset;
214    uint16_t short_mem_offset;
215    uint16_t rr3_offset;
216    uint16_t rr4_offset;
217} RADEONBIOSInitTable;
218
219#define RADEON_PLL_USE_BIOS_DIVS   (1 << 0)
220#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
221#define RADEON_PLL_USE_REF_DIV     (1 << 2)
222#define RADEON_PLL_LEGACY          (1 << 3)
223#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
224
225typedef struct {
226    uint16_t          reference_freq;
227    uint16_t          reference_div;
228    uint32_t          pll_in_min;
229    uint32_t          pll_in_max;
230    uint32_t          pll_out_min;
231    uint32_t          pll_out_max;
232    uint16_t          xclk;
233
234    uint32_t          min_ref_div;
235    uint32_t          max_ref_div;
236    uint32_t          min_post_div;
237    uint32_t          max_post_div;
238    uint32_t          min_feedback_div;
239    uint32_t          max_feedback_div;
240    uint32_t          best_vco;
241} RADEONPLLRec, *RADEONPLLPtr;
242
243typedef struct {
244    int               bitsPerPixel;
245    int               depth;
246    int               displayWidth;
247    int               displayHeight;
248    int               pixel_code;
249    int               pixel_bytes;
250    DisplayModePtr    mode;
251} RADEONFBLayout;
252
253typedef enum {
254    CHIP_FAMILY_UNKNOW,
255    CHIP_FAMILY_LEGACY,
256    CHIP_FAMILY_RADEON,
257    CHIP_FAMILY_RV100,
258    CHIP_FAMILY_RS100,    /* U1 (IGP320M) or A3 (IGP320)*/
259    CHIP_FAMILY_RV200,
260    CHIP_FAMILY_RS200,    /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */
261    CHIP_FAMILY_R200,
262    CHIP_FAMILY_RV250,
263    CHIP_FAMILY_RS300,    /* RS300/RS350 */
264    CHIP_FAMILY_RV280,
265    CHIP_FAMILY_R300,
266    CHIP_FAMILY_R350,
267    CHIP_FAMILY_RV350,
268    CHIP_FAMILY_RV380,    /* RV370/RV380/M22/M24 */
269    CHIP_FAMILY_R420,     /* R420/R423/M18 */
270    CHIP_FAMILY_RV410,    /* RV410, M26 */
271    CHIP_FAMILY_RS400,    /* xpress 200, 200m (RS400) Intel */
272    CHIP_FAMILY_RS480,    /* xpress 200, 200m (RS410/480/482/485) AMD */
273    CHIP_FAMILY_RV515,    /* rv515 */
274    CHIP_FAMILY_R520,    /* r520 */
275    CHIP_FAMILY_RV530,    /* rv530 */
276    CHIP_FAMILY_R580,    /* r580 */
277    CHIP_FAMILY_RV560,   /* rv560 */
278    CHIP_FAMILY_RV570,   /* rv570 */
279    CHIP_FAMILY_RS600,
280    CHIP_FAMILY_RS690,
281    CHIP_FAMILY_RS740,
282    CHIP_FAMILY_R600,    /* r600 */
283    CHIP_FAMILY_R630,
284    CHIP_FAMILY_RV610,
285    CHIP_FAMILY_RV630,
286    CHIP_FAMILY_RV670,
287    CHIP_FAMILY_RV620,
288    CHIP_FAMILY_RV635,
289    CHIP_FAMILY_RS780,
290    CHIP_FAMILY_LAST
291} RADEONChipFamily;
292
293#define IS_RV100_VARIANT ((info->ChipFamily == CHIP_FAMILY_RV100)  ||  \
294        (info->ChipFamily == CHIP_FAMILY_RV200)  ||  \
295        (info->ChipFamily == CHIP_FAMILY_RS100)  ||  \
296        (info->ChipFamily == CHIP_FAMILY_RS200)  ||  \
297        (info->ChipFamily == CHIP_FAMILY_RV250)  ||  \
298        (info->ChipFamily == CHIP_FAMILY_RV280)  ||  \
299        (info->ChipFamily == CHIP_FAMILY_RS300))
300
301
302#define IS_R300_VARIANT ((info->ChipFamily == CHIP_FAMILY_R300)  ||  \
303        (info->ChipFamily == CHIP_FAMILY_RV350) ||  \
304        (info->ChipFamily == CHIP_FAMILY_R350)  ||  \
305        (info->ChipFamily == CHIP_FAMILY_RV380) ||  \
306        (info->ChipFamily == CHIP_FAMILY_R420)  ||  \
307        (info->ChipFamily == CHIP_FAMILY_RV410) ||  \
308        (info->ChipFamily == CHIP_FAMILY_RS400) ||  \
309        (info->ChipFamily == CHIP_FAMILY_RS480))
310
311#define IS_AVIVO_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV515))
312
313#define IS_DCE3_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV620))
314
315#define IS_R500_3D ((info->ChipFamily == CHIP_FAMILY_RV515)  ||  \
316	(info->ChipFamily == CHIP_FAMILY_R520)   ||  \
317	(info->ChipFamily == CHIP_FAMILY_RV530)  ||  \
318	(info->ChipFamily == CHIP_FAMILY_R580)   ||  \
319	(info->ChipFamily == CHIP_FAMILY_RV560)  ||  \
320	(info->ChipFamily == CHIP_FAMILY_RV570))
321
322#define IS_R300_3D ((info->ChipFamily == CHIP_FAMILY_R300)  ||  \
323	(info->ChipFamily == CHIP_FAMILY_RV350) ||  \
324	(info->ChipFamily == CHIP_FAMILY_R350)  ||  \
325	(info->ChipFamily == CHIP_FAMILY_RV380) ||  \
326	(info->ChipFamily == CHIP_FAMILY_R420)  ||  \
327	(info->ChipFamily == CHIP_FAMILY_RV410) ||  \
328	(info->ChipFamily == CHIP_FAMILY_RS690) ||  \
329	(info->ChipFamily == CHIP_FAMILY_RS600) ||  \
330	(info->ChipFamily == CHIP_FAMILY_RS740) ||  \
331	(info->ChipFamily == CHIP_FAMILY_RS400) ||  \
332	(info->ChipFamily == CHIP_FAMILY_RS480))
333
334/*
335 * Errata workarounds
336 */
337typedef enum {
338       CHIP_ERRATA_R300_CG             = 0x00000001,
339       CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
340       CHIP_ERRATA_PLL_DELAY           = 0x00000004
341} RADEONErrata;
342
343typedef enum {
344    RADEON_DVOCHIP_NONE,
345    RADEON_SIL_164,
346    RADEON_SIL_1178
347} RADEONExtTMDSChip;
348
349#if defined(__powerpc__)
350typedef enum {
351    RADEON_MAC_NONE,
352    RADEON_MAC_IBOOK,
353    RADEON_MAC_POWERBOOK_EXTERNAL,
354    RADEON_MAC_POWERBOOK_INTERNAL,
355    RADEON_MAC_POWERBOOK_VGA,
356    RADEON_MAC_MINI_EXTERNAL,
357    RADEON_MAC_MINI_INTERNAL,
358    RADEON_MAC_IMAC_G5_ISIGHT
359} RADEONMacModel;
360#endif
361
362typedef enum {
363	CARD_PCI,
364	CARD_AGP,
365	CARD_PCIE
366} RADEONCardType;
367
368typedef struct _atomBiosHandle *atomBiosHandlePtr;
369
370typedef struct {
371    uint32_t pci_device_id;
372    RADEONChipFamily chip_family;
373    int mobility;
374    int igp;
375    int nocrtc2;
376    int nointtvout;
377    int singledac;
378} RADEONCardInfo;
379
380typedef struct {
381    EntityInfoPtr     pEnt;
382    pciVideoPtr       PciInfo;
383    PCITAG            PciTag;
384    int               Chipset;
385    RADEONChipFamily  ChipFamily;
386    RADEONErrata      ChipErrata;
387
388    unsigned long     LinearAddr;       /* Frame buffer physical address     */
389    unsigned long     MMIOAddr;         /* MMIO region physical address      */
390    unsigned long     BIOSAddr;         /* BIOS physical address             */
391    uint32_t          fbLocation;
392    uint32_t          gartLocation;
393    uint32_t          mc_fb_location;
394    uint32_t          mc_agp_location;
395    uint32_t          mc_agp_location_hi;
396
397    void              *MMIO;            /* Map of MMIO region                */
398    void              *FB;              /* Map of frame buffer               */
399    uint8_t           *VBIOS;           /* Video BIOS pointer                */
400
401    Bool              IsAtomBios;       /* New BIOS used in R420 etc.        */
402    int               ROMHeaderStart;   /* Start of the ROM Info Table       */
403    int               MasterDataStart;  /* Offset for Master Data Table for ATOM BIOS */
404
405    uint32_t          MemCntl;
406    uint32_t          BusCntl;
407    unsigned long     MMIOSize;         /* MMIO region physical address      */
408    unsigned long     FbMapSize;        /* Size of frame buffer, in bytes    */
409    unsigned long     FbSecureSize;     /* Size of secured fb area at end of
410                                           framebuffer */
411
412    Bool              IsMobility;       /* Mobile chips for laptops */
413    Bool              IsIGP;            /* IGP chips */
414    Bool              HasSingleDAC;     /* only TVDAC on chip */
415    Bool              ddc_mode;         /* Validate mode by matching exactly
416					 * the modes supported in DDC data
417					 */
418    Bool              R300CGWorkaround;
419
420				/* EDID or BIOS values for FPs */
421    int               RefDivider;
422    int               FeedbackDivider;
423    int               PostDivider;
424    Bool              UseBiosDividers;
425				/* EDID data using DDC interface */
426    Bool              ddc_bios;
427    Bool              ddc1;
428    Bool              ddc2;
429
430    RADEONPLLRec      pll;
431
432    int               RamWidth;
433    float	      sclk;		/* in MHz */
434    float	      mclk;		/* in MHz */
435    Bool	      IsDDR;
436    int               DispPriority;
437
438    RADEONSavePtr     SavedReg;         /* Original (text) mode              */
439    RADEONSavePtr     ModeReg;          /* Current mode                      */
440    Bool              (*CloseScreen)(int, ScreenPtr);
441
442    void              (*BlockHandler)(int, pointer, pointer, pointer);
443
444    Bool              PaletteSavedOnVT; /* Palette saved on last VT switch   */
445
446#ifdef USE_EXA
447    ExaDriverPtr      exa;
448    int               exaSyncMarker;
449    int               exaMarkerSynced;
450    int               engineMode;
451#define EXA_ENGINEMODE_UNKNOWN 0
452#define EXA_ENGINEMODE_2D      1
453#define EXA_ENGINEMODE_3D      2
454#ifdef XF86DRI
455    Bool              accelDFS;
456#endif
457#endif
458#ifdef USE_XAA
459    XAAInfoRecPtr     accel;
460#endif
461    Bool              accelOn;
462    xf86CursorInfoPtr cursor;
463    Bool              allowColorTiling;
464    Bool              tilingEnabled; /* mirror of sarea->tiling_enabled */
465#ifdef ARGB_CURSOR
466    Bool	      cursor_argb;
467#endif
468    int               cursor_fg;
469    int               cursor_bg;
470
471#ifdef USE_XAA
472    /*
473     * XAAForceTransBlit is used to change the behavior of the XAA
474     * SetupForScreenToScreenCopy function, to make it DGA-friendly.
475     */
476    Bool              XAAForceTransBlit;
477#endif
478
479    int               fifo_slots;       /* Free slots in the FIFO (64 max)   */
480    int               pix24bpp;         /* Depth of pixmap for 24bpp fb      */
481    Bool              dac6bits;         /* Use 6 bit DAC?                    */
482
483				/* Computed values for Radeon */
484    int               pitch;
485    int               datatype;
486    uint32_t          dp_gui_master_cntl;
487    uint32_t          dp_gui_master_cntl_clip;
488    uint32_t          trans_color;
489
490				/* Saved values for ScreenToScreenCopy */
491    int               xdir;
492    int               ydir;
493
494#ifdef USE_XAA
495				/* ScanlineScreenToScreenColorExpand support */
496    unsigned char     *scratch_buffer[1];
497    unsigned char     *scratch_save;
498    int               scanline_x;
499    int               scanline_y;
500    int               scanline_w;
501    int               scanline_h;
502    int               scanline_h_w;
503    int               scanline_words;
504    int               scanline_direct;
505    int               scanline_bpp;     /* Only used for ImageWrite */
506    int               scanline_fg;
507    int               scanline_bg;
508    int               scanline_hpass;
509    int               scanline_x1clip;
510    int               scanline_x2clip;
511#endif
512				/* Saved values for DashedTwoPointLine */
513    int               dashLen;
514    uint32_t          dashPattern;
515    int               dash_fg;
516    int               dash_bg;
517
518    DGAModePtr        DGAModes;
519    int               numDGAModes;
520    Bool              DGAactive;
521    int               DGAViewportStatus;
522    DGAFunctionRec    DGAFuncs;
523
524    RADEONFBLayout    CurrentLayout;
525    uint32_t          dst_pitch_offset;
526#ifdef XF86DRI
527    Bool              noBackBuffer;
528    Bool              directRenderingEnabled;
529    Bool              directRenderingInited;
530    Bool              newMemoryMap;
531    drmVersionPtr     pLibDRMVersion;
532    drmVersionPtr     pKernelDRMVersion;
533    DRIInfoPtr        pDRIInfo;
534    int               drmFD;
535    int               numVisualConfigs;
536    __GLXvisualConfig *pVisualConfigs;
537    RADEONConfigPrivPtr pVisualConfigsPriv;
538    Bool             (*DRICloseScreen)(int, ScreenPtr);
539
540    drm_handle_t      fbHandle;
541
542    drmSize           registerSize;
543    drm_handle_t      registerHandle;
544
545    RADEONCardType    cardType;            /* Current card is a PCI card */
546    drmSize           pciSize;
547    drm_handle_t      pciMemHandle;
548    unsigned char     *PCI;             /* Map */
549
550    Bool              depthMoves;       /* Enable depth moves -- slow! */
551    Bool              allowPageFlip;    /* Enable 3d page flipping */
552#ifdef DAMAGE
553    DamagePtr         pDamage;
554    RegionRec         driRegion;
555#endif
556    Bool              have3DWindows;    /* Are there any 3d clients? */
557
558    int               pciAperSize;
559    drmSize           gartSize;
560    drm_handle_t      agpMemHandle;     /* Handle from drmAgpAlloc */
561    unsigned long     gartOffset;
562    unsigned char     *AGP;             /* Map */
563    int               agpMode;
564
565    uint32_t          pciCommand;
566
567    Bool              CPRuns;           /* CP is running */
568    Bool              CPInUse;          /* CP has been used by X server */
569    Bool              CPStarted;        /* CP has started */
570    int               CPMode;           /* CP mode that server/clients use */
571    int               CPFifoSize;       /* Size of the CP command FIFO */
572    int               CPusecTimeout;    /* CP timeout in usecs */
573    Bool              needCacheFlush;
574
575				/* CP ring buffer data */
576    unsigned long     ringStart;        /* Offset into GART space */
577    drm_handle_t      ringHandle;       /* Handle from drmAddMap */
578    drmSize           ringMapSize;      /* Size of map */
579    int               ringSize;         /* Size of ring (in MB) */
580    drmAddress        ring;             /* Map */
581    int               ringSizeLog2QW;
582
583    unsigned long     ringReadOffset;   /* Offset into GART space */
584    drm_handle_t      ringReadPtrHandle; /* Handle from drmAddMap */
585    drmSize           ringReadMapSize;  /* Size of map */
586    drmAddress        ringReadPtr;      /* Map */
587
588				/* CP vertex/indirect buffer data */
589    unsigned long     bufStart;         /* Offset into GART space */
590    drm_handle_t      bufHandle;        /* Handle from drmAddMap */
591    drmSize           bufMapSize;       /* Size of map */
592    int               bufSize;          /* Size of buffers (in MB) */
593    drmAddress        buf;              /* Map */
594    int               bufNumBufs;       /* Number of buffers */
595    drmBufMapPtr      buffers;          /* Buffer map */
596
597				/* CP GART Texture data */
598    unsigned long     gartTexStart;      /* Offset into GART space */
599    drm_handle_t      gartTexHandle;     /* Handle from drmAddMap */
600    drmSize           gartTexMapSize;    /* Size of map */
601    int               gartTexSize;       /* Size of GART tex space (in MB) */
602    drmAddress        gartTex;           /* Map */
603    int               log2GARTTexGran;
604
605				/* CP accleration */
606    drmBufPtr         indirectBuffer;
607    int               indirectStart;
608
609				/* DRI screen private data */
610    int               fbX;
611    int               fbY;
612    int               backX;
613    int               backY;
614    int               depthX;
615    int               depthY;
616
617    int               frontOffset;
618    int               frontPitch;
619    int               backOffset;
620    int               backPitch;
621    int               depthOffset;
622    int               depthPitch;
623    int               depthBits;
624    int               textureOffset;
625    int               textureSize;
626    int               log2TexGran;
627
628    int               pciGartSize;
629    uint32_t          pciGartOffset;
630    void              *pciGartBackup;
631#ifdef USE_XAA
632    uint32_t          frontPitchOffset;
633    uint32_t          backPitchOffset;
634    uint32_t          depthPitchOffset;
635
636				/* offscreen memory management */
637    int               backLines;
638    FBAreaPtr         backArea;
639    int               depthTexLines;
640    FBAreaPtr         depthTexArea;
641#endif
642
643				/* Saved scissor values */
644    uint32_t          sc_left;
645    uint32_t          sc_right;
646    uint32_t          sc_top;
647    uint32_t          sc_bottom;
648
649    uint32_t          re_top_left;
650    uint32_t          re_width_height;
651
652    uint32_t          aux_sc_cntl;
653
654    int               irq;
655
656    Bool              DMAForXv;
657
658#ifdef PER_CONTEXT_SAREA
659    int               perctx_sarea_size;
660#endif
661
662    /* Debugging info for BEGIN_RING/ADVANCE_RING pairs. */
663    int               dma_begin_count;
664    char              *dma_debug_func;
665    int               dma_debug_lineno;
666#endif /* XF86DRI */
667
668				/* XVideo */
669    XF86VideoAdaptorPtr adaptor;
670    void              (*VideoTimerCallback)(ScrnInfoPtr, Time);
671    int               videoKey;
672    int		      RageTheatreCrystal;
673    int               RageTheatreTunerPort;
674    int               RageTheatreCompositePort;
675    int               RageTheatreSVideoPort;
676    int               tunerType;
677    char*             RageTheatreMicrocPath;
678    char*             RageTheatreMicrocType;
679    Bool              MM_TABLE_valid;
680    struct {
681    	uint8_t table_revision;
682	uint8_t table_size;
683        uint8_t tuner_type;
684        uint8_t audio_chip;
685        uint8_t product_id;
686        uint8_t tuner_voltage_teletext_fm;
687        uint8_t i2s_config; /* configuration of the sound chip */
688        uint8_t video_decoder_type;
689        uint8_t video_decoder_host_config;
690        uint8_t input[5];
691    } MM_TABLE;
692    uint16_t video_decoder_type;
693    int overlay_scaler_buffer_width;
694    int ecp_div;
695
696    /* Render */
697    Bool              RenderAccel;
698    unsigned short    texW[2];
699    unsigned short    texH[2];
700#ifdef USE_XAA
701    FBLinearPtr       RenderTex;
702    void              (*RenderCallback)(ScrnInfoPtr);
703    Time              RenderTimeout;
704#endif
705
706    /* general */
707    Bool              showCache;
708    OptionInfoPtr     Options;
709
710    Bool              useEXA;
711#ifdef USE_EXA
712    XF86ModReqInfo    exaReq;
713#endif
714#ifdef USE_XAA
715    XF86ModReqInfo    xaaReq;
716#endif
717
718    /* X itself has the 3D context */
719    Bool              XInited3D;
720
721    DisplayModePtr currentMode, savedCurrentMode;
722
723    /* special handlings for DELL triple-head server */
724    Bool              IsDellServer;
725
726    Bool              VGAAccess;
727
728    int               MaxSurfaceWidth;
729    int               MaxLines;
730
731    uint32_t          tv_dac_adj;
732    uint32_t          tv_dac_enable_mask;
733
734    Bool want_vblank_interrupts;
735    RADEONBIOSConnector BiosConnector[RADEON_MAX_BIOS_CONNECTOR];
736    RADEONBIOSInitTable BiosTable;
737
738    /* save crtc state for console restore */
739    Bool              crtc_on;
740    Bool              crtc2_on;
741
742    Bool              InternalTVOut;
743    int               tvdac_use_count;
744
745#if defined(__powerpc__)
746    RADEONMacModel    MacModel;
747#endif
748    RADEONExtTMDSChip ext_tmds_chip;
749
750    atomBiosHandlePtr atomBIOS;
751    unsigned long FbFreeStart, FbFreeSize;
752    unsigned char*      BIOSCopy;
753
754    /* output enable masks for outputs shared across connectors */
755    int output_crt1;
756    int output_crt2;
757    int output_dfp1;
758    int output_dfp2;
759    int output_lcd1;
760    int output_tv1;
761
762    Rotation rotation;
763    void (*PointerMoved)(int, int, int);
764    CreateScreenResourcesProcPtr CreateScreenResources;
765
766    /* if no devices are connected at server startup */
767    Bool              first_load_no_devices;
768
769    Bool              IsSecondary;
770    Bool              IsPrimary;
771
772    Bool              r600_shadow_fb;
773    void *fb_shadow;
774
775    int num_gb_pipes;
776    Bool has_tcl;
777} RADEONInfoRec, *RADEONInfoPtr;
778
779#define RADEONWaitForFifo(pScrn, entries)				\
780do {									\
781    if (info->fifo_slots < entries)					\
782	RADEONWaitForFifoFunction(pScrn, entries);			\
783    info->fifo_slots -= entries;					\
784} while (0)
785
786/* legacy_crtc.c */
787extern void legacy_crtc_dpms(xf86CrtcPtr crtc, int mode);
788extern void legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
789				 DisplayModePtr adjusted_mode, int x, int y);
790extern void RADEONInitDispBandwidth(ScrnInfoPtr pScrn);
791extern void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn,
792					 RADEONSavePtr restore);
793extern void RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn,
794				       RADEONSavePtr restore);
795extern void RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn,
796					RADEONSavePtr restore);
797extern void RADEONRestorePLLRegisters(ScrnInfoPtr pScrn,
798				      RADEONSavePtr restore);
799extern void RADEONRestorePLL2Registers(ScrnInfoPtr pScrn,
800				       RADEONSavePtr restore);
801extern void RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
802extern void RADEONSaveCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
803extern void RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save);
804extern void RADEONSavePLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
805extern void RADEONSavePLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save);
806
807/* legacy_output.c */
808extern RADEONMonitorType legacy_dac_detect(ScrnInfoPtr pScrn,
809					   xf86OutputPtr output);
810extern void legacy_output_dpms(xf86OutputPtr output, int mode);
811extern void legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode,
812				   DisplayModePtr adjusted_mode);
813extern I2CDevPtr RADEONDVODeviceInit(I2CBusPtr b, I2CSlaveAddr addr);
814extern Bool RADEONDVOReadByte(I2CDevPtr dvo, int addr, uint8_t *ch);
815extern Bool RADEONDVOWriteByte(I2CDevPtr dvo, int addr, uint8_t ch);
816extern void RADEONRestoreDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
817extern void RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
818extern void RADEONRestoreFP2Registers(ScrnInfoPtr pScrn, RADEONSavePtr restore);
819extern void RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
820extern void RADEONRestoreRMXRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
821extern void RADEONSaveDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
822extern void RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
823
824/* radeon_accel.c */
825extern Bool RADEONAccelInit(ScreenPtr pScreen);
826extern void RADEONEngineFlush(ScrnInfoPtr pScrn);
827extern void RADEONEngineInit(ScrnInfoPtr pScrn);
828extern void RADEONEngineReset(ScrnInfoPtr pScrn);
829extern void RADEONEngineRestore(ScrnInfoPtr pScrn);
830extern uint8_t *RADEONHostDataBlit(ScrnInfoPtr pScrn, unsigned int cpp,
831				 unsigned int w, uint32_t dstPitchOff,
832				 uint32_t *bufPitch, int x, int *y,
833				 unsigned int *h, unsigned int *hpass);
834extern void RADEONHostDataBlitCopyPass(ScrnInfoPtr pScrn,
835				       unsigned int bpp,
836				       uint8_t *dst, uint8_t *src,
837				       unsigned int hpass,
838				       unsigned int dstPitch,
839				       unsigned int srcPitch);
840extern void  RADEONCopySwap(uint8_t *dst, uint8_t *src, unsigned int size, int swap);
841extern void RADEONHostDataParams(ScrnInfoPtr pScrn, uint8_t *dst,
842				 uint32_t pitch, int cpp,
843				 uint32_t *dstPitchOffset, int *x, int *y);
844extern void RADEONInit3DEngine(ScrnInfoPtr pScrn);
845extern void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries);
846#ifdef XF86DRI
847extern drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn);
848extern void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard);
849extern void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn);
850extern int RADEONCPStop(ScrnInfoPtr pScrn,  RADEONInfoPtr info);
851#  ifdef USE_XAA
852extern Bool RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen);
853#  endif
854#endif
855
856#ifdef USE_XAA
857/* radeon_accelfuncs.c */
858extern void RADEONAccelInitMMIO(ScreenPtr pScreen, XAAInfoRecPtr a);
859extern Bool RADEONSetupMemXAA(int scrnIndex, ScreenPtr pScreen);
860#endif
861
862/* radeon_bios.c */
863extern Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10);
864extern Bool RADEONGetClockInfoFromBIOS(ScrnInfoPtr pScrn);
865extern Bool RADEONGetConnectorInfoFromBIOS(ScrnInfoPtr pScrn);
866extern Bool RADEONGetDAC2InfoFromBIOS(xf86OutputPtr output);
867extern Bool RADEONGetExtTMDSInfoFromBIOS(xf86OutputPtr output);
868extern Bool RADEONGetHardCodedEDIDFromBIOS(xf86OutputPtr output);
869extern Bool RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn);
870extern Bool RADEONGetLVDSInfoFromBIOS(xf86OutputPtr output);
871extern Bool RADEONGetTMDSInfoFromBIOS(xf86OutputPtr output);
872extern Bool RADEONGetTVInfoFromBIOS(xf86OutputPtr output);
873extern Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output);
874extern Bool RADEONPostCardFromBIOSTables(ScrnInfoPtr pScrn);
875
876/* radeon_commonfuncs.c */
877#ifdef XF86DRI
878extern void RADEONWaitForIdleCP(ScrnInfoPtr pScrn);
879#endif
880extern void RADEONWaitForIdleMMIO(ScrnInfoPtr pScrn);
881
882/* radeon_crtc.c */
883extern void radeon_crtc_dpms(xf86CrtcPtr crtc, int mode);
884extern void radeon_crtc_load_lut(xf86CrtcPtr crtc);
885extern void radeon_crtc_modeset_ioctl(xf86CrtcPtr crtc, Bool post);
886extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask);
887extern void RADEONBlank(ScrnInfoPtr pScrn);
888extern void RADEONComputePLL(RADEONPLLPtr pll, unsigned long freq,
889			     uint32_t *chosen_dot_clock_freq,
890			     uint32_t *chosen_feedback_div,
891			     uint32_t *chosen_reference_div,
892			     uint32_t *chosen_post_div, int flags);
893extern DisplayModePtr RADEONCrtcFindClosestMode(xf86CrtcPtr crtc,
894						DisplayModePtr pMode);
895extern void RADEONUnblank(ScrnInfoPtr pScrn);
896extern Bool RADEONSetTiling(ScrnInfoPtr pScrn);
897
898/* radeon_cursor.c */
899extern Bool RADEONCursorInit(ScreenPtr pScreen);
900extern void radeon_crtc_hide_cursor(xf86CrtcPtr crtc);
901extern void radeon_crtc_load_cursor_argb(xf86CrtcPtr crtc, CARD32 *image);
902extern void radeon_crtc_set_cursor_colors(xf86CrtcPtr crtc, int bg, int fg);
903extern void radeon_crtc_set_cursor_position(xf86CrtcPtr crtc, int x, int y);
904extern void radeon_crtc_show_cursor(xf86CrtcPtr crtc);
905
906/* radeon_dga.c */
907extern Bool RADEONDGAInit(ScreenPtr pScreen);
908
909#ifdef XF86DRI
910/* radeon_dri.c */
911extern void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen);
912extern void RADEONDRICloseScreen(ScreenPtr pScreen);
913extern Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen);
914extern int RADEONDRIGetPciAperTableSize(ScrnInfoPtr pScrn);
915extern Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn);
916extern void RADEONDRIResume(ScreenPtr pScreen);
917extern Bool RADEONDRIScreenInit(ScreenPtr pScreen);
918extern int RADEONDRISetParam(ScrnInfoPtr pScrn,
919			     unsigned int param, int64_t value);
920extern Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on);
921extern void RADEONDRIStop(ScreenPtr pScreen);
922#endif
923
924/* radeon_driver.c */
925extern void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool clone);
926extern void RADEONChangeSurfaces(ScrnInfoPtr pScrn);
927extern RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn);
928extern int RADEONMinBits(int val);
929extern unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr);
930extern unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr);
931extern void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, uint32_t data);
932extern void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, uint32_t data);
933extern void RADEONPllErrataAfterData(RADEONInfoPtr info);
934extern void RADEONPllErrataAfterIndex(RADEONInfoPtr info);
935extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn);
936extern void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn);
937extern void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
938				      RADEONInfoPtr info);
939extern void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
940					 RADEONSavePtr restore);
941
942#ifdef USE_EXA
943/* radeon_exa.c */
944extern Bool RADEONSetupMemEXA(ScreenPtr pScreen);
945
946/* radeon_exa_funcs.c */
947extern void RADEONCopyCP(PixmapPtr pDst, int srcX, int srcY, int dstX,
948			 int dstY, int w, int h);
949extern void RADEONCopyMMIO(PixmapPtr pDst, int srcX, int srcY, int dstX,
950			   int dstY, int w, int h);
951extern Bool RADEONDrawInitCP(ScreenPtr pScreen);
952extern Bool RADEONDrawInitMMIO(ScreenPtr pScreen);
953extern void RADEONDoPrepareCopyCP(ScrnInfoPtr pScrn,
954				  uint32_t src_pitch_offset,
955				  uint32_t dst_pitch_offset,
956				  uint32_t datatype, int rop,
957				  Pixel planemask);
958extern void RADEONDoPrepareCopyMMIO(ScrnInfoPtr pScrn,
959				    uint32_t src_pitch_offset,
960				    uint32_t dst_pitch_offset,
961				    uint32_t datatype, int rop,
962				    Pixel planemask);
963#endif
964
965#if defined(XF86DRI) && defined(USE_EXA)
966/* radeon_exa.c */
967extern Bool RADEONGetDatatypeBpp(int bpp, uint32_t *type);
968extern Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix,
969				       uint32_t *pitch_offset);
970extern unsigned long long RADEONTexOffsetStart(PixmapPtr pPix);
971#endif
972
973/* radeon_modes.c */
974extern void RADEONSetPitch(ScrnInfoPtr pScrn);
975extern DisplayModePtr RADEONProbeOutputModes(xf86OutputPtr output);
976
977/* radeon_output.c */
978extern RADEONI2CBusRec atom_setup_i2c_bus(int ddc_line);
979extern RADEONI2CBusRec legacy_setup_i2c_bus(int ddc_line);
980extern void RADEONGetPanelInfo(ScrnInfoPtr pScrn);
981extern void RADEONInitConnector(xf86OutputPtr output);
982extern void RADEONPrintPortMap(ScrnInfoPtr pScrn);
983extern void RADEONSetOutputType(ScrnInfoPtr pScrn,
984				RADEONOutputPrivatePtr radeon_output);
985extern Bool RADEONSetupConnectors(ScrnInfoPtr pScrn);
986
987/* radeon_tv.c */
988extern void RADEONSaveTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
989extern void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
990					   DisplayModePtr mode, xf86OutputPtr output);
991extern void RADEONAdjustPLLRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
992					  DisplayModePtr mode, xf86OutputPtr output);
993extern void RADEONAdjustCrtc2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
994					   DisplayModePtr mode, xf86OutputPtr output);
995extern void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
996					  DisplayModePtr mode, xf86OutputPtr output);
997extern void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
998                                  DisplayModePtr mode, BOOL IsPrimary);
999extern void RADEONRestoreTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
1000extern void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode);
1001
1002/* radeon_video.c */
1003extern void RADEONInitVideo(ScreenPtr pScreen);
1004extern void RADEONResetVideo(ScrnInfoPtr pScrn);
1005
1006#ifdef XF86DRI
1007#  ifdef USE_XAA
1008/* radeon_accelfuncs.c */
1009extern void RADEONAccelInitCP(ScreenPtr pScreen, XAAInfoRecPtr a);
1010#  endif
1011
1012#define RADEONCP_START(pScrn, info)					\
1013do {									\
1014    int _ret = drmCommandNone(info->drmFD, DRM_RADEON_CP_START);	\
1015    if (_ret) {								\
1016	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,				\
1017		   "%s: CP start %d\n", __FUNCTION__, _ret);		\
1018    }									\
1019    info->CPStarted = TRUE;                                             \
1020} while (0)
1021
1022#define RADEONCP_RELEASE(pScrn, info)					\
1023do {									\
1024    if (info->CPInUse) {						\
1025	RADEON_PURGE_CACHE();						\
1026	RADEON_WAIT_UNTIL_IDLE();					\
1027	RADEONCPReleaseIndirect(pScrn);					\
1028	info->CPInUse = FALSE;						\
1029    }									\
1030} while (0)
1031
1032#define RADEONCP_STOP(pScrn, info)					\
1033do {									\
1034    int _ret;								\
1035     if (info->CPStarted) {						\
1036        _ret = RADEONCPStop(pScrn, info);				\
1037        if (_ret) {							\
1038	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR,			\
1039		   "%s: CP stop %d\n", __FUNCTION__, _ret);		\
1040        }								\
1041        info->CPStarted = FALSE;                                        \
1042   }									\
1043    RADEONEngineRestore(pScrn);						\
1044    info->CPRuns = FALSE;						\
1045} while (0)
1046
1047#define RADEONCP_RESET(pScrn, info)					\
1048do {									\
1049    if (RADEONCP_USE_RING_BUFFER(info->CPMode)) {			\
1050	int _ret = drmCommandNone(info->drmFD, DRM_RADEON_CP_RESET);	\
1051	if (_ret) {							\
1052	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR,			\
1053		       "%s: CP reset %d\n", __FUNCTION__, _ret);	\
1054	}								\
1055    }									\
1056} while (0)
1057
1058#define RADEONCP_REFRESH(pScrn, info)					\
1059do {									\
1060    if (!info->CPInUse) {						\
1061	if (info->needCacheFlush) {					\
1062	    RADEON_PURGE_CACHE();					\
1063	    RADEON_PURGE_ZCACHE();					\
1064	    info->needCacheFlush = FALSE;				\
1065	}								\
1066	RADEON_WAIT_UNTIL_IDLE();					\
1067        if (info->ChipFamily <= CHIP_FAMILY_RV280) {                    \
1068	    BEGIN_RING(6);						\
1069	    OUT_RING_REG(RADEON_RE_TOP_LEFT,     info->re_top_left);	\
1070	    OUT_RING_REG(RADEON_RE_WIDTH_HEIGHT, info->re_width_height); \
1071	    OUT_RING_REG(RADEON_AUX_SC_CNTL,     info->aux_sc_cntl);	\
1072	    ADVANCE_RING();						\
1073        } else {                                                        \
1074            BEGIN_RING(4);                                              \
1075            OUT_RING_REG(R300_SC_SCISSOR0, info->re_top_left);          \
1076	    OUT_RING_REG(R300_SC_SCISSOR1, info->re_width_height);      \
1077            ADVANCE_RING();                                             \
1078	}                                                               \
1079	info->CPInUse = TRUE;						\
1080    }									\
1081} while (0)
1082
1083
1084#define CP_PACKET0(reg, n)						\
1085	(RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1086#define CP_PACKET1(reg0, reg1)						\
1087	(RADEON_CP_PACKET1 | (((reg1) >> 2) << 11) | ((reg0) >> 2))
1088#define CP_PACKET2()							\
1089	(RADEON_CP_PACKET2)
1090#define CP_PACKET3(pkt, n)						\
1091	(RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
1092
1093
1094#define RADEON_VERBOSE	0
1095
1096#define RING_LOCALS	uint32_t *__head = NULL; int __expected; int __count = 0
1097
1098#define BEGIN_RING(n) do {						\
1099    if (RADEON_VERBOSE) {						\
1100	xf86DrvMsg(pScrn->scrnIndex, X_INFO,				\
1101		   "BEGIN_RING(%d) in %s\n", (unsigned int)n, __FUNCTION__);\
1102    }									\
1103    if (++info->dma_begin_count != 1) {					\
1104	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,				\
1105		   "BEGIN_RING without end at %s:%d\n",			\
1106		   info->dma_debug_func, info->dma_debug_lineno);	\
1107	info->dma_begin_count = 1;					\
1108    }									\
1109    info->dma_debug_func = __FILE__;					\
1110    info->dma_debug_lineno = __LINE__;					\
1111    if (!info->indirectBuffer) {					\
1112	info->indirectBuffer = RADEONCPGetBuffer(pScrn);		\
1113	info->indirectStart = 0;					\
1114    } else if (info->indirectBuffer->used + (n) * (int)sizeof(uint32_t) >	\
1115	       info->indirectBuffer->total) {				\
1116	RADEONCPFlushIndirect(pScrn, 1);				\
1117    }									\
1118    __expected = n;							\
1119    __head = (pointer)((char *)info->indirectBuffer->address +		\
1120		       info->indirectBuffer->used);			\
1121    __count = 0;							\
1122} while (0)
1123
1124#define ADVANCE_RING() do {						\
1125    if (info->dma_begin_count-- != 1) {					\
1126	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,				\
1127		   "ADVANCE_RING without begin at %s:%d\n",		\
1128		   __FILE__, __LINE__);					\
1129	info->dma_begin_count = 0;					\
1130    }									\
1131    if (__count != __expected) {					\
1132	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,				\
1133		   "ADVANCE_RING count != expected (%d vs %d) at %s:%d\n", \
1134		   __count, __expected, __FILE__, __LINE__);		\
1135    }									\
1136    if (RADEON_VERBOSE) {						\
1137	xf86DrvMsg(pScrn->scrnIndex, X_INFO,				\
1138		   "ADVANCE_RING() start: %d used: %d count: %d\n",	\
1139		   info->indirectStart,					\
1140		   info->indirectBuffer->used,				\
1141		   __count * (int)sizeof(uint32_t));			\
1142    }									\
1143    info->indirectBuffer->used += __count * (int)sizeof(uint32_t);	\
1144} while (0)
1145
1146#define OUT_RING(x) do {						\
1147    if (RADEON_VERBOSE) {						\
1148	xf86DrvMsg(pScrn->scrnIndex, X_INFO,				\
1149		   "   OUT_RING(0x%08x)\n", (unsigned int)(x));		\
1150    }									\
1151    __head[__count++] = (x);						\
1152} while (0)
1153
1154#define OUT_RING_REG(reg, val)						\
1155do {									\
1156    OUT_RING(CP_PACKET0(reg, 0));					\
1157    OUT_RING(val);							\
1158} while (0)
1159
1160#define FLUSH_RING()							\
1161do {									\
1162    if (RADEON_VERBOSE)							\
1163	xf86DrvMsg(pScrn->scrnIndex, X_INFO,				\
1164		   "FLUSH_RING in %s\n", __FUNCTION__);			\
1165    if (info->indirectBuffer) {						\
1166	RADEONCPFlushIndirect(pScrn, 0);				\
1167    }									\
1168} while (0)
1169
1170
1171#define RADEON_WAIT_UNTIL_2D_IDLE()					\
1172do {									\
1173    BEGIN_RING(2);							\
1174    OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));				\
1175    OUT_RING((RADEON_WAIT_2D_IDLECLEAN |				\
1176	      RADEON_WAIT_HOST_IDLECLEAN));				\
1177    ADVANCE_RING();							\
1178} while (0)
1179
1180#define RADEON_WAIT_UNTIL_3D_IDLE()					\
1181do {									\
1182    BEGIN_RING(2);							\
1183    OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));				\
1184    OUT_RING((RADEON_WAIT_3D_IDLECLEAN |				\
1185	      RADEON_WAIT_HOST_IDLECLEAN));				\
1186    ADVANCE_RING();							\
1187} while (0)
1188
1189#define RADEON_WAIT_UNTIL_IDLE()					\
1190do {									\
1191    if (RADEON_VERBOSE) {						\
1192	xf86DrvMsg(pScrn->scrnIndex, X_INFO,				\
1193		   "WAIT_UNTIL_IDLE() in %s\n", __FUNCTION__);		\
1194    }									\
1195    BEGIN_RING(2);							\
1196    OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));				\
1197    OUT_RING((RADEON_WAIT_2D_IDLECLEAN |				\
1198	      RADEON_WAIT_3D_IDLECLEAN |				\
1199	      RADEON_WAIT_HOST_IDLECLEAN));				\
1200    ADVANCE_RING();							\
1201} while (0)
1202
1203#define RADEON_PURGE_CACHE()						\
1204do {									\
1205    BEGIN_RING(2);							\
1206    if (info->ChipFamily <= CHIP_FAMILY_RV280) {                        \
1207        OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));		\
1208        OUT_RING(RADEON_RB3D_DC_FLUSH_ALL);				\
1209    } else {                                                            \
1210        OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));		\
1211        OUT_RING(R300_RB3D_DC_FLUSH_ALL);				\
1212    }                                                                   \
1213    ADVANCE_RING();							\
1214} while (0)
1215
1216#define RADEON_PURGE_ZCACHE()						\
1217do {									\
1218    BEGIN_RING(2);							\
1219    if (info->ChipFamily <= CHIP_FAMILY_RV280) {                        \
1220        OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));		\
1221        OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL);				\
1222    } else {                                                            \
1223        OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));		\
1224        OUT_RING(R300_ZC_FLUSH_ALL);					\
1225    }                                                                   \
1226    ADVANCE_RING();							\
1227} while (0)
1228
1229#endif /* XF86DRI */
1230
1231static __inline__ void RADEON_MARK_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn)
1232{
1233#ifdef USE_EXA
1234    if (info->useEXA)
1235	exaMarkSync(pScrn->pScreen);
1236#endif
1237#ifdef USE_XAA
1238    if (!info->useEXA)
1239	SET_SYNC_FLAG(info->accel);
1240#endif
1241}
1242
1243static __inline__ void RADEON_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn)
1244{
1245#ifdef USE_EXA
1246    if (info->useEXA)
1247	exaWaitSync(pScrn->pScreen);
1248#endif
1249#ifdef USE_XAA
1250    if (!info->useEXA && info->accel)
1251	info->accel->Sync(pScrn);
1252#endif
1253}
1254
1255static __inline__ void radeon_init_timeout(struct timeval *endtime,
1256    unsigned int timeout)
1257{
1258    gettimeofday(endtime, NULL);
1259    endtime->tv_usec += timeout;
1260    endtime->tv_sec += endtime->tv_usec / 1000000;
1261    endtime->tv_usec %= 1000000;
1262}
1263
1264static __inline__ int radeon_timedout(const struct timeval *endtime)
1265{
1266    struct timeval now;
1267    gettimeofday(&now, NULL);
1268    return now.tv_sec == endtime->tv_sec ?
1269        now.tv_usec > endtime->tv_usec : now.tv_sec > endtime->tv_sec;
1270}
1271
1272#endif /* _RADEON_H_ */
1273