radeon.h revision 2f39173d
1/* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining 8 * a copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation on the rights to use, copy, modify, merge, 11 * publish, distribute, sublicense, and/or sell copies of the Software, 12 * and to permit persons to whom the Software is furnished to do so, 13 * subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 */ 28 29/* 30 * Authors: 31 * Kevin E. Martin <martin@xfree86.org> 32 * Rickard E. Faith <faith@valinux.com> 33 * Alan Hourihane <alanh@fairlite.demon.co.uk> 34 * 35 */ 36 37#ifndef _RADEON_H_ 38#define _RADEON_H_ 39 40#include <stdlib.h> /* For abs() */ 41#include <unistd.h> /* For usleep() */ 42#include <sys/time.h> /* For gettimeofday() */ 43 44#include "config.h" 45#include "xf86str.h" 46#include "compiler.h" 47#include "xf86fbman.h" 48 49 /* PCI support */ 50#include "xf86Pci.h" 51 52#ifdef USE_EXA 53#include "exa.h" 54#endif 55#ifdef USE_XAA 56#include "xaa.h" 57#endif 58 59 /* Exa and Cursor Support */ 60#include "vbe.h" 61#include "xf86Cursor.h" 62 63 /* DDC support */ 64#include "xf86DDC.h" 65 66 /* Xv support */ 67#include "xf86xv.h" 68 69#include "radeon_probe.h" 70#include "radeon_tv.h" 71 72 /* DRI support */ 73#ifdef XF86DRI 74#define _XF86DRI_SERVER_ 75#include "dri.h" 76#include "GL/glxint.h" 77#include "xf86drm.h" 78#include "radeon_drm.h" 79 80#ifdef DAMAGE 81#include "damage.h" 82#include "globals.h" 83#endif 84#endif 85 86#include "xf86Crtc.h" 87#include "X11/Xatom.h" 88 89#ifdef XF86DRM_MODE 90#include "radeon_bo.h" 91#include "radeon_cs.h" 92#include "radeon_dri2.h" 93#include "drmmode_display.h" 94#else 95#include "radeon_dummy_bufmgr.h" 96#endif 97 98 /* Render support */ 99#ifdef RENDER 100#include "picturestr.h" 101#endif 102 103#include "simple_list.h" 104#include "atipcirename.h" 105 106#ifndef MAX 107#define MAX(a,b) ((a)>(b)?(a):(b)) 108#endif 109#ifndef MIN 110#define MIN(a,b) ((a)>(b)?(b):(a)) 111#endif 112 113#if HAVE_BYTESWAP_H 114#include <byteswap.h> 115#elif defined(USE_SYS_ENDIAN_H) 116#include <sys/endian.h> 117#else 118#define bswap_16(value) \ 119 ((((value) & 0xff) << 8) | ((value) >> 8)) 120 121#define bswap_32(value) \ 122 (((uint32_t)bswap_16((uint16_t)((value) & 0xffff)) << 16) | \ 123 (uint32_t)bswap_16((uint16_t)((value) >> 16))) 124 125#define bswap_64(value) \ 126 (((uint64_t)bswap_32((uint32_t)((value) & 0xffffffff)) \ 127 << 32) | \ 128 (uint64_t)bswap_32((uint32_t)((value) >> 32))) 129#endif 130 131#if X_BYTE_ORDER == X_BIG_ENDIAN 132#define le32_to_cpu(x) bswap_32(x) 133#define le16_to_cpu(x) bswap_16(x) 134#define cpu_to_le32(x) bswap_32(x) 135#define cpu_to_le16(x) bswap_16(x) 136#else 137#define le32_to_cpu(x) (x) 138#define le16_to_cpu(x) (x) 139#define cpu_to_le32(x) (x) 140#define cpu_to_le16(x) (x) 141#endif 142 143/* Provide substitutes for gcc's __FUNCTION__ on other compilers */ 144#if !defined(__GNUC__) && !defined(__FUNCTION__) 145# define __FUNCTION__ __func__ /* C99 */ 146#endif 147 148#ifndef HAVE_XF86MODEBANDWIDTH 149extern unsigned int xf86ModeBandwidth(DisplayModePtr mode, int depth); 150#define MODE_BANDWIDTH MODE_BAD 151#endif 152 153typedef enum { 154 OPTION_NOACCEL, 155 OPTION_SW_CURSOR, 156 OPTION_DAC_6BIT, 157 OPTION_DAC_8BIT, 158#ifdef XF86DRI 159 OPTION_BUS_TYPE, 160 OPTION_CP_PIO, 161 OPTION_USEC_TIMEOUT, 162 OPTION_AGP_MODE, 163 OPTION_AGP_FW, 164 OPTION_GART_SIZE, 165 OPTION_GART_SIZE_OLD, 166 OPTION_RING_SIZE, 167 OPTION_BUFFER_SIZE, 168 OPTION_DEPTH_MOVE, 169 OPTION_PAGE_FLIP, 170 OPTION_NO_BACKBUFFER, 171 OPTION_XV_DMA, 172 OPTION_FBTEX_PERCENT, 173 OPTION_DEPTH_BITS, 174 OPTION_PCIAPER_SIZE, 175#ifdef USE_EXA 176 OPTION_ACCEL_DFS, 177 OPTION_EXA_PIXMAPS, 178#endif 179#endif 180 OPTION_IGNORE_EDID, 181 OPTION_CUSTOM_EDID, 182 OPTION_DISP_PRIORITY, 183 OPTION_PANEL_SIZE, 184 OPTION_MIN_DOTCLOCK, 185 OPTION_COLOR_TILING, 186#ifdef XvExtension 187 OPTION_VIDEO_KEY, 188 OPTION_RAGE_THEATRE_CRYSTAL, 189 OPTION_RAGE_THEATRE_TUNER_PORT, 190 OPTION_RAGE_THEATRE_COMPOSITE_PORT, 191 OPTION_RAGE_THEATRE_SVIDEO_PORT, 192 OPTION_TUNER_TYPE, 193 OPTION_RAGE_THEATRE_MICROC_PATH, 194 OPTION_RAGE_THEATRE_MICROC_TYPE, 195 OPTION_SCALER_WIDTH, 196#endif 197#ifdef RENDER 198 OPTION_RENDER_ACCEL, 199 OPTION_SUBPIXEL_ORDER, 200#endif 201 OPTION_SHOWCACHE, 202 OPTION_CLOCK_GATING, 203 OPTION_BIOS_HOTKEYS, 204 OPTION_VGA_ACCESS, 205 OPTION_REVERSE_DDC, 206 OPTION_LVDS_PROBE_PLL, 207 OPTION_ACCELMETHOD, 208 OPTION_CONNECTORTABLE, 209 OPTION_DRI, 210 OPTION_DEFAULT_CONNECTOR_TABLE, 211#if defined(__powerpc__) 212 OPTION_MAC_MODEL, 213#endif 214 OPTION_DEFAULT_TMDS_PLL, 215 OPTION_TVDAC_LOAD_DETECT, 216 OPTION_FORCE_TVOUT, 217 OPTION_TVSTD, 218 OPTION_IGNORE_LID_STATUS, 219 OPTION_DEFAULT_TVDAC_ADJ, 220 OPTION_INT10, 221 OPTION_EXA_VSYNC, 222 OPTION_ATOM_TVOUT, 223 OPTION_R4XX_ATOM, 224 OPTION_FORCE_LOW_POWER, 225 OPTION_DYNAMIC_PM, 226 OPTION_NEW_PLL, 227 OPTION_ZAPHOD_HEADS 228} RADEONOpts; 229 230 231#define RADEON_IDLE_RETRY 16 /* Fall out of idle loops after this count */ 232#define RADEON_TIMEOUT 2000000 /* Fall out of wait loops after this count */ 233 234#define RADEON_VSYNC_TIMEOUT 20000 /* Maximum wait for VSYNC (in usecs) */ 235 236/* Buffer are aligned on 4096 byte boundaries */ 237#define RADEON_GPU_PAGE_SIZE 4096 238#define RADEON_BUFFER_ALIGN (RADEON_GPU_PAGE_SIZE - 1) 239#define RADEON_VBIOS_SIZE 0x00010000 240#define RADEON_USE_RMX 0x80000000 /* mode flag for using RMX 241 * Need to comfirm this is not used 242 * for something else. 243 */ 244 245#define xFixedToFloat(f) (((float) (f)) / 65536) 246 247#define RADEON_LOGLEVEL_DEBUG 4 248 249/* for Xv, outputs */ 250#define MAKE_ATOM(a) MakeAtom(a, sizeof(a) - 1, TRUE) 251 252/* Other macros */ 253#define RADEON_ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) 254#define RADEON_ALIGN(x,bytes) (((x) + ((bytes) - 1)) & ~((bytes) - 1)) 255#define RADEONPTR(pScrn) ((RADEONInfoPtr)(pScrn)->driverPrivate) 256 257typedef struct { 258 int revision; 259 uint16_t rr1_offset; 260 uint16_t rr2_offset; 261 uint16_t dyn_clk_offset; 262 uint16_t pll_offset; 263 uint16_t mem_config_offset; 264 uint16_t mem_reset_offset; 265 uint16_t short_mem_offset; 266 uint16_t rr3_offset; 267 uint16_t rr4_offset; 268} RADEONBIOSInitTable; 269 270#define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 271#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 272#define RADEON_PLL_USE_REF_DIV (1 << 2) 273#define RADEON_PLL_LEGACY (1 << 3) 274#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 275#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 276#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 277#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 278#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 279#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 280#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 281#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 282#define RADEON_PLL_USE_POST_DIV (1 << 12) 283 284typedef struct { 285 uint32_t reference_freq; 286 uint32_t reference_div; 287 uint32_t post_div; 288 uint32_t pll_in_min; 289 uint32_t pll_in_max; 290 uint32_t pll_out_min; 291 uint32_t pll_out_max; 292 uint16_t xclk; 293 294 uint32_t min_ref_div; 295 uint32_t max_ref_div; 296 uint32_t min_post_div; 297 uint32_t max_post_div; 298 uint32_t min_feedback_div; 299 uint32_t max_feedback_div; 300 uint32_t min_frac_feedback_div; 301 uint32_t max_frac_feedback_div; 302 uint32_t best_vco; 303} RADEONPLLRec, *RADEONPLLPtr; 304 305typedef struct { 306 int bitsPerPixel; 307 int depth; 308 int displayWidth; 309 int displayHeight; 310 int pixel_code; 311 int pixel_bytes; 312 DisplayModePtr mode; 313} RADEONFBLayout; 314 315typedef enum { 316 CHIP_FAMILY_UNKNOW, 317 CHIP_FAMILY_LEGACY, 318 CHIP_FAMILY_RADEON, 319 CHIP_FAMILY_RV100, 320 CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/ 321 CHIP_FAMILY_RV200, 322 CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */ 323 CHIP_FAMILY_R200, 324 CHIP_FAMILY_RV250, 325 CHIP_FAMILY_RS300, /* RS300/RS350 */ 326 CHIP_FAMILY_RV280, 327 CHIP_FAMILY_R300, 328 CHIP_FAMILY_R350, 329 CHIP_FAMILY_RV350, 330 CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ 331 CHIP_FAMILY_R420, /* R420/R423/M18 */ 332 CHIP_FAMILY_RV410, /* RV410, M26 */ 333 CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400) Intel */ 334 CHIP_FAMILY_RS480, /* xpress 200, 200m (RS410/480/482/485) AMD */ 335 CHIP_FAMILY_RV515, /* rv515 */ 336 CHIP_FAMILY_R520, /* r520 */ 337 CHIP_FAMILY_RV530, /* rv530 */ 338 CHIP_FAMILY_R580, /* r580 */ 339 CHIP_FAMILY_RV560, /* rv560 */ 340 CHIP_FAMILY_RV570, /* rv570 */ 341 CHIP_FAMILY_RS600, 342 CHIP_FAMILY_RS690, 343 CHIP_FAMILY_RS740, 344 CHIP_FAMILY_R600, /* r600 */ 345 CHIP_FAMILY_RV610, 346 CHIP_FAMILY_RV630, 347 CHIP_FAMILY_RV670, 348 CHIP_FAMILY_RV620, 349 CHIP_FAMILY_RV635, 350 CHIP_FAMILY_RS780, 351 CHIP_FAMILY_RS880, 352 CHIP_FAMILY_RV770, /* r700 */ 353 CHIP_FAMILY_RV730, 354 CHIP_FAMILY_RV710, 355 CHIP_FAMILY_RV740, 356 CHIP_FAMILY_CEDAR, /* evergreen */ 357 CHIP_FAMILY_REDWOOD, 358 CHIP_FAMILY_JUNIPER, 359 CHIP_FAMILY_CYPRESS, 360 CHIP_FAMILY_HEMLOCK, 361 CHIP_FAMILY_LAST 362} RADEONChipFamily; 363 364#define IS_RV100_VARIANT ((info->ChipFamily == CHIP_FAMILY_RV100) || \ 365 (info->ChipFamily == CHIP_FAMILY_RV200) || \ 366 (info->ChipFamily == CHIP_FAMILY_RS100) || \ 367 (info->ChipFamily == CHIP_FAMILY_RS200) || \ 368 (info->ChipFamily == CHIP_FAMILY_RV250) || \ 369 (info->ChipFamily == CHIP_FAMILY_RV280) || \ 370 (info->ChipFamily == CHIP_FAMILY_RS300)) 371 372 373#define IS_R300_VARIANT ((info->ChipFamily == CHIP_FAMILY_R300) || \ 374 (info->ChipFamily == CHIP_FAMILY_RV350) || \ 375 (info->ChipFamily == CHIP_FAMILY_R350) || \ 376 (info->ChipFamily == CHIP_FAMILY_RV380) || \ 377 (info->ChipFamily == CHIP_FAMILY_R420) || \ 378 (info->ChipFamily == CHIP_FAMILY_RV410) || \ 379 (info->ChipFamily == CHIP_FAMILY_RS400) || \ 380 (info->ChipFamily == CHIP_FAMILY_RS480)) 381 382#define IS_AVIVO_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV515)) 383 384#define IS_DCE3_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV620)) 385 386#define IS_DCE32_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV730)) 387 388#define IS_DCE4_VARIANT ((info->ChipFamily >= CHIP_FAMILY_CEDAR)) 389 390#define IS_R600_3D (info->ChipFamily >= CHIP_FAMILY_R600) 391 392#define IS_R500_3D ((info->ChipFamily == CHIP_FAMILY_RV515) || \ 393 (info->ChipFamily == CHIP_FAMILY_R520) || \ 394 (info->ChipFamily == CHIP_FAMILY_RV530) || \ 395 (info->ChipFamily == CHIP_FAMILY_R580) || \ 396 (info->ChipFamily == CHIP_FAMILY_RV560) || \ 397 (info->ChipFamily == CHIP_FAMILY_RV570)) 398 399#define IS_R400_3D ((info->ChipFamily == CHIP_FAMILY_R420) || \ 400 (info->ChipFamily == CHIP_FAMILY_RV410) || \ 401 (info->ChipFamily == CHIP_FAMILY_RS690) || \ 402 (info->ChipFamily == CHIP_FAMILY_RS600) || \ 403 (info->ChipFamily == CHIP_FAMILY_RS740)) 404 405#define IS_R300_3D ((info->ChipFamily == CHIP_FAMILY_R300) || \ 406 (info->ChipFamily == CHIP_FAMILY_RV350) || \ 407 (info->ChipFamily == CHIP_FAMILY_R350) || \ 408 (info->ChipFamily == CHIP_FAMILY_RV380) || \ 409 (info->ChipFamily == CHIP_FAMILY_R420) || \ 410 (info->ChipFamily == CHIP_FAMILY_RV410) || \ 411 (info->ChipFamily == CHIP_FAMILY_RS690) || \ 412 (info->ChipFamily == CHIP_FAMILY_RS600) || \ 413 (info->ChipFamily == CHIP_FAMILY_RS740) || \ 414 (info->ChipFamily == CHIP_FAMILY_RS400) || \ 415 (info->ChipFamily == CHIP_FAMILY_RS480)) 416 417#define IS_R200_3D ((info->ChipFamily == CHIP_FAMILY_RV250) || \ 418 (info->ChipFamily == CHIP_FAMILY_RV280) || \ 419 (info->ChipFamily == CHIP_FAMILY_RS300) || \ 420 (info->ChipFamily == CHIP_FAMILY_R200)) 421 422/* 423 * Errata workarounds 424 */ 425typedef enum { 426 CHIP_ERRATA_R300_CG = 0x00000001, 427 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 428 CHIP_ERRATA_PLL_DELAY = 0x00000004 429} RADEONErrata; 430 431typedef enum { 432 RADEON_DVOCHIP_NONE, 433 RADEON_SIL_164, 434 RADEON_SIL_1178 435} RADEONExtTMDSChip; 436 437#if defined(__powerpc__) 438typedef enum { 439 RADEON_MAC_NONE, 440 RADEON_MAC_IBOOK, 441 RADEON_MAC_POWERBOOK_EXTERNAL, 442 RADEON_MAC_POWERBOOK_INTERNAL, 443 RADEON_MAC_POWERBOOK_VGA, 444 RADEON_MAC_MINI_EXTERNAL, 445 RADEON_MAC_MINI_INTERNAL, 446 RADEON_MAC_IMAC_G5_ISIGHT, 447 RADEON_MAC_EMAC 448} RADEONMacModel; 449#endif 450 451typedef enum { 452 CARD_PCI, 453 CARD_AGP, 454 CARD_PCIE 455} RADEONCardType; 456 457typedef enum { 458 POWER_DEFAULT, 459 POWER_LOW, 460 POWER_HIGH 461} RADEONPMType; 462 463typedef struct { 464 RADEONPMType type; 465 uint32_t sclk; 466 uint32_t mclk; 467 uint32_t pcie_lanes; 468 uint32_t flags; 469} RADEONPowerMode; 470 471typedef struct { 472 /* power modes */ 473 int num_modes; 474 int current_mode; 475 RADEONPowerMode mode[3]; 476 477 Bool clock_gating_enabled; 478 Bool dynamic_mode_enabled; 479 Bool force_low_power_enabled; 480} RADEONPowerManagement; 481 482typedef struct _atomBiosHandle *atomBiosHandlePtr; 483 484struct radeon_exa_pixmap_priv { 485 struct radeon_bo *bo; 486 int flags; 487 Bool bo_mapped; 488}; 489 490typedef struct { 491 uint32_t pci_device_id; 492 RADEONChipFamily chip_family; 493 int mobility; 494 int igp; 495 int nocrtc2; 496 int nointtvout; 497 int singledac; 498} RADEONCardInfo; 499 500#define RADEON_2D_EXA_COPY 1 501#define RADEON_2D_EXA_SOLID 2 502 503struct radeon_2d_state { 504 int op; // 505 uint32_t dst_pitch_offset; 506 uint32_t src_pitch_offset; 507 uint32_t dp_gui_master_cntl; 508 uint32_t dp_cntl; 509 uint32_t dp_write_mask; 510 uint32_t dp_brush_frgd_clr; 511 uint32_t dp_brush_bkgd_clr; 512 uint32_t dp_src_frgd_clr; 513 uint32_t dp_src_bkgd_clr; 514 uint32_t default_sc_bottom_right; 515 struct radeon_bo *dst_bo; 516 struct radeon_bo *src_bo; 517}; 518 519#ifdef XF86DRI 520struct radeon_cp { 521 Bool CPRuns; /* CP is running */ 522 Bool CPInUse; /* CP has been used by X server */ 523 Bool CPStarted; /* CP has started */ 524 int CPMode; /* CP mode that server/clients use */ 525 int CPFifoSize; /* Size of the CP command FIFO */ 526 int CPusecTimeout; /* CP timeout in usecs */ 527 Bool needCacheFlush; 528 529 /* CP accleration */ 530 drmBufPtr indirectBuffer; 531 int indirectStart; 532 533 /* Debugging info for BEGIN_RING/ADVANCE_RING pairs. */ 534 int dma_begin_count; 535 char *dma_debug_func; 536 int dma_debug_lineno; 537 538 }; 539 540typedef struct { 541 /* Nothing here yet */ 542 int dummy; 543} RADEONConfigPrivRec, *RADEONConfigPrivPtr; 544 545typedef struct { 546 /* Nothing here yet */ 547 int dummy; 548} RADEONDRIContextRec, *RADEONDRIContextPtr; 549 550struct radeon_dri { 551 Bool noBackBuffer; 552 553 Bool newMemoryMap; 554 drmVersionPtr pLibDRMVersion; 555 drmVersionPtr pKernelDRMVersion; 556 DRIInfoPtr pDRIInfo; 557 int drmFD; 558 int numVisualConfigs; 559 __GLXvisualConfig *pVisualConfigs; 560 RADEONConfigPrivPtr pVisualConfigsPriv; 561 Bool (*DRICloseScreen)(int, ScreenPtr); 562 563 drm_handle_t fbHandle; 564 565 drmSize registerSize; 566 drm_handle_t registerHandle; 567 568 drmSize pciSize; 569 drm_handle_t pciMemHandle; 570 unsigned char *PCI; /* Map */ 571 572 Bool depthMoves; /* Enable depth moves -- slow! */ 573 Bool allowPageFlip; /* Enable 3d page flipping */ 574#ifdef DAMAGE 575 DamagePtr pDamage; 576 RegionRec driRegion; 577#endif 578 Bool have3DWindows; /* Are there any 3d clients? */ 579 580 int pciAperSize; 581 drmSize gartSize; 582 drm_handle_t agpMemHandle; /* Handle from drmAgpAlloc */ 583 unsigned long gartOffset; 584 unsigned char *AGP; /* Map */ 585 int agpMode; 586 587 uint32_t pciCommand; 588 589 /* CP ring buffer data */ 590 unsigned long ringStart; /* Offset into GART space */ 591 drm_handle_t ringHandle; /* Handle from drmAddMap */ 592 drmSize ringMapSize; /* Size of map */ 593 int ringSize; /* Size of ring (in MB) */ 594 drmAddress ring; /* Map */ 595 int ringSizeLog2QW; 596 597 unsigned long ringReadOffset; /* Offset into GART space */ 598 drm_handle_t ringReadPtrHandle; /* Handle from drmAddMap */ 599 drmSize ringReadMapSize; /* Size of map */ 600 drmAddress ringReadPtr; /* Map */ 601 602 /* CP vertex/indirect buffer data */ 603 unsigned long bufStart; /* Offset into GART space */ 604 drm_handle_t bufHandle; /* Handle from drmAddMap */ 605 drmSize bufMapSize; /* Size of map */ 606 int bufSize; /* Size of buffers (in MB) */ 607 drmAddress buf; /* Map */ 608 int bufNumBufs; /* Number of buffers */ 609 drmBufMapPtr buffers; /* Buffer map */ 610 611 /* CP GART Texture data */ 612 unsigned long gartTexStart; /* Offset into GART space */ 613 drm_handle_t gartTexHandle; /* Handle from drmAddMap */ 614 drmSize gartTexMapSize; /* Size of map */ 615 int gartTexSize; /* Size of GART tex space (in MB) */ 616 drmAddress gartTex; /* Map */ 617 int log2GARTTexGran; 618 619 /* DRI screen private data */ 620 int fbX; 621 int fbY; 622 int backX; 623 int backY; 624 int depthX; 625 int depthY; 626 627 int frontOffset; 628 int frontPitch; 629 int backOffset; 630 int backPitch; 631 int depthOffset; 632 int depthPitch; 633 int depthBits; 634 int textureOffset; 635 int textureSize; 636 int log2TexGran; 637 638 int pciGartSize; 639 uint32_t pciGartOffset; 640 void *pciGartBackup; 641 642 int irq; 643 644#ifdef USE_XAA 645 uint32_t frontPitchOffset; 646 uint32_t backPitchOffset; 647 uint32_t depthPitchOffset; 648 649 /* offscreen memory management */ 650 int backLines; 651 FBAreaPtr backArea; 652 int depthTexLines; 653 FBAreaPtr depthTexArea; 654#endif 655 656}; 657#endif 658 659#define DMA_BO_FREE_TIME 1000 660 661struct radeon_dma_bo { 662 struct radeon_dma_bo *next, *prev; 663 struct radeon_bo *bo; 664 int expire_counter; 665}; 666 667struct r600_accel_object { 668 uint32_t pitch; 669 uint32_t width; 670 uint32_t height; 671 uint32_t offset; 672 int bpp; 673 uint32_t domain; 674 struct radeon_bo *bo; 675}; 676 677struct radeon_accel_state { 678 /* common accel data */ 679 int fifo_slots; /* Free slots in the FIFO (64 max) */ 680 /* Computed values for Radeon */ 681 uint32_t dp_gui_master_cntl; 682 uint32_t dp_gui_master_cntl_clip; 683 uint32_t trans_color; 684 /* Saved values for ScreenToScreenCopy */ 685 int xdir; 686 int ydir; 687 uint32_t dst_pitch_offset; 688 689 /* render accel */ 690 unsigned short texW[2]; 691 unsigned short texH[2]; 692 Bool XInited3D; /* X itself has the 3D context */ 693 int num_gb_pipes; 694 Bool has_tcl; 695 696#ifdef USE_EXA 697 /* EXA */ 698 ExaDriverPtr exa; 699 int exaSyncMarker; 700 int exaMarkerSynced; 701 int engineMode; 702#define EXA_ENGINEMODE_UNKNOWN 0 703#define EXA_ENGINEMODE_2D 1 704#define EXA_ENGINEMODE_3D 2 705 706 int composite_op; 707 PicturePtr dst_pic; 708 PicturePtr msk_pic; 709 PicturePtr src_pic; 710 PixmapPtr dst_pix; 711 PixmapPtr msk_pix; 712 PixmapPtr src_pix; 713 Bool is_transform[2]; 714 PictTransform *transform[2]; 715 /* Whether we are tiling horizontally and vertically */ 716 Bool need_src_tile_x; 717 Bool need_src_tile_y; 718 /* Size of tiles ... set to 65536x65536 if not tiling in that direction */ 719 Bool src_tile_width; 720 Bool src_tile_height; 721 uint32_t *draw_header; 722 unsigned vtx_count; 723 unsigned num_vtx; 724 725 Bool vsync; 726 727 drmBufPtr ib; 728 int vb_offset; 729 uint64_t vb_mc_addr; 730 int vb_total; 731 void *vb_ptr; 732 uint32_t vb_size; 733 uint32_t vb_op_vert_size; 734 int32_t vb_start_op; 735 /* where to discard IB from if we cancel operation */ 736 uint32_t ib_reset_op; 737 struct radeon_bo *vb_bo; 738#ifdef XF86DRM_MODE 739 struct radeon_dma_bo bo_free; 740 struct radeon_dma_bo bo_wait; 741 struct radeon_dma_bo bo_reserved; 742 Bool use_vbos; 743#endif 744 745 // shader storage 746 ExaOffscreenArea *shaders; 747 struct radeon_bo *shaders_bo; 748 uint32_t solid_vs_offset; 749 uint32_t solid_ps_offset; 750 uint32_t copy_vs_offset; 751 uint32_t copy_ps_offset; 752 uint32_t comp_vs_offset; 753 uint32_t comp_ps_offset; 754 uint32_t comp_mask_ps_offset; 755 uint32_t xv_vs_offset; 756 uint32_t xv_ps_offset; 757 758 //size/addr stuff 759 struct r600_accel_object src_obj[2]; 760 struct r600_accel_object dst_obj; 761 uint32_t src_size[2]; 762 uint32_t dst_size; 763 764 uint32_t vs_size; 765 uint64_t vs_mc_addr; 766 uint32_t ps_size; 767 uint64_t ps_mc_addr; 768 769 // UTS/DFS 770 drmBufPtr scratch; 771 772 // copy 773 ExaOffscreenArea *copy_area; 774 struct radeon_bo *copy_area_bo; 775 Bool same_surface; 776 int rop; 777 uint32_t planemask; 778 779 // composite 780 Bool component_alpha; 781 Bool src_alpha; 782 // vline 783 xf86CrtcPtr vline_crtc; 784 int vline_y1; 785 int vline_y2; 786#endif 787 788#ifdef USE_XAA 789 /* XAA */ 790 XAAInfoRecPtr accel; 791 /* ScanlineScreenToScreenColorExpand support */ 792 unsigned char *scratch_buffer[1]; 793 unsigned char *scratch_save; 794 int scanline_x; 795 int scanline_y; 796 int scanline_w; 797 int scanline_h; 798 int scanline_h_w; 799 int scanline_words; 800 int scanline_direct; 801 int scanline_bpp; /* Only used for ImageWrite */ 802 int scanline_fg; 803 int scanline_bg; 804 int scanline_hpass; 805 int scanline_x1clip; 806 int scanline_x2clip; 807 /* Saved values for DashedTwoPointLine */ 808 int dashLen; 809 uint32_t dashPattern; 810 int dash_fg; 811 int dash_bg; 812 813 FBLinearPtr RenderTex; 814 void (*RenderCallback)(ScrnInfoPtr); 815 Time RenderTimeout; 816 /* 817 * XAAForceTransBlit is used to change the behavior of the XAA 818 * SetupForScreenToScreenCopy function, to make it DGA-friendly. 819 */ 820 Bool XAAForceTransBlit; 821#endif 822 823}; 824 825typedef struct { 826 EntityInfoPtr pEnt; 827 pciVideoPtr PciInfo; 828 PCITAG PciTag; 829 int Chipset; 830 RADEONChipFamily ChipFamily; 831 RADEONErrata ChipErrata; 832 833 unsigned long long LinearAddr; /* Frame buffer physical address */ 834 unsigned long long MMIOAddr; /* MMIO region physical address */ 835 unsigned long long BIOSAddr; /* BIOS physical address */ 836 uint32_t fbLocation; 837 uint32_t gartLocation; 838 uint32_t mc_fb_location; 839 uint32_t mc_agp_location; 840 uint32_t mc_agp_location_hi; 841 842 void *MMIO; /* Map of MMIO region */ 843 void *FB; /* Map of frame buffer */ 844 uint8_t *VBIOS; /* Video BIOS pointer */ 845 846 Bool IsAtomBios; /* New BIOS used in R420 etc. */ 847 int ROMHeaderStart; /* Start of the ROM Info Table */ 848 int MasterDataStart; /* Offset for Master Data Table for ATOM BIOS */ 849 850 uint32_t MemCntl; 851 uint32_t BusCntl; 852 unsigned long MMIOSize; /* MMIO region physical address */ 853 unsigned long FbMapSize; /* Size of frame buffer, in bytes */ 854 unsigned long FbSecureSize; /* Size of secured fb area at end of 855 framebuffer */ 856 857 Bool IsMobility; /* Mobile chips for laptops */ 858 Bool IsIGP; /* IGP chips */ 859 Bool HasSingleDAC; /* only TVDAC on chip */ 860 Bool ddc_mode; /* Validate mode by matching exactly 861 * the modes supported in DDC data 862 */ 863 Bool R300CGWorkaround; 864 865 /* EDID or BIOS values for FPs */ 866 int RefDivider; 867 int FeedbackDivider; 868 int PostDivider; 869 Bool UseBiosDividers; 870 /* EDID data using DDC interface */ 871 Bool ddc_bios; 872 Bool ddc1; 873 Bool ddc2; 874 875 RADEONPLLRec pll; 876 877 int RamWidth; 878 float sclk; /* in MHz */ 879 float mclk; /* in MHz */ 880 Bool IsDDR; 881 int DispPriority; 882 883 RADEONSavePtr SavedReg; /* Original (text) mode */ 884 RADEONSavePtr ModeReg; /* Current mode */ 885 Bool (*CloseScreen)(int, ScreenPtr); 886 887 void (*BlockHandler)(int, pointer, pointer, pointer); 888 889 Bool PaletteSavedOnVT; /* Palette saved on last VT switch */ 890 891 xf86CursorInfoPtr cursor; 892#ifdef ARGB_CURSOR 893 Bool cursor_argb; 894#endif 895 int cursor_fg; 896 int cursor_bg; 897 898 int pix24bpp; /* Depth of pixmap for 24bpp fb */ 899 Bool dac6bits; /* Use 6 bit DAC? */ 900 901 RADEONFBLayout CurrentLayout; 902 903#ifdef XF86DRI 904 Bool directRenderingEnabled; 905 Bool directRenderingInited; 906 RADEONCardType cardType; /* Current card is a PCI card */ 907 struct radeon_cp *cp; 908 struct radeon_dri *dri; 909#ifdef XF86DRM_MODE 910 struct radeon_dri2 dri2; 911#endif 912#ifdef USE_EXA 913 Bool accelDFS; 914#endif 915 Bool DMAForXv; 916#endif /* XF86DRI */ 917 918 /* accel */ 919 Bool RenderAccel; /* Render */ 920 Bool allowColorTiling; 921 Bool tilingEnabled; /* mirror of sarea->tiling_enabled */ 922 struct radeon_accel_state *accel_state; 923 Bool accelOn; 924 Bool useEXA; 925#ifdef USE_EXA 926 Bool exa_pixmaps; 927 Bool exa_force_create; 928 XF86ModReqInfo exaReq; 929#endif 930#ifdef USE_XAA 931 XF86ModReqInfo xaaReq; 932#endif 933 934 /* XVideo */ 935 XF86VideoAdaptorPtr adaptor; 936 void (*VideoTimerCallback)(ScrnInfoPtr, Time); 937 int videoKey; 938 int RageTheatreCrystal; 939 int RageTheatreTunerPort; 940 int RageTheatreCompositePort; 941 int RageTheatreSVideoPort; 942 int tunerType; 943 char* RageTheatreMicrocPath; 944 char* RageTheatreMicrocType; 945 Bool MM_TABLE_valid; 946 struct { 947 uint8_t table_revision; 948 uint8_t table_size; 949 uint8_t tuner_type; 950 uint8_t audio_chip; 951 uint8_t product_id; 952 uint8_t tuner_voltage_teletext_fm; 953 uint8_t i2s_config; /* configuration of the sound chip */ 954 uint8_t video_decoder_type; 955 uint8_t video_decoder_host_config; 956 uint8_t input[5]; 957 } MM_TABLE; 958 uint16_t video_decoder_type; 959 int overlay_scaler_buffer_width; 960 int ecp_div; 961 unsigned int xv_max_width; 962 unsigned int xv_max_height; 963 964 /* general */ 965 OptionInfoPtr Options; 966 967 DisplayModePtr currentMode, savedCurrentMode; 968 969 /* special handlings for DELL triple-head server */ 970 Bool IsDellServer; 971 972 Bool VGAAccess; 973 974 int MaxSurfaceWidth; 975 int MaxLines; 976 977 Bool want_vblank_interrupts; 978 RADEONBIOSConnector BiosConnector[RADEON_MAX_BIOS_CONNECTOR]; 979 radeon_encoder_ptr encoders[RADEON_MAX_BIOS_CONNECTOR]; 980 RADEONBIOSInitTable BiosTable; 981 982 /* save crtc state for console restore */ 983 Bool crtc_on; 984 Bool crtc2_on; 985 986 Bool InternalTVOut; 987 988#if defined(__powerpc__) 989 RADEONMacModel MacModel; 990#endif 991 RADEONExtTMDSChip ext_tmds_chip; 992 993 atomBiosHandlePtr atomBIOS; 994 unsigned long FbFreeStart, FbFreeSize; 995 unsigned char* BIOSCopy; 996 997 CreateScreenResourcesProcPtr CreateScreenResources; 998 999 /* if no devices are connected at server startup */ 1000 Bool first_load_no_devices; 1001 1002 Bool IsSecondary; 1003 Bool IsPrimary; 1004 1005 Bool r600_shadow_fb; 1006 void *fb_shadow; 1007 1008 /* some server chips have a hardcoded edid in the bios so that they work with KVMs */ 1009 Bool get_hardcoded_edid_from_bios; 1010 1011 int virtualX; 1012 int virtualY; 1013 1014 Bool r4xx_atom; 1015 1016 /* pm */ 1017 RADEONPowerManagement pm; 1018 1019 /* igp info */ 1020 float igp_sideport_mclk; 1021 float igp_system_mclk; 1022 float igp_ht_link_clk; 1023 float igp_ht_link_width; 1024 1025 int can_resize; 1026 void (*reemit_current2d)(ScrnInfoPtr pScrn, int op); // emit the current 2D state into the IB 1027 struct radeon_2d_state state_2d; 1028 Bool kms_enabled; 1029 struct radeon_bo *front_bo; 1030#ifdef XF86DRM_MODE 1031 struct radeon_bo_manager *bufmgr; 1032 struct radeon_cs_manager *csm; 1033 struct radeon_cs *cs; 1034 1035 struct radeon_bo *cursor_bo[6]; 1036 uint64_t vram_size; 1037 uint64_t gart_size; 1038 drmmode_rec drmmode; 1039#else 1040 /* fake bool */ 1041 Bool cs; 1042#endif 1043 1044 /* Xv bicubic filtering */ 1045 struct radeon_bo *bicubic_bo; 1046 void *bicubic_memory; 1047 int bicubic_offset; 1048} RADEONInfoRec, *RADEONInfoPtr; 1049 1050#define RADEONWaitForFifo(pScrn, entries) \ 1051do { \ 1052 if (info->accel_state->fifo_slots < entries) \ 1053 RADEONWaitForFifoFunction(pScrn, entries); \ 1054 info->accel_state->fifo_slots -= entries; \ 1055} while (0) 1056 1057/* legacy_crtc.c */ 1058extern void legacy_crtc_dpms(xf86CrtcPtr crtc, int mode); 1059extern void legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, 1060 DisplayModePtr adjusted_mode, int x, int y); 1061extern void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, 1062 RADEONSavePtr restore); 1063extern void RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn, 1064 RADEONSavePtr restore); 1065extern void RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, 1066 RADEONSavePtr restore); 1067extern void RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, 1068 RADEONSavePtr restore); 1069extern void RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, 1070 RADEONSavePtr restore); 1071extern void RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1072extern void RADEONSaveCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1073extern void RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save); 1074extern void RADEONSavePLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1075extern void RADEONSavePLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save); 1076 1077/* legacy_output.c */ 1078extern RADEONMonitorType legacy_dac_detect(xf86OutputPtr output); 1079extern void legacy_output_dpms(xf86OutputPtr output, int mode); 1080extern void legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, 1081 DisplayModePtr adjusted_mode); 1082extern I2CDevPtr RADEONDVODeviceInit(I2CBusPtr b, I2CSlaveAddr addr); 1083extern Bool RADEONDVOReadByte(I2CDevPtr dvo, int addr, uint8_t *ch); 1084extern Bool RADEONDVOWriteByte(I2CDevPtr dvo, int addr, uint8_t ch); 1085extern void RADEONRestoreDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1086extern void RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1087extern void RADEONRestoreFP2Registers(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1088extern void RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1089extern void RADEONRestoreRMXRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1090extern void RADEONSaveDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1091extern void RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1092 1093extern void RADEONGetTVDacAdjInfo(ScrnInfoPtr pScrn, radeon_tvdac_ptr tvdac); 1094extern void RADEONGetTMDSInfoFromTable(ScrnInfoPtr pScrn, radeon_tmds_ptr tmds); 1095extern void RADEONGetTMDSInfo(ScrnInfoPtr pScrn, radeon_tmds_ptr tmds); 1096extern void RADEONGetExtTMDSInfo(ScrnInfoPtr pScrn, radeon_dvo_ptr dvo); 1097extern void RADEONGetLVDSInfo(ScrnInfoPtr pScrn, radeon_lvds_ptr lvds); 1098 1099/* radeon_accel.c */ 1100extern Bool RADEONAccelInit(ScreenPtr pScreen); 1101extern void RADEONEngineFlush(ScrnInfoPtr pScrn); 1102extern void RADEONEngineInit(ScrnInfoPtr pScrn); 1103extern void RADEONEngineReset(ScrnInfoPtr pScrn); 1104extern void RADEONEngineRestore(ScrnInfoPtr pScrn); 1105extern uint8_t *RADEONHostDataBlit(ScrnInfoPtr pScrn, unsigned int cpp, 1106 unsigned int w, uint32_t dstPitchOff, 1107 uint32_t *bufPitch, int x, int *y, 1108 unsigned int *h, unsigned int *hpass); 1109extern void RADEONHostDataBlitCopyPass(ScrnInfoPtr pScrn, 1110 unsigned int bpp, 1111 uint8_t *dst, uint8_t *src, 1112 unsigned int hpass, 1113 unsigned int dstPitch, 1114 unsigned int srcPitch); 1115extern void RADEONCopySwap(uint8_t *dst, uint8_t *src, unsigned int size, int swap); 1116extern void RADEONHostDataParams(ScrnInfoPtr pScrn, uint8_t *dst, 1117 uint32_t pitch, int cpp, 1118 uint32_t *dstPitchOffset, int *x, int *y); 1119extern void RADEONInit3DEngine(ScrnInfoPtr pScrn); 1120extern void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries); 1121#ifdef XF86DRI 1122extern drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn); 1123extern void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard); 1124extern void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn); 1125extern int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info); 1126# ifdef USE_XAA 1127extern Bool RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen); 1128# endif 1129uint32_t radeonGetPixmapOffset(PixmapPtr pPix); 1130#endif 1131extern int radeon_cs_space_remaining(ScrnInfoPtr pScrn); 1132 1133#ifdef USE_XAA 1134/* radeon_accelfuncs.c */ 1135extern void RADEONAccelInitMMIO(ScreenPtr pScreen, XAAInfoRecPtr a); 1136extern Bool RADEONSetupMemXAA(int scrnIndex, ScreenPtr pScreen); 1137#endif 1138 1139/* radeon_bios.c */ 1140extern Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10); 1141extern Bool RADEONGetClockInfoFromBIOS(ScrnInfoPtr pScrn); 1142extern Bool RADEONGetConnectorInfoFromBIOS(ScrnInfoPtr pScrn); 1143extern Bool RADEONGetDAC2InfoFromBIOS(ScrnInfoPtr pScrn, radeon_tvdac_ptr tvdac); 1144extern Bool RADEONGetExtTMDSInfoFromBIOS (ScrnInfoPtr pScrn, radeon_dvo_ptr dvo); 1145extern xf86MonPtr RADEONGetHardCodedEDIDFromBIOS(xf86OutputPtr output); 1146extern Bool RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn); 1147extern Bool RADEONGetLVDSInfoFromBIOS(ScrnInfoPtr pScrn, radeon_lvds_ptr lvds); 1148extern Bool RADEONGetTMDSInfoFromBIOS(ScrnInfoPtr pScrn, radeon_tmds_ptr tmds); 1149extern Bool RADEONGetTVInfoFromBIOS(xf86OutputPtr output); 1150extern Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output); 1151extern Bool RADEONPostCardFromBIOSTables(ScrnInfoPtr pScrn); 1152extern Bool radeon_card_posted(ScrnInfoPtr pScrn); 1153 1154/* radeon_commonfuncs.c */ 1155#ifdef XF86DRI 1156extern void RADEONWaitForIdleCP(ScrnInfoPtr pScrn); 1157extern void RADEONWaitForVLineCP(ScrnInfoPtr pScrn, PixmapPtr pPix, 1158 xf86CrtcPtr crtc, int start, int stop); 1159#endif 1160extern void RADEONWaitForIdleMMIO(ScrnInfoPtr pScrn); 1161extern void RADEONWaitForVLineMMIO(ScrnInfoPtr pScrn, PixmapPtr pPix, 1162 xf86CrtcPtr crtc, int start, int stop); 1163 1164/* radeon_crtc.c */ 1165extern void radeon_crtc_dpms(xf86CrtcPtr crtc, int mode); 1166extern void radeon_crtc_load_lut(xf86CrtcPtr crtc); 1167extern void radeon_crtc_modeset_ioctl(xf86CrtcPtr crtc, Bool post); 1168extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask); 1169extern void RADEONBlank(ScrnInfoPtr pScrn); 1170extern void RADEONComputePLL(xf86CrtcPtr crtc, 1171 RADEONPLLPtr pll, unsigned long freq, 1172 uint32_t *chosen_dot_clock_freq, 1173 uint32_t *chosen_feedback_div, 1174 uint32_t *chosen_frac_feedback_div, 1175 uint32_t *chosen_reference_div, 1176 uint32_t *chosen_post_div, int flags); 1177extern DisplayModePtr RADEONCrtcFindClosestMode(xf86CrtcPtr crtc, 1178 DisplayModePtr pMode); 1179extern void RADEONUnblank(ScrnInfoPtr pScrn); 1180extern Bool RADEONSetTiling(ScrnInfoPtr pScrn); 1181extern void RADEONInitDispBandwidth(ScrnInfoPtr pScrn); 1182 1183/* radeon_cursor.c */ 1184extern Bool RADEONCursorInit(ScreenPtr pScreen); 1185extern void radeon_crtc_hide_cursor(xf86CrtcPtr crtc); 1186extern void radeon_crtc_load_cursor_argb(xf86CrtcPtr crtc, CARD32 *image); 1187extern void radeon_crtc_set_cursor_colors(xf86CrtcPtr crtc, int bg, int fg); 1188extern void radeon_crtc_set_cursor_position(xf86CrtcPtr crtc, int x, int y); 1189extern void radeon_crtc_show_cursor(xf86CrtcPtr crtc); 1190 1191#ifdef XF86DRI 1192/* radeon_dri.c */ 1193extern void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen); 1194extern void RADEONDRICloseScreen(ScreenPtr pScreen); 1195extern Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen); 1196extern int RADEONDRIGetPciAperTableSize(ScrnInfoPtr pScrn); 1197extern Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn); 1198extern void RADEONDRIResume(ScreenPtr pScreen); 1199extern Bool RADEONDRIScreenInit(ScreenPtr pScreen); 1200extern int RADEONDRISetParam(ScrnInfoPtr pScrn, 1201 unsigned int param, int64_t value); 1202extern Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on); 1203extern void RADEONDRIStop(ScreenPtr pScreen); 1204#endif 1205 1206/* radeon_driver.c */ 1207extern void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool clone); 1208extern void RADEONChangeSurfaces(ScrnInfoPtr pScrn); 1209extern RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn); 1210extern int RADEONMinBits(int val); 1211extern unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr); 1212extern unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr); 1213extern unsigned RADEONINPCIE(ScrnInfoPtr pScrn, int addr); 1214extern unsigned R600INPCIE_PORT(ScrnInfoPtr pScrn, int addr); 1215extern void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, uint32_t data); 1216extern void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, uint32_t data); 1217extern void RADEONOUTPCIE(ScrnInfoPtr pScrn, int addr, uint32_t data); 1218extern void R600OUTPCIE_PORT(ScrnInfoPtr pScrn, int addr, uint32_t data); 1219extern void RADEONPllErrataAfterData(RADEONInfoPtr info); 1220extern void RADEONPllErrataAfterIndex(RADEONInfoPtr info); 1221extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn); 1222extern void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn); 1223extern void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, 1224 RADEONInfoPtr info); 1225extern void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, 1226 RADEONSavePtr restore); 1227extern Bool 1228RADEONZaphodStringMatches(ScrnInfoPtr pScrn, const char *s, char *output_name); 1229 1230Bool RADEONGetRec(ScrnInfoPtr pScrn); 1231void RADEONFreeRec(ScrnInfoPtr pScrn); 1232Bool RADEONPreInitVisual(ScrnInfoPtr pScrn); 1233Bool RADEONPreInitWeight(ScrnInfoPtr pScrn); 1234 1235extern Bool RADEON_DP_I2CInit(ScrnInfoPtr pScrn, I2CBusPtr *bus_ptr, 1236 char *name, xf86OutputPtr output); 1237extern void RADEON_DP_GetDPCD(xf86OutputPtr output); 1238extern int RADEON_DP_GetSinkType(xf86OutputPtr output); 1239 1240/* radeon_pm.c */ 1241extern void RADEONPMInit(ScrnInfoPtr pScrn); 1242extern void RADEONPMBlockHandler(ScrnInfoPtr pScrn); 1243extern void RADEONPMEnterVT(ScrnInfoPtr pScrn); 1244extern void RADEONPMLeaveVT(ScrnInfoPtr pScrn); 1245extern void RADEONPMFini(ScrnInfoPtr pScrn); 1246 1247#ifdef USE_EXA 1248/* radeon_exa.c */ 1249extern Bool RADEONSetupMemEXA(ScreenPtr pScreen); 1250 1251/* radeon_exa_funcs.c */ 1252extern void RADEONCopyCP(PixmapPtr pDst, int srcX, int srcY, int dstX, 1253 int dstY, int w, int h); 1254extern void RADEONCopyMMIO(PixmapPtr pDst, int srcX, int srcY, int dstX, 1255 int dstY, int w, int h); 1256extern Bool RADEONDrawInitCP(ScreenPtr pScreen); 1257extern Bool RADEONDrawInitMMIO(ScreenPtr pScreen); 1258extern void RADEONDoPrepareCopyCP(ScrnInfoPtr pScrn, 1259 uint32_t src_pitch_offset, 1260 uint32_t dst_pitch_offset, 1261 uint32_t datatype, int rop, 1262 Pixel planemask); 1263extern void RADEONDoPrepareCopyMMIO(ScrnInfoPtr pScrn, 1264 uint32_t src_pitch_offset, 1265 uint32_t dst_pitch_offset, 1266 uint32_t datatype, int rop, 1267 Pixel planemask); 1268extern Bool R600DrawInit(ScreenPtr pScreen); 1269extern Bool R600LoadShaders(ScrnInfoPtr pScrn); 1270#endif 1271 1272#if defined(XF86DRI) && defined(USE_EXA) 1273/* radeon_exa.c */ 1274extern Bool RADEONGetDatatypeBpp(int bpp, uint32_t *type); 1275extern Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, 1276 uint32_t *pitch_offset); 1277extern unsigned long long RADEONTexOffsetStart(PixmapPtr pPix); 1278#endif 1279 1280/* radeon_modes.c */ 1281extern void RADEONSetPitch(ScrnInfoPtr pScrn); 1282extern DisplayModePtr RADEONProbeOutputModes(xf86OutputPtr output); 1283 1284/* radeon_output.c */ 1285extern RADEONI2CBusRec atom_setup_i2c_bus(int ddc_line); 1286extern RADEONI2CBusRec legacy_setup_i2c_bus(int ddc_line); 1287extern void RADEONGetPanelInfo(ScrnInfoPtr pScrn); 1288extern void RADEONInitConnector(xf86OutputPtr output); 1289extern void RADEONPrintPortMap(ScrnInfoPtr pScrn); 1290extern void RADEONSetOutputType(ScrnInfoPtr pScrn, 1291 RADEONOutputPrivatePtr radeon_output); 1292extern Bool RADEONSetupConnectors(ScrnInfoPtr pScrn); 1293extern Bool RADEONI2CDoLock(xf86OutputPtr output, I2CBusPtr b, Bool lock_state); 1294 1295extern Bool radeon_dp_mode_fixup(xf86OutputPtr output, DisplayModePtr mode, DisplayModePtr adjusted_mode); 1296 1297/* radeon_tv.c */ 1298extern void RADEONSaveTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1299extern void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, 1300 DisplayModePtr mode, xf86OutputPtr output); 1301extern void RADEONAdjustPLLRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, 1302 DisplayModePtr mode, xf86OutputPtr output); 1303extern void RADEONAdjustCrtc2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, 1304 DisplayModePtr mode, xf86OutputPtr output); 1305extern void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, 1306 DisplayModePtr mode, xf86OutputPtr output); 1307extern void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save, 1308 DisplayModePtr mode, BOOL IsPrimary); 1309extern void RADEONRestoreTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1310extern void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode); 1311 1312/* radeon_video.c */ 1313extern void RADEONInitVideo(ScreenPtr pScreen); 1314extern void RADEONResetVideo(ScrnInfoPtr pScrn); 1315extern Bool radeon_load_bicubic_texture(ScrnInfoPtr pScrn); 1316extern xf86CrtcPtr radeon_pick_best_crtc(ScrnInfoPtr pScrn, 1317 int x1, int x2, int y1, int y2); 1318 1319/* radeon_legacy_memory.c */ 1320extern uint32_t 1321radeon_legacy_allocate_memory(ScrnInfoPtr pScrn, 1322 void **mem_struct, 1323 int size, 1324 int align, 1325 int domain); 1326extern void 1327radeon_legacy_free_memory(ScrnInfoPtr pScrn, 1328 void *mem_struct); 1329 1330#ifdef XF86DRM_MODE 1331extern void radeon_cs_flush_indirect(ScrnInfoPtr pScrn); 1332extern void radeon_ddx_cs_start(ScrnInfoPtr pScrn, 1333 int num, const char *file, 1334 const char *func, int line); 1335void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, int new_fb_size); 1336#endif 1337struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix); 1338void radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_bo *bo); 1339 1340#ifdef XF86DRI 1341# ifdef USE_XAA 1342/* radeon_accelfuncs.c */ 1343extern void RADEONAccelInitCP(ScreenPtr pScreen, XAAInfoRecPtr a); 1344# endif 1345 1346#define RADEONCP_START(pScrn, info) \ 1347do { \ 1348 int _ret = drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_START); \ 1349 if (_ret) { \ 1350 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1351 "%s: CP start %d\n", __FUNCTION__, _ret); \ 1352 } \ 1353 info->cp->CPStarted = TRUE; \ 1354} while (0) 1355 1356#define RADEONCP_RELEASE(pScrn, info) \ 1357do { \ 1358 if (info->cs) { \ 1359 radeon_cs_flush_indirect(pScrn); \ 1360 } else if (info->cp->CPInUse) { \ 1361 RADEON_PURGE_CACHE(); \ 1362 RADEON_WAIT_UNTIL_IDLE(); \ 1363 RADEONCPReleaseIndirect(pScrn); \ 1364 info->cp->CPInUse = FALSE; \ 1365 } \ 1366} while (0) 1367 1368#define RADEONCP_STOP(pScrn, info) \ 1369do { \ 1370 int _ret; \ 1371 if (info->cp->CPStarted) { \ 1372 _ret = RADEONCPStop(pScrn, info); \ 1373 if (_ret) { \ 1374 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1375 "%s: CP stop %d\n", __FUNCTION__, _ret); \ 1376 } \ 1377 info->cp->CPStarted = FALSE; \ 1378 } \ 1379 if (info->ChipFamily < CHIP_FAMILY_R600) \ 1380 RADEONEngineRestore(pScrn); \ 1381 info->cp->CPRuns = FALSE; \ 1382} while (0) 1383 1384#define RADEONCP_RESET(pScrn, info) \ 1385do { \ 1386 int _ret = drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_RESET); \ 1387 if (_ret) { \ 1388 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1389 "%s: CP reset %d\n", __FUNCTION__, _ret); \ 1390 } \ 1391} while (0) 1392 1393#define RADEONCP_REFRESH(pScrn, info) \ 1394do { \ 1395 if (!info->cp->CPInUse && !info->cs) { \ 1396 if (info->cp->needCacheFlush) { \ 1397 RADEON_PURGE_CACHE(); \ 1398 RADEON_PURGE_ZCACHE(); \ 1399 info->cp->needCacheFlush = FALSE; \ 1400 } \ 1401 RADEON_WAIT_UNTIL_IDLE(); \ 1402 info->cp->CPInUse = TRUE; \ 1403 } \ 1404} while (0) 1405 1406 1407#define CP_PACKET0(reg, n) \ 1408 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 1409#define CP_PACKET1(reg0, reg1) \ 1410 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 11) | ((reg0) >> 2)) 1411#define CP_PACKET2() \ 1412 (RADEON_CP_PACKET2) 1413#define CP_PACKET3(pkt, n) \ 1414 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 1415 1416 1417#define RADEON_VERBOSE 0 1418 1419#define RING_LOCALS uint32_t *__head = NULL; int __expected; int __count = 0 1420 1421#define BEGIN_RING(n) do { \ 1422 if (RADEON_VERBOSE) { \ 1423 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ 1424 "BEGIN_RING(%d) in %s\n", (unsigned int)n, __FUNCTION__);\ 1425 } \ 1426 if (info->cs) { radeon_ddx_cs_start(pScrn, n, __FILE__, __func__, __LINE__); } else { \ 1427 if (++info->cp->dma_begin_count != 1) { \ 1428 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1429 "BEGIN_RING without end at %s:%d\n", \ 1430 info->cp->dma_debug_func, info->cp->dma_debug_lineno); \ 1431 info->cp->dma_begin_count = 1; \ 1432 } \ 1433 info->cp->dma_debug_func = __FILE__; \ 1434 info->cp->dma_debug_lineno = __LINE__; \ 1435 if (!info->cp->indirectBuffer) { \ 1436 info->cp->indirectBuffer = RADEONCPGetBuffer(pScrn); \ 1437 info->cp->indirectStart = 0; \ 1438 } else if (info->cp->indirectBuffer->used + (n) * (int)sizeof(uint32_t) > \ 1439 info->cp->indirectBuffer->total) { \ 1440 RADEONCPFlushIndirect(pScrn, 1); \ 1441 } \ 1442 __expected = n; \ 1443 __head = (pointer)((char *)info->cp->indirectBuffer->address + \ 1444 info->cp->indirectBuffer->used); \ 1445 __count = 0; \ 1446 } \ 1447} while (0) 1448 1449#define ADVANCE_RING() do { \ 1450 if (info->cs) radeon_cs_end(info->cs, __FILE__, __func__, __LINE__); else { \ 1451 if (info->cp->dma_begin_count-- != 1) { \ 1452 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1453 "ADVANCE_RING without begin at %s:%d\n", \ 1454 __FILE__, __LINE__); \ 1455 info->cp->dma_begin_count = 0; \ 1456 } \ 1457 if (__count != __expected) { \ 1458 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1459 "ADVANCE_RING count != expected (%d vs %d) at %s:%d\n", \ 1460 __count, __expected, __FILE__, __LINE__); \ 1461 } \ 1462 if (RADEON_VERBOSE) { \ 1463 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ 1464 "ADVANCE_RING() start: %d used: %d count: %d\n", \ 1465 info->cp->indirectStart, \ 1466 info->cp->indirectBuffer->used, \ 1467 __count * (int)sizeof(uint32_t)); \ 1468 } \ 1469 info->cp->indirectBuffer->used += __count * (int)sizeof(uint32_t); \ 1470 } \ 1471 } while (0) 1472 1473#define OUT_RING(x) do { \ 1474 if (RADEON_VERBOSE) { \ 1475 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ 1476 " OUT_RING(0x%08x)\n", (unsigned int)(x)); \ 1477 } \ 1478 if (info->cs) radeon_cs_write_dword(info->cs, (x)); else \ 1479 __head[__count++] = (x); \ 1480} while (0) 1481 1482#define OUT_RING_REG(reg, val) \ 1483do { \ 1484 OUT_RING(CP_PACKET0(reg, 0)); \ 1485 OUT_RING(val); \ 1486} while (0) 1487 1488#define OUT_RING_RELOC(x, read_domains, write_domain) \ 1489 do { \ 1490 int _ret; \ 1491 _ret = radeon_cs_write_reloc(info->cs, x, read_domains, write_domain, 0); \ 1492 if (_ret) ErrorF("reloc emit failure %d\n", _ret); \ 1493 } while(0) 1494 1495 1496#define FLUSH_RING() \ 1497do { \ 1498 if (RADEON_VERBOSE) \ 1499 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ 1500 "FLUSH_RING in %s\n", __FUNCTION__); \ 1501 if (info->cs) \ 1502 radeon_cs_flush_indirect(pScrn); \ 1503 else if (info->cp->indirectBuffer) \ 1504 RADEONCPFlushIndirect(pScrn, 0); \ 1505} while (0) 1506 1507 1508#define RADEON_WAIT_UNTIL_2D_IDLE() \ 1509do { \ 1510 if (info->ChipFamily < CHIP_FAMILY_R600) { \ 1511 BEGIN_RING(2); \ 1512 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \ 1513 OUT_RING((RADEON_WAIT_2D_IDLECLEAN | \ 1514 RADEON_WAIT_HOST_IDLECLEAN)); \ 1515 ADVANCE_RING(); \ 1516 } \ 1517} while (0) 1518 1519#define RADEON_WAIT_UNTIL_3D_IDLE() \ 1520do { \ 1521 if (info->ChipFamily < CHIP_FAMILY_R600) { \ 1522 BEGIN_RING(2); \ 1523 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \ 1524 OUT_RING((RADEON_WAIT_3D_IDLECLEAN | \ 1525 RADEON_WAIT_HOST_IDLECLEAN)); \ 1526 ADVANCE_RING(); \ 1527 } \ 1528} while (0) 1529 1530#define RADEON_WAIT_UNTIL_IDLE() \ 1531do { \ 1532 if (RADEON_VERBOSE) { \ 1533 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ 1534 "WAIT_UNTIL_IDLE() in %s\n", __FUNCTION__); \ 1535 } \ 1536 if (info->ChipFamily < CHIP_FAMILY_R600) { \ 1537 BEGIN_RING(2); \ 1538 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \ 1539 OUT_RING((RADEON_WAIT_2D_IDLECLEAN | \ 1540 RADEON_WAIT_3D_IDLECLEAN | \ 1541 RADEON_WAIT_HOST_IDLECLEAN)); \ 1542 ADVANCE_RING(); \ 1543 } \ 1544} while (0) 1545 1546#define RADEON_PURGE_CACHE() \ 1547do { \ 1548 if (info->ChipFamily < CHIP_FAMILY_R600) { \ 1549 BEGIN_RING(2); \ 1550 if (info->ChipFamily <= CHIP_FAMILY_RV280) { \ 1551 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1552 OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \ 1553 } else { \ 1554 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1555 OUT_RING(R300_RB3D_DC_FLUSH_ALL); \ 1556 } \ 1557 ADVANCE_RING(); \ 1558 } \ 1559} while (0) 1560 1561#define RADEON_PURGE_ZCACHE() \ 1562do { \ 1563 if (info->ChipFamily < CHIP_FAMILY_R600) { \ 1564 BEGIN_RING(2); \ 1565 if (info->ChipFamily <= CHIP_FAMILY_RV280) { \ 1566 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1567 OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL); \ 1568 } else { \ 1569 OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); \ 1570 OUT_RING(R300_ZC_FLUSH_ALL); \ 1571 } \ 1572 ADVANCE_RING(); \ 1573 } \ 1574} while (0) 1575 1576#endif /* XF86DRI */ 1577 1578#if defined(XF86DRI) && defined(USE_EXA) 1579 1580#ifdef XF86DRM_MODE 1581#define CS_FULL(cs) ((cs)->cdw > 15 * 1024) 1582#else 1583#define CS_FULL(cs) FALSE 1584#endif 1585 1586#define RADEON_SWITCH_TO_2D() \ 1587do { \ 1588 uint32_t flush = 0; \ 1589 switch (info->accel_state->engineMode) { \ 1590 case EXA_ENGINEMODE_UNKNOWN: \ 1591 flush = 1; \ 1592 break; \ 1593 case EXA_ENGINEMODE_3D: \ 1594 flush = !info->cs || CS_FULL(info->cs); \ 1595 break; \ 1596 case EXA_ENGINEMODE_2D: \ 1597 flush = info->cs && CS_FULL(info->cs); \ 1598 break; \ 1599 } \ 1600 if (flush) { \ 1601 if (info->cs) \ 1602 radeon_cs_flush_indirect(pScrn); \ 1603 else if (info->directRenderingEnabled) \ 1604 RADEONCPFlushIndirect(pScrn, 1); \ 1605 } \ 1606 info->accel_state->engineMode = EXA_ENGINEMODE_2D; \ 1607} while (0); 1608 1609#define RADEON_SWITCH_TO_3D() \ 1610do { \ 1611 uint32_t flush = 0; \ 1612 switch (info->accel_state->engineMode) { \ 1613 case EXA_ENGINEMODE_UNKNOWN: \ 1614 flush = 1; \ 1615 break; \ 1616 case EXA_ENGINEMODE_2D: \ 1617 flush = !info->cs || CS_FULL(info->cs); \ 1618 break; \ 1619 case EXA_ENGINEMODE_3D: \ 1620 flush = info->cs && CS_FULL(info->cs); \ 1621 break; \ 1622 } \ 1623 if (flush) { \ 1624 if (info->cs) \ 1625 radeon_cs_flush_indirect(pScrn); \ 1626 else if (info->directRenderingEnabled) \ 1627 RADEONCPFlushIndirect(pScrn, 1); \ 1628 } \ 1629 if (!info->accel_state->XInited3D) \ 1630 RADEONInit3DEngine(pScrn); \ 1631 info->accel_state->engineMode = EXA_ENGINEMODE_3D; \ 1632} while (0); 1633#else 1634#define RADEON_SWITCH_TO_2D() 1635#define RADEON_SWITCH_TO_3D() 1636#endif 1637 1638static __inline__ void RADEON_MARK_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn) 1639{ 1640#ifdef USE_EXA 1641 if (info->useEXA) 1642 exaMarkSync(pScrn->pScreen); 1643#endif 1644#ifdef USE_XAA 1645 if (!info->useEXA) 1646 SET_SYNC_FLAG(info->accel_state->accel); 1647#endif 1648} 1649 1650static __inline__ void RADEON_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn) 1651{ 1652#ifdef USE_EXA 1653 if (info->useEXA && pScrn->pScreen) 1654 exaWaitSync(pScrn->pScreen); 1655#endif 1656#ifdef USE_XAA 1657 if (!info->useEXA && info->accel_state->accel) 1658 info->accel_state->accel->Sync(pScrn); 1659#endif 1660} 1661 1662static __inline__ void radeon_init_timeout(struct timeval *endtime, 1663 unsigned int timeout) 1664{ 1665 gettimeofday(endtime, NULL); 1666 endtime->tv_usec += timeout; 1667 endtime->tv_sec += endtime->tv_usec / 1000000; 1668 endtime->tv_usec %= 1000000; 1669} 1670 1671static __inline__ int radeon_timedout(const struct timeval *endtime) 1672{ 1673 struct timeval now; 1674 gettimeofday(&now, NULL); 1675 return now.tv_sec == endtime->tv_sec ? 1676 now.tv_usec > endtime->tv_usec : now.tv_sec > endtime->tv_sec; 1677} 1678 1679enum { 1680 RADEON_CREATE_PIXMAP_TILING_MACRO = 0x10000000, 1681 RADEON_CREATE_PIXMAP_TILING_MICRO = 0x20000000, 1682}; 1683 1684#endif /* _RADEON_H_ */ 1685