radeon.h revision 921a55d8
1/* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining 8 * a copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation on the rights to use, copy, modify, merge, 11 * publish, distribute, sublicense, and/or sell copies of the Software, 12 * and to permit persons to whom the Software is furnished to do so, 13 * subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 */ 28 29/* 30 * Authors: 31 * Kevin E. Martin <martin@xfree86.org> 32 * Rickard E. Faith <faith@valinux.com> 33 * Alan Hourihane <alanh@fairlite.demon.co.uk> 34 * 35 */ 36 37#ifndef _RADEON_H_ 38#define _RADEON_H_ 39 40#include <stdlib.h> /* For abs() */ 41#include <unistd.h> /* For usleep() */ 42#include <sys/time.h> /* For gettimeofday() */ 43 44#include "config.h" 45#include "xf86str.h" 46#include "compiler.h" 47#include "xf86fbman.h" 48 49 /* PCI support */ 50#include "xf86Pci.h" 51 52#ifdef USE_EXA 53#include "exa.h" 54#endif 55#ifdef USE_XAA 56#include "xaa.h" 57#endif 58 59 /* Exa and Cursor Support */ 60#include "vbe.h" 61#include "xf86Cursor.h" 62 63 /* DDC support */ 64#include "xf86DDC.h" 65 66 /* Xv support */ 67#include "xf86xv.h" 68 69#include "radeon_probe.h" 70#include "radeon_tv.h" 71 72 /* DRI support */ 73#ifdef XF86DRI 74#define _XF86DRI_SERVER_ 75#include "dri.h" 76#include "GL/glxint.h" 77#include "xf86drm.h" 78#include "radeon_drm.h" 79 80#ifdef DAMAGE 81#include "damage.h" 82#include "globals.h" 83#endif 84#endif 85 86#include "xf86Crtc.h" 87#include "X11/Xatom.h" 88 89#ifdef XF86DRM_MODE 90#include "radeon_bo.h" 91#include "radeon_cs.h" 92#include "radeon_dri2.h" 93#include "drmmode_display.h" 94#else 95#include "radeon_dummy_bufmgr.h" 96#endif 97 98 /* Render support */ 99#ifdef RENDER 100#include "picturestr.h" 101#endif 102 103#include "simple_list.h" 104#include "atipcirename.h" 105 106#ifndef MAX 107#define MAX(a,b) ((a)>(b)?(a):(b)) 108#endif 109#ifndef MIN 110#define MIN(a,b) ((a)>(b)?(b):(a)) 111#endif 112 113#if HAVE_BYTESWAP_H 114#include <byteswap.h> 115#elif defined(USE_SYS_ENDIAN_H) 116#include <sys/endian.h> 117#else 118#define bswap_16(value) \ 119 ((((value) & 0xff) << 8) | ((value) >> 8)) 120 121#define bswap_32(value) \ 122 (((uint32_t)bswap_16((uint16_t)((value) & 0xffff)) << 16) | \ 123 (uint32_t)bswap_16((uint16_t)((value) >> 16))) 124 125#define bswap_64(value) \ 126 (((uint64_t)bswap_32((uint32_t)((value) & 0xffffffff)) \ 127 << 32) | \ 128 (uint64_t)bswap_32((uint32_t)((value) >> 32))) 129#endif 130 131#if X_BYTE_ORDER == X_BIG_ENDIAN 132#define le32_to_cpu(x) bswap_32(x) 133#define le16_to_cpu(x) bswap_16(x) 134#define cpu_to_le32(x) bswap_32(x) 135#define cpu_to_le16(x) bswap_16(x) 136#else 137#define le32_to_cpu(x) (x) 138#define le16_to_cpu(x) (x) 139#define cpu_to_le32(x) (x) 140#define cpu_to_le16(x) (x) 141#endif 142 143/* Provide substitutes for gcc's __FUNCTION__ on other compilers */ 144#if !defined(__GNUC__) && !defined(__FUNCTION__) 145# define __FUNCTION__ __func__ /* C99 */ 146#endif 147 148#ifndef HAVE_XF86MODEBANDWIDTH 149extern unsigned int xf86ModeBandwidth(DisplayModePtr mode, int depth); 150#define MODE_BANDWIDTH MODE_BAD 151#endif 152 153typedef enum { 154 OPTION_NOACCEL, 155 OPTION_SW_CURSOR, 156 OPTION_DAC_6BIT, 157 OPTION_DAC_8BIT, 158#ifdef XF86DRI 159 OPTION_BUS_TYPE, 160 OPTION_CP_PIO, 161 OPTION_USEC_TIMEOUT, 162 OPTION_AGP_MODE, 163 OPTION_AGP_FW, 164 OPTION_GART_SIZE, 165 OPTION_GART_SIZE_OLD, 166 OPTION_RING_SIZE, 167 OPTION_BUFFER_SIZE, 168 OPTION_DEPTH_MOVE, 169 OPTION_PAGE_FLIP, 170 OPTION_NO_BACKBUFFER, 171 OPTION_XV_DMA, 172 OPTION_FBTEX_PERCENT, 173 OPTION_DEPTH_BITS, 174 OPTION_PCIAPER_SIZE, 175#ifdef USE_EXA 176 OPTION_ACCEL_DFS, 177 OPTION_EXA_PIXMAPS, 178#endif 179#endif 180 OPTION_IGNORE_EDID, 181 OPTION_CUSTOM_EDID, 182 OPTION_DISP_PRIORITY, 183 OPTION_PANEL_SIZE, 184 OPTION_MIN_DOTCLOCK, 185 OPTION_COLOR_TILING, 186#ifdef XvExtension 187 OPTION_VIDEO_KEY, 188 OPTION_RAGE_THEATRE_CRYSTAL, 189 OPTION_RAGE_THEATRE_TUNER_PORT, 190 OPTION_RAGE_THEATRE_COMPOSITE_PORT, 191 OPTION_RAGE_THEATRE_SVIDEO_PORT, 192 OPTION_TUNER_TYPE, 193 OPTION_RAGE_THEATRE_MICROC_PATH, 194 OPTION_RAGE_THEATRE_MICROC_TYPE, 195 OPTION_SCALER_WIDTH, 196#endif 197#ifdef RENDER 198 OPTION_RENDER_ACCEL, 199 OPTION_SUBPIXEL_ORDER, 200#endif 201 OPTION_SHOWCACHE, 202 OPTION_CLOCK_GATING, 203 OPTION_BIOS_HOTKEYS, 204 OPTION_VGA_ACCESS, 205 OPTION_REVERSE_DDC, 206 OPTION_LVDS_PROBE_PLL, 207 OPTION_ACCELMETHOD, 208 OPTION_CONNECTORTABLE, 209 OPTION_DRI, 210 OPTION_DEFAULT_CONNECTOR_TABLE, 211#if defined(__powerpc__) 212 OPTION_MAC_MODEL, 213#endif 214 OPTION_DEFAULT_TMDS_PLL, 215 OPTION_TVDAC_LOAD_DETECT, 216 OPTION_FORCE_TVOUT, 217 OPTION_TVSTD, 218 OPTION_IGNORE_LID_STATUS, 219 OPTION_DEFAULT_TVDAC_ADJ, 220 OPTION_INT10, 221 OPTION_EXA_VSYNC, 222 OPTION_ATOM_TVOUT, 223 OPTION_R4XX_ATOM, 224 OPTION_FORCE_LOW_POWER, 225 OPTION_DYNAMIC_PM, 226 OPTION_NEW_PLL, 227 OPTION_ZAPHOD_HEADS, 228 OPTION_SWAPBUFFERS_WAIT 229} RADEONOpts; 230 231 232#define RADEON_IDLE_RETRY 16 /* Fall out of idle loops after this count */ 233#define RADEON_TIMEOUT 2000000 /* Fall out of wait loops after this count */ 234 235#define RADEON_VSYNC_TIMEOUT 20000 /* Maximum wait for VSYNC (in usecs) */ 236 237/* Buffer are aligned on 4096 byte boundaries */ 238#define RADEON_GPU_PAGE_SIZE 4096 239#define RADEON_BUFFER_ALIGN (RADEON_GPU_PAGE_SIZE - 1) 240#define RADEON_VBIOS_SIZE 0x00010000 241#define RADEON_USE_RMX 0x80000000 /* mode flag for using RMX 242 * Need to comfirm this is not used 243 * for something else. 244 */ 245 246#define xFixedToFloat(f) (((float) (f)) / 65536) 247 248#define RADEON_LOGLEVEL_DEBUG 4 249 250/* for Xv, outputs */ 251#define MAKE_ATOM(a) MakeAtom(a, sizeof(a) - 1, TRUE) 252 253/* Other macros */ 254#define RADEON_ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) 255#define RADEON_ALIGN(x,bytes) (((x) + ((bytes) - 1)) & ~((bytes) - 1)) 256#define RADEONPTR(pScrn) ((RADEONInfoPtr)(pScrn)->driverPrivate) 257 258typedef struct { 259 int revision; 260 uint16_t rr1_offset; 261 uint16_t rr2_offset; 262 uint16_t dyn_clk_offset; 263 uint16_t pll_offset; 264 uint16_t mem_config_offset; 265 uint16_t mem_reset_offset; 266 uint16_t short_mem_offset; 267 uint16_t rr3_offset; 268 uint16_t rr4_offset; 269} RADEONBIOSInitTable; 270 271#define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 272#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 273#define RADEON_PLL_USE_REF_DIV (1 << 2) 274#define RADEON_PLL_LEGACY (1 << 3) 275#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 276#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 277#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 278#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 279#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 280#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 281#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 282#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 283#define RADEON_PLL_USE_POST_DIV (1 << 12) 284 285typedef struct { 286 uint32_t reference_freq; 287 uint32_t reference_div; 288 uint32_t post_div; 289 uint32_t pll_in_min; 290 uint32_t pll_in_max; 291 uint32_t pll_out_min; 292 uint32_t pll_out_max; 293 uint16_t xclk; 294 295 uint32_t min_ref_div; 296 uint32_t max_ref_div; 297 uint32_t min_post_div; 298 uint32_t max_post_div; 299 uint32_t min_feedback_div; 300 uint32_t max_feedback_div; 301 uint32_t min_frac_feedback_div; 302 uint32_t max_frac_feedback_div; 303 uint32_t best_vco; 304} RADEONPLLRec, *RADEONPLLPtr; 305 306typedef struct { 307 int bitsPerPixel; 308 int depth; 309 int displayWidth; 310 int displayHeight; 311 int pixel_code; 312 int pixel_bytes; 313 DisplayModePtr mode; 314} RADEONFBLayout; 315 316typedef enum { 317 CHIP_FAMILY_UNKNOW, 318 CHIP_FAMILY_LEGACY, 319 CHIP_FAMILY_RADEON, 320 CHIP_FAMILY_RV100, 321 CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/ 322 CHIP_FAMILY_RV200, 323 CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */ 324 CHIP_FAMILY_R200, 325 CHIP_FAMILY_RV250, 326 CHIP_FAMILY_RS300, /* RS300/RS350 */ 327 CHIP_FAMILY_RV280, 328 CHIP_FAMILY_R300, 329 CHIP_FAMILY_R350, 330 CHIP_FAMILY_RV350, 331 CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ 332 CHIP_FAMILY_R420, /* R420/R423/M18 */ 333 CHIP_FAMILY_RV410, /* RV410, M26 */ 334 CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400) Intel */ 335 CHIP_FAMILY_RS480, /* xpress 200, 200m (RS410/480/482/485) AMD */ 336 CHIP_FAMILY_RV515, /* rv515 */ 337 CHIP_FAMILY_R520, /* r520 */ 338 CHIP_FAMILY_RV530, /* rv530 */ 339 CHIP_FAMILY_R580, /* r580 */ 340 CHIP_FAMILY_RV560, /* rv560 */ 341 CHIP_FAMILY_RV570, /* rv570 */ 342 CHIP_FAMILY_RS600, 343 CHIP_FAMILY_RS690, 344 CHIP_FAMILY_RS740, 345 CHIP_FAMILY_R600, /* r600 */ 346 CHIP_FAMILY_RV610, 347 CHIP_FAMILY_RV630, 348 CHIP_FAMILY_RV670, 349 CHIP_FAMILY_RV620, 350 CHIP_FAMILY_RV635, 351 CHIP_FAMILY_RS780, 352 CHIP_FAMILY_RS880, 353 CHIP_FAMILY_RV770, /* r700 */ 354 CHIP_FAMILY_RV730, 355 CHIP_FAMILY_RV710, 356 CHIP_FAMILY_RV740, 357 CHIP_FAMILY_CEDAR, /* evergreen */ 358 CHIP_FAMILY_REDWOOD, 359 CHIP_FAMILY_JUNIPER, 360 CHIP_FAMILY_CYPRESS, 361 CHIP_FAMILY_HEMLOCK, 362 CHIP_FAMILY_PALM, 363 CHIP_FAMILY_BARTS, 364 CHIP_FAMILY_TURKS, 365 CHIP_FAMILY_CAICOS, 366 CHIP_FAMILY_LAST 367} RADEONChipFamily; 368 369#define IS_RV100_VARIANT ((info->ChipFamily == CHIP_FAMILY_RV100) || \ 370 (info->ChipFamily == CHIP_FAMILY_RV200) || \ 371 (info->ChipFamily == CHIP_FAMILY_RS100) || \ 372 (info->ChipFamily == CHIP_FAMILY_RS200) || \ 373 (info->ChipFamily == CHIP_FAMILY_RV250) || \ 374 (info->ChipFamily == CHIP_FAMILY_RV280) || \ 375 (info->ChipFamily == CHIP_FAMILY_RS300)) 376 377 378#define IS_R300_VARIANT ((info->ChipFamily == CHIP_FAMILY_R300) || \ 379 (info->ChipFamily == CHIP_FAMILY_RV350) || \ 380 (info->ChipFamily == CHIP_FAMILY_R350) || \ 381 (info->ChipFamily == CHIP_FAMILY_RV380) || \ 382 (info->ChipFamily == CHIP_FAMILY_R420) || \ 383 (info->ChipFamily == CHIP_FAMILY_RV410) || \ 384 (info->ChipFamily == CHIP_FAMILY_RS400) || \ 385 (info->ChipFamily == CHIP_FAMILY_RS480)) 386 387#define IS_AVIVO_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV515)) 388 389#define IS_DCE3_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV620)) 390 391#define IS_DCE32_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV730)) 392 393#define IS_DCE4_VARIANT ((info->ChipFamily >= CHIP_FAMILY_CEDAR)) 394 395#define IS_DCE41_VARIANT ((info->ChipFamily >= CHIP_FAMILY_PALM)) 396 397#define IS_DCE5_VARIANT ((info->ChipFamily >= CHIP_FAMILY_BARTS)) 398 399#define IS_EVERGREEN_3D (info->ChipFamily >= CHIP_FAMILY_CEDAR) 400 401#define IS_R600_3D (info->ChipFamily >= CHIP_FAMILY_R600) 402 403#define IS_R500_3D ((info->ChipFamily == CHIP_FAMILY_RV515) || \ 404 (info->ChipFamily == CHIP_FAMILY_R520) || \ 405 (info->ChipFamily == CHIP_FAMILY_RV530) || \ 406 (info->ChipFamily == CHIP_FAMILY_R580) || \ 407 (info->ChipFamily == CHIP_FAMILY_RV560) || \ 408 (info->ChipFamily == CHIP_FAMILY_RV570)) 409 410#define IS_R400_3D ((info->ChipFamily == CHIP_FAMILY_R420) || \ 411 (info->ChipFamily == CHIP_FAMILY_RV410) || \ 412 (info->ChipFamily == CHIP_FAMILY_RS690) || \ 413 (info->ChipFamily == CHIP_FAMILY_RS600) || \ 414 (info->ChipFamily == CHIP_FAMILY_RS740)) 415 416#define IS_R300_3D ((info->ChipFamily == CHIP_FAMILY_R300) || \ 417 (info->ChipFamily == CHIP_FAMILY_RV350) || \ 418 (info->ChipFamily == CHIP_FAMILY_R350) || \ 419 (info->ChipFamily == CHIP_FAMILY_RV380) || \ 420 (info->ChipFamily == CHIP_FAMILY_R420) || \ 421 (info->ChipFamily == CHIP_FAMILY_RV410) || \ 422 (info->ChipFamily == CHIP_FAMILY_RS690) || \ 423 (info->ChipFamily == CHIP_FAMILY_RS600) || \ 424 (info->ChipFamily == CHIP_FAMILY_RS740) || \ 425 (info->ChipFamily == CHIP_FAMILY_RS400) || \ 426 (info->ChipFamily == CHIP_FAMILY_RS480)) 427 428#define IS_R200_3D ((info->ChipFamily == CHIP_FAMILY_RV250) || \ 429 (info->ChipFamily == CHIP_FAMILY_RV280) || \ 430 (info->ChipFamily == CHIP_FAMILY_RS300) || \ 431 (info->ChipFamily == CHIP_FAMILY_R200)) 432 433/* 434 * Errata workarounds 435 */ 436typedef enum { 437 CHIP_ERRATA_R300_CG = 0x00000001, 438 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 439 CHIP_ERRATA_PLL_DELAY = 0x00000004 440} RADEONErrata; 441 442typedef enum { 443 RADEON_DVOCHIP_NONE, 444 RADEON_SIL_164, 445 RADEON_SIL_1178 446} RADEONExtTMDSChip; 447 448#if defined(__powerpc__) 449typedef enum { 450 RADEON_MAC_NONE, 451 RADEON_MAC_IBOOK, 452 RADEON_MAC_POWERBOOK_EXTERNAL, 453 RADEON_MAC_POWERBOOK_INTERNAL, 454 RADEON_MAC_POWERBOOK_VGA, 455 RADEON_MAC_MINI_EXTERNAL, 456 RADEON_MAC_MINI_INTERNAL, 457 RADEON_MAC_IMAC_G5_ISIGHT, 458 RADEON_MAC_EMAC 459} RADEONMacModel; 460#endif 461 462typedef enum { 463 CARD_PCI, 464 CARD_AGP, 465 CARD_PCIE 466} RADEONCardType; 467 468typedef enum { 469 POWER_DEFAULT, 470 POWER_LOW, 471 POWER_HIGH 472} RADEONPMType; 473 474typedef struct { 475 RADEONPMType type; 476 uint32_t sclk; 477 uint32_t mclk; 478 uint32_t pcie_lanes; 479 uint32_t flags; 480} RADEONPowerMode; 481 482typedef struct { 483 /* power modes */ 484 int num_modes; 485 int current_mode; 486 RADEONPowerMode mode[3]; 487 488 Bool clock_gating_enabled; 489 Bool dynamic_mode_enabled; 490 Bool force_low_power_enabled; 491} RADEONPowerManagement; 492 493typedef struct _atomBiosHandle *atomBiosHandlePtr; 494 495struct radeon_exa_pixmap_priv { 496 struct radeon_bo *bo; 497 int flags; 498 Bool bo_mapped; 499}; 500 501typedef struct { 502 uint32_t pci_device_id; 503 RADEONChipFamily chip_family; 504 int mobility; 505 int igp; 506 int nocrtc2; 507 int nointtvout; 508 int singledac; 509} RADEONCardInfo; 510 511#define RADEON_2D_EXA_COPY 1 512#define RADEON_2D_EXA_SOLID 2 513 514struct radeon_2d_state { 515 int op; // 516 uint32_t dst_pitch_offset; 517 uint32_t src_pitch_offset; 518 uint32_t dp_gui_master_cntl; 519 uint32_t dp_cntl; 520 uint32_t dp_write_mask; 521 uint32_t dp_brush_frgd_clr; 522 uint32_t dp_brush_bkgd_clr; 523 uint32_t dp_src_frgd_clr; 524 uint32_t dp_src_bkgd_clr; 525 uint32_t default_sc_bottom_right; 526 struct radeon_bo *dst_bo; 527 struct radeon_bo *src_bo; 528}; 529 530#ifdef XF86DRI 531struct radeon_cp { 532 Bool CPRuns; /* CP is running */ 533 Bool CPInUse; /* CP has been used by X server */ 534 Bool CPStarted; /* CP has started */ 535 int CPMode; /* CP mode that server/clients use */ 536 int CPFifoSize; /* Size of the CP command FIFO */ 537 int CPusecTimeout; /* CP timeout in usecs */ 538 Bool needCacheFlush; 539 540 /* CP accleration */ 541 drmBufPtr indirectBuffer; 542 int indirectStart; 543 544 /* Debugging info for BEGIN_RING/ADVANCE_RING pairs. */ 545 int dma_begin_count; 546 char *dma_debug_func; 547 int dma_debug_lineno; 548 549 }; 550 551typedef struct { 552 /* Nothing here yet */ 553 int dummy; 554} RADEONConfigPrivRec, *RADEONConfigPrivPtr; 555 556typedef struct { 557 /* Nothing here yet */ 558 int dummy; 559} RADEONDRIContextRec, *RADEONDRIContextPtr; 560 561struct radeon_dri { 562 Bool noBackBuffer; 563 564 Bool newMemoryMap; 565 drmVersionPtr pLibDRMVersion; 566 drmVersionPtr pKernelDRMVersion; 567 DRIInfoPtr pDRIInfo; 568 int drmFD; 569 int numVisualConfigs; 570 __GLXvisualConfig *pVisualConfigs; 571 RADEONConfigPrivPtr pVisualConfigsPriv; 572 Bool (*DRICloseScreen)(int, ScreenPtr); 573 574 drm_handle_t fbHandle; 575 576 drmSize registerSize; 577 drm_handle_t registerHandle; 578 579 drmSize pciSize; 580 drm_handle_t pciMemHandle; 581 unsigned char *PCI; /* Map */ 582 583 Bool depthMoves; /* Enable depth moves -- slow! */ 584 Bool allowPageFlip; /* Enable 3d page flipping */ 585#ifdef DAMAGE 586 DamagePtr pDamage; 587 RegionRec driRegion; 588#endif 589 Bool have3DWindows; /* Are there any 3d clients? */ 590 591 int pciAperSize; 592 drmSize gartSize; 593 drm_handle_t agpMemHandle; /* Handle from drmAgpAlloc */ 594 unsigned long gartOffset; 595 unsigned char *AGP; /* Map */ 596 int agpMode; 597 598 uint32_t pciCommand; 599 600 /* CP ring buffer data */ 601 unsigned long ringStart; /* Offset into GART space */ 602 drm_handle_t ringHandle; /* Handle from drmAddMap */ 603 drmSize ringMapSize; /* Size of map */ 604 int ringSize; /* Size of ring (in MB) */ 605 drmAddress ring; /* Map */ 606 int ringSizeLog2QW; 607 608 unsigned long ringReadOffset; /* Offset into GART space */ 609 drm_handle_t ringReadPtrHandle; /* Handle from drmAddMap */ 610 drmSize ringReadMapSize; /* Size of map */ 611 drmAddress ringReadPtr; /* Map */ 612 613 /* CP vertex/indirect buffer data */ 614 unsigned long bufStart; /* Offset into GART space */ 615 drm_handle_t bufHandle; /* Handle from drmAddMap */ 616 drmSize bufMapSize; /* Size of map */ 617 int bufSize; /* Size of buffers (in MB) */ 618 drmAddress buf; /* Map */ 619 int bufNumBufs; /* Number of buffers */ 620 drmBufMapPtr buffers; /* Buffer map */ 621 622 /* CP GART Texture data */ 623 unsigned long gartTexStart; /* Offset into GART space */ 624 drm_handle_t gartTexHandle; /* Handle from drmAddMap */ 625 drmSize gartTexMapSize; /* Size of map */ 626 int gartTexSize; /* Size of GART tex space (in MB) */ 627 drmAddress gartTex; /* Map */ 628 int log2GARTTexGran; 629 630 /* DRI screen private data */ 631 int fbX; 632 int fbY; 633 int backX; 634 int backY; 635 int depthX; 636 int depthY; 637 638 int frontOffset; 639 int frontPitch; 640 int backOffset; 641 int backPitch; 642 int depthOffset; 643 int depthPitch; 644 int depthBits; 645 int textureOffset; 646 int textureSize; 647 int log2TexGran; 648 649 int pciGartSize; 650 uint32_t pciGartOffset; 651 void *pciGartBackup; 652 653 int irq; 654 655#ifdef USE_XAA 656 uint32_t frontPitchOffset; 657 uint32_t backPitchOffset; 658 uint32_t depthPitchOffset; 659 660 /* offscreen memory management */ 661 int backLines; 662 FBAreaPtr backArea; 663 int depthTexLines; 664 FBAreaPtr depthTexArea; 665#endif 666 667}; 668#endif 669 670#define DMA_BO_FREE_TIME 1000 671 672struct radeon_dma_bo { 673 struct radeon_dma_bo *next, *prev; 674 struct radeon_bo *bo; 675 int expire_counter; 676}; 677 678struct r600_accel_object { 679 uint32_t pitch; 680 uint32_t width; 681 uint32_t height; 682 uint32_t offset; 683 int bpp; 684 uint32_t domain; 685 struct radeon_bo *bo; 686}; 687 688struct radeon_vbo_object { 689 int vb_offset; 690 uint64_t vb_mc_addr; 691 int vb_total; 692 void *vb_ptr; 693 uint32_t vb_size; 694 uint32_t vb_op_vert_size; 695 int32_t vb_start_op; 696 struct radeon_bo *vb_bo; 697 unsigned verts_per_op; 698}; 699 700struct radeon_accel_state { 701 /* common accel data */ 702 int fifo_slots; /* Free slots in the FIFO (64 max) */ 703 /* Computed values for Radeon */ 704 uint32_t dp_gui_master_cntl; 705 uint32_t dp_gui_master_cntl_clip; 706 uint32_t trans_color; 707 /* Saved values for ScreenToScreenCopy */ 708 int xdir; 709 int ydir; 710 uint32_t dst_pitch_offset; 711 712 /* render accel */ 713 unsigned short texW[2]; 714 unsigned short texH[2]; 715 Bool XInited3D; /* X itself has the 3D context */ 716 int num_gb_pipes; 717 Bool has_tcl; 718 719#ifdef USE_EXA 720 /* EXA */ 721 ExaDriverPtr exa; 722 int exaSyncMarker; 723 int exaMarkerSynced; 724 int engineMode; 725#define EXA_ENGINEMODE_UNKNOWN 0 726#define EXA_ENGINEMODE_2D 1 727#define EXA_ENGINEMODE_3D 2 728 729 int composite_op; 730 PicturePtr dst_pic; 731 PicturePtr msk_pic; 732 PicturePtr src_pic; 733 PixmapPtr dst_pix; 734 PixmapPtr msk_pix; 735 PixmapPtr src_pix; 736 Bool is_transform[2]; 737 PictTransform *transform[2]; 738 /* Whether we are tiling horizontally and vertically */ 739 Bool need_src_tile_x; 740 Bool need_src_tile_y; 741 /* Size of tiles ... set to 65536x65536 if not tiling in that direction */ 742 Bool src_tile_width; 743 Bool src_tile_height; 744 uint32_t *draw_header; 745 unsigned vtx_count; 746 unsigned num_vtx; 747 Bool vsync; 748 749 drmBufPtr ib; 750 751 struct radeon_vbo_object vbo; 752 struct radeon_vbo_object cbuf; 753 754 /* where to discard IB from if we cancel operation */ 755 uint32_t ib_reset_op; 756#ifdef XF86DRM_MODE 757 struct radeon_dma_bo bo_free; 758 struct radeon_dma_bo bo_wait; 759 struct radeon_dma_bo bo_reserved; 760 Bool use_vbos; 761#endif 762 void (*finish_op)(ScrnInfoPtr, int); 763 // shader storage 764 ExaOffscreenArea *shaders; 765 struct radeon_bo *shaders_bo; 766 uint32_t solid_vs_offset; 767 uint32_t solid_ps_offset; 768 uint32_t copy_vs_offset; 769 uint32_t copy_ps_offset; 770 uint32_t comp_vs_offset; 771 uint32_t comp_ps_offset; 772 uint32_t xv_vs_offset; 773 uint32_t xv_ps_offset; 774 // shader consts 775 uint32_t solid_vs_const_offset; 776 uint32_t solid_ps_const_offset; 777 uint32_t copy_vs_const_offset; 778 uint32_t copy_ps_const_offset; 779 uint32_t comp_vs_const_offset; 780 uint32_t comp_ps_const_offset; 781 uint32_t comp_mask_ps_const_offset; 782 uint32_t xv_vs_const_offset; 783 uint32_t xv_ps_const_offset; 784 785 //size/addr stuff 786 struct r600_accel_object src_obj[2]; 787 struct r600_accel_object dst_obj; 788 uint32_t src_size[2]; 789 uint32_t dst_size; 790 791 uint32_t vs_size; 792 uint64_t vs_mc_addr; 793 uint32_t ps_size; 794 uint64_t ps_mc_addr; 795 796 // UTS/DFS 797 drmBufPtr scratch; 798 799 // copy 800 ExaOffscreenArea *copy_area; 801 struct radeon_bo *copy_area_bo; 802 Bool same_surface; 803 int rop; 804 uint32_t planemask; 805 806 // composite 807 Bool component_alpha; 808 Bool src_alpha; 809 // vline 810 xf86CrtcPtr vline_crtc; 811 int vline_y1; 812 int vline_y2; 813#endif 814 815#ifdef USE_XAA 816 /* XAA */ 817 XAAInfoRecPtr accel; 818 /* ScanlineScreenToScreenColorExpand support */ 819 unsigned char *scratch_buffer[1]; 820 unsigned char *scratch_save; 821 int scanline_x; 822 int scanline_y; 823 int scanline_w; 824 int scanline_h; 825 int scanline_h_w; 826 int scanline_words; 827 int scanline_direct; 828 int scanline_bpp; /* Only used for ImageWrite */ 829 int scanline_fg; 830 int scanline_bg; 831 int scanline_hpass; 832 int scanline_x1clip; 833 int scanline_x2clip; 834 /* Saved values for DashedTwoPointLine */ 835 int dashLen; 836 uint32_t dashPattern; 837 int dash_fg; 838 int dash_bg; 839 840 FBLinearPtr RenderTex; 841 void (*RenderCallback)(ScrnInfoPtr); 842 Time RenderTimeout; 843 /* 844 * XAAForceTransBlit is used to change the behavior of the XAA 845 * SetupForScreenToScreenCopy function, to make it DGA-friendly. 846 */ 847 Bool XAAForceTransBlit; 848#endif 849 850}; 851 852typedef struct { 853 EntityInfoPtr pEnt; 854 pciVideoPtr PciInfo; 855 PCITAG PciTag; 856 int Chipset; 857 RADEONChipFamily ChipFamily; 858 RADEONErrata ChipErrata; 859 860 unsigned long long LinearAddr; /* Frame buffer physical address */ 861 unsigned long long MMIOAddr; /* MMIO region physical address */ 862 unsigned long long BIOSAddr; /* BIOS physical address */ 863 uint64_t fbLocation; 864 uint32_t gartLocation; 865 uint32_t mc_fb_location; 866 uint32_t mc_agp_location; 867 uint32_t mc_agp_location_hi; 868 869 void *MMIO; /* Map of MMIO region */ 870 void *FB; /* Map of frame buffer */ 871 uint8_t *VBIOS; /* Video BIOS pointer */ 872 873 Bool IsAtomBios; /* New BIOS used in R420 etc. */ 874 int ROMHeaderStart; /* Start of the ROM Info Table */ 875 int MasterDataStart; /* Offset for Master Data Table for ATOM BIOS */ 876 877 uint32_t MemCntl; 878 uint32_t BusCntl; 879 unsigned long MMIOSize; /* MMIO region physical address */ 880 unsigned long FbMapSize; /* Size of frame buffer, in bytes */ 881 unsigned long FbSecureSize; /* Size of secured fb area at end of 882 framebuffer */ 883 884 Bool IsMobility; /* Mobile chips for laptops */ 885 Bool IsIGP; /* IGP chips */ 886 Bool HasSingleDAC; /* only TVDAC on chip */ 887 Bool ddc_mode; /* Validate mode by matching exactly 888 * the modes supported in DDC data 889 */ 890 Bool R300CGWorkaround; 891 892 /* EDID or BIOS values for FPs */ 893 int RefDivider; 894 int FeedbackDivider; 895 int PostDivider; 896 Bool UseBiosDividers; 897 /* EDID data using DDC interface */ 898 Bool ddc_bios; 899 Bool ddc1; 900 Bool ddc2; 901 902 RADEONPLLRec pll; 903 int default_dispclk; 904 int dp_extclk; 905 906 int RamWidth; 907 float sclk; /* in MHz */ 908 float mclk; /* in MHz */ 909 Bool IsDDR; 910 int DispPriority; 911 912 RADEONSavePtr SavedReg; /* Original (text) mode */ 913 RADEONSavePtr ModeReg; /* Current mode */ 914 Bool (*CloseScreen)(int, ScreenPtr); 915 916 void (*BlockHandler)(int, pointer, pointer, pointer); 917 918 Bool PaletteSavedOnVT; /* Palette saved on last VT switch */ 919 920 xf86CursorInfoPtr cursor; 921#ifdef ARGB_CURSOR 922 Bool cursor_argb; 923#endif 924 int cursor_fg; 925 int cursor_bg; 926 927 int pix24bpp; /* Depth of pixmap for 24bpp fb */ 928 Bool dac6bits; /* Use 6 bit DAC? */ 929 930 RADEONFBLayout CurrentLayout; 931 932#ifdef XF86DRI 933 Bool directRenderingEnabled; 934 Bool directRenderingInited; 935 RADEONCardType cardType; /* Current card is a PCI card */ 936 struct radeon_cp *cp; 937 struct radeon_dri *dri; 938#ifdef XF86DRM_MODE 939 struct radeon_dri2 dri2; 940#endif 941#ifdef USE_EXA 942 Bool accelDFS; 943#endif 944 Bool DMAForXv; 945#endif /* XF86DRI */ 946 947 /* accel */ 948 Bool RenderAccel; /* Render */ 949 Bool allowColorTiling; 950 Bool tilingEnabled; /* mirror of sarea->tiling_enabled */ 951 struct radeon_accel_state *accel_state; 952 Bool accelOn; 953 Bool useEXA; 954#ifdef USE_EXA 955 Bool exa_pixmaps; 956 Bool exa_force_create; 957 XF86ModReqInfo exaReq; 958#endif 959#ifdef USE_XAA 960 XF86ModReqInfo xaaReq; 961#endif 962 963 /* XVideo */ 964 XF86VideoAdaptorPtr adaptor; 965 void (*VideoTimerCallback)(ScrnInfoPtr, Time); 966 int videoKey; 967 int RageTheatreCrystal; 968 int RageTheatreTunerPort; 969 int RageTheatreCompositePort; 970 int RageTheatreSVideoPort; 971 int tunerType; 972 char* RageTheatreMicrocPath; 973 char* RageTheatreMicrocType; 974 Bool MM_TABLE_valid; 975 struct { 976 uint8_t table_revision; 977 uint8_t table_size; 978 uint8_t tuner_type; 979 uint8_t audio_chip; 980 uint8_t product_id; 981 uint8_t tuner_voltage_teletext_fm; 982 uint8_t i2s_config; /* configuration of the sound chip */ 983 uint8_t video_decoder_type; 984 uint8_t video_decoder_host_config; 985 uint8_t input[5]; 986 } MM_TABLE; 987 uint16_t video_decoder_type; 988 int overlay_scaler_buffer_width; 989 int ecp_div; 990 unsigned int xv_max_width; 991 unsigned int xv_max_height; 992 993 /* general */ 994 OptionInfoPtr Options; 995 996 DisplayModePtr currentMode, savedCurrentMode; 997 998 /* special handlings for DELL triple-head server */ 999 Bool IsDellServer; 1000 1001 Bool VGAAccess; 1002 1003 int MaxSurfaceWidth; 1004 int MaxLines; 1005 1006 Bool want_vblank_interrupts; 1007 RADEONBIOSConnector BiosConnector[RADEON_MAX_BIOS_CONNECTOR]; 1008 radeon_encoder_ptr encoders[RADEON_MAX_BIOS_CONNECTOR]; 1009 RADEONBIOSInitTable BiosTable; 1010 1011 /* save crtc state for console restore */ 1012 Bool crtc_on; 1013 Bool crtc2_on; 1014 1015 Bool InternalTVOut; 1016 1017#if defined(__powerpc__) 1018 RADEONMacModel MacModel; 1019#endif 1020 RADEONExtTMDSChip ext_tmds_chip; 1021 1022 atomBiosHandlePtr atomBIOS; 1023 unsigned long FbFreeStart, FbFreeSize; 1024 unsigned char* BIOSCopy; 1025 1026 CreateScreenResourcesProcPtr CreateScreenResources; 1027 1028 /* if no devices are connected at server startup */ 1029 Bool first_load_no_devices; 1030 1031 Bool IsSecondary; 1032 Bool IsPrimary; 1033 1034 Bool r600_shadow_fb; 1035 void *fb_shadow; 1036 1037 /* some server chips have a hardcoded edid in the bios so that they work with KVMs */ 1038 Bool get_hardcoded_edid_from_bios; 1039 1040 int virtualX; 1041 int virtualY; 1042 1043 Bool r4xx_atom; 1044 1045 /* pm */ 1046 RADEONPowerManagement pm; 1047 1048 /* igp info */ 1049 float igp_sideport_mclk; 1050 float igp_system_mclk; 1051 float igp_ht_link_clk; 1052 float igp_ht_link_width; 1053 1054 int can_resize; 1055 void (*reemit_current2d)(ScrnInfoPtr pScrn, int op); // emit the current 2D state into the IB 1056 struct radeon_2d_state state_2d; 1057 Bool kms_enabled; 1058 struct radeon_bo *front_bo; 1059#ifdef XF86DRM_MODE 1060 struct radeon_bo_manager *bufmgr; 1061 struct radeon_cs_manager *csm; 1062 struct radeon_cs *cs; 1063 1064 struct radeon_bo *cursor_bo[6]; 1065 uint64_t vram_size; 1066 uint64_t gart_size; 1067 drmmode_rec drmmode; 1068 /* r6xx+ tile config */ 1069 uint32_t tile_config; 1070 int group_bytes; 1071 int num_channels; 1072 int num_banks; 1073 int r7xx_bank_op; 1074#else 1075 /* fake bool */ 1076 Bool cs; 1077#endif 1078 1079 /* Xv bicubic filtering */ 1080 struct radeon_bo *bicubic_bo; 1081 void *bicubic_memory; 1082 int bicubic_offset; 1083 /* kms pageflipping */ 1084 Bool allowPageFlip; 1085 1086 /* Perform vsync'ed SwapBuffers? */ 1087 Bool swapBuffersWait; 1088} RADEONInfoRec, *RADEONInfoPtr; 1089 1090#define RADEONWaitForFifo(pScrn, entries) \ 1091do { \ 1092 if (info->accel_state->fifo_slots < entries) \ 1093 RADEONWaitForFifoFunction(pScrn, entries); \ 1094 info->accel_state->fifo_slots -= entries; \ 1095} while (0) 1096 1097/* legacy_crtc.c */ 1098extern void legacy_crtc_dpms(xf86CrtcPtr crtc, int mode); 1099extern void legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, 1100 DisplayModePtr adjusted_mode, int x, int y); 1101extern void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, 1102 RADEONSavePtr restore); 1103extern void RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn, 1104 RADEONSavePtr restore); 1105extern void RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, 1106 RADEONSavePtr restore); 1107extern void RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, 1108 RADEONSavePtr restore); 1109extern void RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, 1110 RADEONSavePtr restore); 1111extern void RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1112extern void RADEONSaveCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1113extern void RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save); 1114extern void RADEONSavePLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1115extern void RADEONSavePLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save); 1116 1117/* legacy_output.c */ 1118extern RADEONMonitorType legacy_dac_detect(xf86OutputPtr output); 1119extern void legacy_output_dpms(xf86OutputPtr output, int mode); 1120extern void legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, 1121 DisplayModePtr adjusted_mode); 1122extern I2CDevPtr RADEONDVODeviceInit(I2CBusPtr b, I2CSlaveAddr addr); 1123extern Bool RADEONDVOReadByte(I2CDevPtr dvo, int addr, uint8_t *ch); 1124extern Bool RADEONDVOWriteByte(I2CDevPtr dvo, int addr, uint8_t ch); 1125extern void RADEONRestoreDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1126extern void RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1127extern void RADEONRestoreFP2Registers(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1128extern void RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1129extern void RADEONRestoreRMXRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1130extern void RADEONSaveDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1131extern void RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1132 1133extern void RADEONGetTVDacAdjInfo(ScrnInfoPtr pScrn, radeon_tvdac_ptr tvdac); 1134extern void RADEONGetTMDSInfoFromTable(ScrnInfoPtr pScrn, radeon_tmds_ptr tmds); 1135extern void RADEONGetTMDSInfo(ScrnInfoPtr pScrn, radeon_tmds_ptr tmds); 1136extern void RADEONGetExtTMDSInfo(ScrnInfoPtr pScrn, radeon_dvo_ptr dvo); 1137extern void RADEONGetLVDSInfo(ScrnInfoPtr pScrn, radeon_lvds_ptr lvds); 1138 1139/* radeon_accel.c */ 1140extern Bool RADEONAccelInit(ScreenPtr pScreen); 1141extern void RADEONEngineFlush(ScrnInfoPtr pScrn); 1142extern void RADEONEngineInit(ScrnInfoPtr pScrn); 1143extern void RADEONEngineReset(ScrnInfoPtr pScrn); 1144extern void RADEONEngineRestore(ScrnInfoPtr pScrn); 1145extern uint8_t *RADEONHostDataBlit(ScrnInfoPtr pScrn, unsigned int cpp, 1146 unsigned int w, uint32_t dstPitchOff, 1147 uint32_t *bufPitch, int x, int *y, 1148 unsigned int *h, unsigned int *hpass); 1149extern void RADEONHostDataBlitCopyPass(ScrnInfoPtr pScrn, 1150 unsigned int bpp, 1151 uint8_t *dst, uint8_t *src, 1152 unsigned int hpass, 1153 unsigned int dstPitch, 1154 unsigned int srcPitch); 1155extern void RADEONCopySwap(uint8_t *dst, uint8_t *src, unsigned int size, int swap); 1156extern void RADEONHostDataParams(ScrnInfoPtr pScrn, uint8_t *dst, 1157 uint32_t pitch, int cpp, 1158 uint32_t *dstPitchOffset, int *x, int *y); 1159extern void RADEONInit3DEngine(ScrnInfoPtr pScrn); 1160extern void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries); 1161#ifdef XF86DRI 1162extern drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn); 1163extern void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard); 1164extern void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn); 1165extern int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info); 1166# ifdef USE_XAA 1167extern Bool RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen); 1168# endif 1169uint32_t radeonGetPixmapOffset(PixmapPtr pPix); 1170#endif 1171extern int radeon_cs_space_remaining(ScrnInfoPtr pScrn); 1172 1173#ifdef USE_XAA 1174/* radeon_accelfuncs.c */ 1175extern void RADEONAccelInitMMIO(ScreenPtr pScreen, XAAInfoRecPtr a); 1176extern Bool RADEONSetupMemXAA(int scrnIndex, ScreenPtr pScreen); 1177#endif 1178 1179/* radeon_bios.c */ 1180extern Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10); 1181extern Bool RADEONGetClockInfoFromBIOS(ScrnInfoPtr pScrn); 1182extern Bool RADEONGetConnectorInfoFromBIOS(ScrnInfoPtr pScrn); 1183extern Bool RADEONGetDAC2InfoFromBIOS(ScrnInfoPtr pScrn, radeon_tvdac_ptr tvdac); 1184extern Bool RADEONGetExtTMDSInfoFromBIOS (ScrnInfoPtr pScrn, radeon_dvo_ptr dvo); 1185extern xf86MonPtr RADEONGetHardCodedEDIDFromBIOS(xf86OutputPtr output); 1186extern Bool RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn); 1187extern Bool RADEONGetLVDSInfoFromBIOS(ScrnInfoPtr pScrn, radeon_lvds_ptr lvds); 1188extern Bool RADEONGetTMDSInfoFromBIOS(ScrnInfoPtr pScrn, radeon_tmds_ptr tmds); 1189extern Bool RADEONGetTVInfoFromBIOS(xf86OutputPtr output); 1190extern Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output); 1191extern Bool RADEONPostCardFromBIOSTables(ScrnInfoPtr pScrn); 1192extern Bool radeon_card_posted(ScrnInfoPtr pScrn); 1193 1194/* radeon_commonfuncs.c */ 1195#ifdef XF86DRI 1196extern void RADEONWaitForIdleCP(ScrnInfoPtr pScrn); 1197extern void RADEONWaitForVLineCP(ScrnInfoPtr pScrn, PixmapPtr pPix, 1198 xf86CrtcPtr crtc, int start, int stop); 1199#endif 1200extern void RADEONWaitForIdleMMIO(ScrnInfoPtr pScrn); 1201extern void RADEONWaitForVLineMMIO(ScrnInfoPtr pScrn, PixmapPtr pPix, 1202 xf86CrtcPtr crtc, int start, int stop); 1203 1204/* radeon_crtc.c */ 1205extern void radeon_crtc_dpms(xf86CrtcPtr crtc, int mode); 1206extern void radeon_crtc_load_lut(xf86CrtcPtr crtc); 1207extern void radeon_crtc_modeset_ioctl(xf86CrtcPtr crtc, Bool post); 1208extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask); 1209extern void RADEONBlank(ScrnInfoPtr pScrn); 1210extern void RADEONComputePLL(xf86CrtcPtr crtc, 1211 RADEONPLLPtr pll, unsigned long freq, 1212 uint32_t *chosen_dot_clock_freq, 1213 uint32_t *chosen_feedback_div, 1214 uint32_t *chosen_frac_feedback_div, 1215 uint32_t *chosen_reference_div, 1216 uint32_t *chosen_post_div, int flags); 1217extern DisplayModePtr RADEONCrtcFindClosestMode(xf86CrtcPtr crtc, 1218 DisplayModePtr pMode); 1219extern void RADEONUnblank(ScrnInfoPtr pScrn); 1220extern Bool RADEONSetTiling(ScrnInfoPtr pScrn); 1221extern void RADEONInitDispBandwidth(ScrnInfoPtr pScrn); 1222 1223/* radeon_cursor.c */ 1224extern Bool RADEONCursorInit(ScreenPtr pScreen); 1225extern void radeon_crtc_hide_cursor(xf86CrtcPtr crtc); 1226extern void radeon_crtc_load_cursor_argb(xf86CrtcPtr crtc, CARD32 *image); 1227extern void radeon_crtc_set_cursor_colors(xf86CrtcPtr crtc, int bg, int fg); 1228extern void radeon_crtc_set_cursor_position(xf86CrtcPtr crtc, int x, int y); 1229extern void radeon_crtc_show_cursor(xf86CrtcPtr crtc); 1230 1231#ifdef XF86DRI 1232/* radeon_dri.c */ 1233extern void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen); 1234extern void RADEONDRICloseScreen(ScreenPtr pScreen); 1235extern Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen); 1236extern int RADEONDRIGetPciAperTableSize(ScrnInfoPtr pScrn); 1237extern Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn); 1238extern void RADEONDRIResume(ScreenPtr pScreen); 1239extern Bool RADEONDRIScreenInit(ScreenPtr pScreen); 1240extern int RADEONDRISetParam(ScrnInfoPtr pScrn, 1241 unsigned int param, int64_t value); 1242extern Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on); 1243extern void RADEONDRIStop(ScreenPtr pScreen); 1244#endif 1245 1246/* radeon_driver.c */ 1247extern void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool clone); 1248extern void RADEONChangeSurfaces(ScrnInfoPtr pScrn); 1249extern RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn); 1250extern int RADEONMinBits(int val); 1251extern unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr); 1252extern unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr); 1253extern unsigned RADEONINPCIE(ScrnInfoPtr pScrn, int addr); 1254extern unsigned R600INPCIE_PORT(ScrnInfoPtr pScrn, int addr); 1255extern void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, uint32_t data); 1256extern void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, uint32_t data); 1257extern void RADEONOUTPCIE(ScrnInfoPtr pScrn, int addr, uint32_t data); 1258extern void R600OUTPCIE_PORT(ScrnInfoPtr pScrn, int addr, uint32_t data); 1259extern void RADEONPllErrataAfterData(RADEONInfoPtr info); 1260extern void RADEONPllErrataAfterIndex(RADEONInfoPtr info); 1261extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn); 1262extern void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn); 1263extern void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, 1264 RADEONInfoPtr info); 1265extern void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, 1266 RADEONSavePtr restore); 1267extern Bool 1268RADEONZaphodStringMatches(ScrnInfoPtr pScrn, const char *s, char *output_name); 1269 1270Bool RADEONGetRec(ScrnInfoPtr pScrn); 1271void RADEONFreeRec(ScrnInfoPtr pScrn); 1272Bool RADEONPreInitVisual(ScrnInfoPtr pScrn); 1273Bool RADEONPreInitWeight(ScrnInfoPtr pScrn); 1274 1275extern Bool RADEON_DP_I2CInit(ScrnInfoPtr pScrn, I2CBusPtr *bus_ptr, 1276 char *name, xf86OutputPtr output); 1277extern void RADEON_DP_GetDPCD(xf86OutputPtr output); 1278extern int RADEON_DP_GetSinkType(xf86OutputPtr output); 1279 1280/* radeon_pm.c */ 1281extern void RADEONPMInit(ScrnInfoPtr pScrn); 1282extern void RADEONPMBlockHandler(ScrnInfoPtr pScrn); 1283extern void RADEONPMEnterVT(ScrnInfoPtr pScrn); 1284extern void RADEONPMLeaveVT(ScrnInfoPtr pScrn); 1285extern void RADEONPMFini(ScrnInfoPtr pScrn); 1286 1287#ifdef USE_EXA 1288/* radeon_exa.c */ 1289extern Bool RADEONSetupMemEXA(ScreenPtr pScreen); 1290extern Bool radeon_transform_is_affine(PictTransformPtr t); 1291 1292/* radeon_exa_funcs.c */ 1293extern void RADEONCopyCP(PixmapPtr pDst, int srcX, int srcY, int dstX, 1294 int dstY, int w, int h); 1295extern void RADEONCopyMMIO(PixmapPtr pDst, int srcX, int srcY, int dstX, 1296 int dstY, int w, int h); 1297extern Bool RADEONDrawInitCP(ScreenPtr pScreen); 1298extern Bool RADEONDrawInitMMIO(ScreenPtr pScreen); 1299extern void RADEONDoPrepareCopyCP(ScrnInfoPtr pScrn, 1300 uint32_t src_pitch_offset, 1301 uint32_t dst_pitch_offset, 1302 uint32_t datatype, int rop, 1303 Pixel planemask); 1304extern void RADEONDoPrepareCopyMMIO(ScrnInfoPtr pScrn, 1305 uint32_t src_pitch_offset, 1306 uint32_t dst_pitch_offset, 1307 uint32_t datatype, int rop, 1308 Pixel planemask); 1309extern Bool R600DrawInit(ScreenPtr pScreen); 1310extern Bool R600LoadShaders(ScrnInfoPtr pScrn); 1311#ifdef XF86DRM_MODE 1312extern Bool EVERGREENDrawInit(ScreenPtr pScreen); 1313extern Bool EVERGREENLoadShaders(ScrnInfoPtr pScrn); 1314#endif 1315#endif 1316 1317#if defined(XF86DRI) && defined(USE_EXA) 1318/* radeon_exa.c */ 1319extern Bool RADEONGetDatatypeBpp(int bpp, uint32_t *type); 1320extern Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, 1321 uint32_t *pitch_offset); 1322extern unsigned long long RADEONTexOffsetStart(PixmapPtr pPix); 1323#endif 1324 1325/* radeon_modes.c */ 1326extern void RADEONSetPitch(ScrnInfoPtr pScrn); 1327extern DisplayModePtr RADEONProbeOutputModes(xf86OutputPtr output); 1328 1329/* radeon_output.c */ 1330extern RADEONI2CBusRec atom_setup_i2c_bus(int ddc_line); 1331extern RADEONI2CBusRec legacy_setup_i2c_bus(int ddc_line); 1332extern void RADEONGetPanelInfo(ScrnInfoPtr pScrn); 1333extern void RADEONInitConnector(xf86OutputPtr output); 1334extern void RADEONPrintPortMap(ScrnInfoPtr pScrn); 1335extern void RADEONSetOutputType(ScrnInfoPtr pScrn, 1336 RADEONOutputPrivatePtr radeon_output); 1337extern Bool RADEONSetupConnectors(ScrnInfoPtr pScrn); 1338extern Bool RADEONI2CDoLock(xf86OutputPtr output, I2CBusPtr b, Bool lock_state); 1339 1340extern Bool radeon_dp_mode_fixup(xf86OutputPtr output, DisplayModePtr mode, DisplayModePtr adjusted_mode); 1341 1342/* radeon_tv.c */ 1343extern void RADEONSaveTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1344extern void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, 1345 DisplayModePtr mode, xf86OutputPtr output); 1346extern void RADEONAdjustPLLRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, 1347 DisplayModePtr mode, xf86OutputPtr output); 1348extern void RADEONAdjustCrtc2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, 1349 DisplayModePtr mode, xf86OutputPtr output); 1350extern void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, 1351 DisplayModePtr mode, xf86OutputPtr output); 1352extern void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save, 1353 DisplayModePtr mode, BOOL IsPrimary); 1354extern void RADEONRestoreTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1355extern void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode); 1356 1357/* radeon_video.c */ 1358extern void RADEONInitVideo(ScreenPtr pScreen); 1359extern void RADEONResetVideo(ScrnInfoPtr pScrn); 1360extern Bool radeon_load_bicubic_texture(ScrnInfoPtr pScrn); 1361extern xf86CrtcPtr radeon_pick_best_crtc(ScrnInfoPtr pScrn, 1362 int x1, int x2, int y1, int y2); 1363 1364/* radeon_legacy_memory.c */ 1365extern uint32_t 1366radeon_legacy_allocate_memory(ScrnInfoPtr pScrn, 1367 void **mem_struct, 1368 int size, 1369 int align, 1370 int domain); 1371extern void 1372radeon_legacy_free_memory(ScrnInfoPtr pScrn, 1373 void *mem_struct); 1374 1375#ifdef XF86DRM_MODE 1376extern void radeon_cs_flush_indirect(ScrnInfoPtr pScrn); 1377extern void radeon_ddx_cs_start(ScrnInfoPtr pScrn, 1378 int num, const char *file, 1379 const char *func, int line); 1380void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, int new_fb_size); 1381#endif 1382struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix); 1383void radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_bo *bo); 1384 1385#ifdef XF86DRI 1386# ifdef USE_XAA 1387/* radeon_accelfuncs.c */ 1388extern void RADEONAccelInitCP(ScreenPtr pScreen, XAAInfoRecPtr a); 1389# endif 1390 1391#define RADEONCP_START(pScrn, info) \ 1392do { \ 1393 int _ret = drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_START); \ 1394 if (_ret) { \ 1395 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1396 "%s: CP start %d\n", __FUNCTION__, _ret); \ 1397 } \ 1398 info->cp->CPStarted = TRUE; \ 1399} while (0) 1400 1401#define RADEONCP_RELEASE(pScrn, info) \ 1402do { \ 1403 if (info->cs) { \ 1404 radeon_cs_flush_indirect(pScrn); \ 1405 } else if (info->cp->CPInUse) { \ 1406 RADEON_PURGE_CACHE(); \ 1407 RADEON_WAIT_UNTIL_IDLE(); \ 1408 RADEONCPReleaseIndirect(pScrn); \ 1409 info->cp->CPInUse = FALSE; \ 1410 } \ 1411} while (0) 1412 1413#define RADEONCP_STOP(pScrn, info) \ 1414do { \ 1415 int _ret; \ 1416 if (info->cp->CPStarted) { \ 1417 _ret = RADEONCPStop(pScrn, info); \ 1418 if (_ret) { \ 1419 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1420 "%s: CP stop %d\n", __FUNCTION__, _ret); \ 1421 } \ 1422 info->cp->CPStarted = FALSE; \ 1423 } \ 1424 if (info->ChipFamily < CHIP_FAMILY_R600) \ 1425 RADEONEngineRestore(pScrn); \ 1426 info->cp->CPRuns = FALSE; \ 1427} while (0) 1428 1429#define RADEONCP_RESET(pScrn, info) \ 1430do { \ 1431 int _ret = drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_RESET); \ 1432 if (_ret) { \ 1433 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1434 "%s: CP reset %d\n", __FUNCTION__, _ret); \ 1435 } \ 1436} while (0) 1437 1438#define RADEONCP_REFRESH(pScrn, info) \ 1439do { \ 1440 if (!info->cp->CPInUse && !info->cs) { \ 1441 if (info->cp->needCacheFlush) { \ 1442 RADEON_PURGE_CACHE(); \ 1443 RADEON_PURGE_ZCACHE(); \ 1444 info->cp->needCacheFlush = FALSE; \ 1445 } \ 1446 RADEON_WAIT_UNTIL_IDLE(); \ 1447 info->cp->CPInUse = TRUE; \ 1448 } \ 1449} while (0) 1450 1451 1452#define CP_PACKET0(reg, n) \ 1453 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 1454#define CP_PACKET1(reg0, reg1) \ 1455 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 11) | ((reg0) >> 2)) 1456#define CP_PACKET2() \ 1457 (RADEON_CP_PACKET2) 1458#define CP_PACKET3(pkt, n) \ 1459 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 1460 1461 1462#define RADEON_VERBOSE 0 1463 1464#define RING_LOCALS uint32_t *__head = NULL; int __expected; int __count = 0 1465 1466#define BEGIN_RING(n) do { \ 1467 if (RADEON_VERBOSE) { \ 1468 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ 1469 "BEGIN_RING(%d) in %s\n", (unsigned int)n, __FUNCTION__);\ 1470 } \ 1471 if (info->cs) { radeon_ddx_cs_start(pScrn, n, __FILE__, __func__, __LINE__); } else { \ 1472 if (++info->cp->dma_begin_count != 1) { \ 1473 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1474 "BEGIN_RING without end at %s:%d\n", \ 1475 info->cp->dma_debug_func, info->cp->dma_debug_lineno); \ 1476 info->cp->dma_begin_count = 1; \ 1477 } \ 1478 info->cp->dma_debug_func = __FILE__; \ 1479 info->cp->dma_debug_lineno = __LINE__; \ 1480 if (!info->cp->indirectBuffer) { \ 1481 info->cp->indirectBuffer = RADEONCPGetBuffer(pScrn); \ 1482 info->cp->indirectStart = 0; \ 1483 } else if (info->cp->indirectBuffer->used + (n) * (int)sizeof(uint32_t) > \ 1484 info->cp->indirectBuffer->total) { \ 1485 RADEONCPFlushIndirect(pScrn, 1); \ 1486 } \ 1487 __expected = n; \ 1488 __head = (pointer)((char *)info->cp->indirectBuffer->address + \ 1489 info->cp->indirectBuffer->used); \ 1490 __count = 0; \ 1491 } \ 1492} while (0) 1493 1494#define ADVANCE_RING() do { \ 1495 if (info->cs) radeon_cs_end(info->cs, __FILE__, __func__, __LINE__); else { \ 1496 if (info->cp->dma_begin_count-- != 1) { \ 1497 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1498 "ADVANCE_RING without begin at %s:%d\n", \ 1499 __FILE__, __LINE__); \ 1500 info->cp->dma_begin_count = 0; \ 1501 } \ 1502 if (__count != __expected) { \ 1503 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1504 "ADVANCE_RING count != expected (%d vs %d) at %s:%d\n", \ 1505 __count, __expected, __FILE__, __LINE__); \ 1506 } \ 1507 if (RADEON_VERBOSE) { \ 1508 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ 1509 "ADVANCE_RING() start: %d used: %d count: %d\n", \ 1510 info->cp->indirectStart, \ 1511 info->cp->indirectBuffer->used, \ 1512 __count * (int)sizeof(uint32_t)); \ 1513 } \ 1514 info->cp->indirectBuffer->used += __count * (int)sizeof(uint32_t); \ 1515 } \ 1516 } while (0) 1517 1518#define OUT_RING(x) do { \ 1519 if (RADEON_VERBOSE) { \ 1520 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ 1521 " OUT_RING(0x%08x)\n", (unsigned int)(x)); \ 1522 } \ 1523 if (info->cs) radeon_cs_write_dword(info->cs, (x)); else \ 1524 __head[__count++] = (x); \ 1525} while (0) 1526 1527#define OUT_RING_REG(reg, val) \ 1528do { \ 1529 OUT_RING(CP_PACKET0(reg, 0)); \ 1530 OUT_RING(val); \ 1531} while (0) 1532 1533#define OUT_RING_RELOC(x, read_domains, write_domain) \ 1534 do { \ 1535 int _ret; \ 1536 _ret = radeon_cs_write_reloc(info->cs, x, read_domains, write_domain, 0); \ 1537 if (_ret) ErrorF("reloc emit failure %d\n", _ret); \ 1538 } while(0) 1539 1540 1541#define FLUSH_RING() \ 1542do { \ 1543 if (RADEON_VERBOSE) \ 1544 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ 1545 "FLUSH_RING in %s\n", __FUNCTION__); \ 1546 if (info->cs) \ 1547 radeon_cs_flush_indirect(pScrn); \ 1548 else if (info->cp->indirectBuffer) \ 1549 RADEONCPFlushIndirect(pScrn, 0); \ 1550} while (0) 1551 1552 1553#define RADEON_WAIT_UNTIL_2D_IDLE() \ 1554do { \ 1555 if (info->ChipFamily < CHIP_FAMILY_R600) { \ 1556 BEGIN_RING(2); \ 1557 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \ 1558 OUT_RING((RADEON_WAIT_2D_IDLECLEAN | \ 1559 RADEON_WAIT_HOST_IDLECLEAN)); \ 1560 ADVANCE_RING(); \ 1561 } \ 1562} while (0) 1563 1564#define RADEON_WAIT_UNTIL_3D_IDLE() \ 1565do { \ 1566 if (info->ChipFamily < CHIP_FAMILY_R600) { \ 1567 BEGIN_RING(2); \ 1568 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \ 1569 OUT_RING((RADEON_WAIT_3D_IDLECLEAN | \ 1570 RADEON_WAIT_HOST_IDLECLEAN)); \ 1571 ADVANCE_RING(); \ 1572 } \ 1573} while (0) 1574 1575#define RADEON_WAIT_UNTIL_IDLE() \ 1576do { \ 1577 if (RADEON_VERBOSE) { \ 1578 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ 1579 "WAIT_UNTIL_IDLE() in %s\n", __FUNCTION__); \ 1580 } \ 1581 if (info->ChipFamily < CHIP_FAMILY_R600) { \ 1582 BEGIN_RING(2); \ 1583 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \ 1584 OUT_RING((RADEON_WAIT_2D_IDLECLEAN | \ 1585 RADEON_WAIT_3D_IDLECLEAN | \ 1586 RADEON_WAIT_HOST_IDLECLEAN)); \ 1587 ADVANCE_RING(); \ 1588 } \ 1589} while (0) 1590 1591#define RADEON_PURGE_CACHE() \ 1592do { \ 1593 if (info->ChipFamily < CHIP_FAMILY_R600) { \ 1594 BEGIN_RING(2); \ 1595 if (info->ChipFamily <= CHIP_FAMILY_RV280) { \ 1596 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1597 OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \ 1598 } else { \ 1599 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1600 OUT_RING(R300_RB3D_DC_FLUSH_ALL); \ 1601 } \ 1602 ADVANCE_RING(); \ 1603 } \ 1604} while (0) 1605 1606#define RADEON_PURGE_ZCACHE() \ 1607do { \ 1608 if (info->ChipFamily < CHIP_FAMILY_R600) { \ 1609 BEGIN_RING(2); \ 1610 if (info->ChipFamily <= CHIP_FAMILY_RV280) { \ 1611 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1612 OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL); \ 1613 } else { \ 1614 OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); \ 1615 OUT_RING(R300_ZC_FLUSH_ALL); \ 1616 } \ 1617 ADVANCE_RING(); \ 1618 } \ 1619} while (0) 1620 1621#endif /* XF86DRI */ 1622 1623#if defined(XF86DRI) && defined(USE_EXA) 1624 1625#ifdef XF86DRM_MODE 1626#define CS_FULL(cs) ((cs)->cdw > 15 * 1024) 1627#else 1628#define CS_FULL(cs) FALSE 1629#endif 1630 1631#define RADEON_SWITCH_TO_2D() \ 1632do { \ 1633 uint32_t flush = 0; \ 1634 switch (info->accel_state->engineMode) { \ 1635 case EXA_ENGINEMODE_UNKNOWN: \ 1636 flush = 1; \ 1637 break; \ 1638 case EXA_ENGINEMODE_3D: \ 1639 flush = !info->cs || CS_FULL(info->cs); \ 1640 break; \ 1641 case EXA_ENGINEMODE_2D: \ 1642 flush = info->cs && CS_FULL(info->cs); \ 1643 break; \ 1644 } \ 1645 if (flush) { \ 1646 if (info->cs) \ 1647 radeon_cs_flush_indirect(pScrn); \ 1648 else if (info->directRenderingEnabled) \ 1649 RADEONCPFlushIndirect(pScrn, 1); \ 1650 } \ 1651 info->accel_state->engineMode = EXA_ENGINEMODE_2D; \ 1652} while (0); 1653 1654#define RADEON_SWITCH_TO_3D() \ 1655do { \ 1656 uint32_t flush = 0; \ 1657 switch (info->accel_state->engineMode) { \ 1658 case EXA_ENGINEMODE_UNKNOWN: \ 1659 flush = 1; \ 1660 break; \ 1661 case EXA_ENGINEMODE_2D: \ 1662 flush = !info->cs || CS_FULL(info->cs); \ 1663 break; \ 1664 case EXA_ENGINEMODE_3D: \ 1665 flush = info->cs && CS_FULL(info->cs); \ 1666 break; \ 1667 } \ 1668 if (flush) { \ 1669 if (info->cs) \ 1670 radeon_cs_flush_indirect(pScrn); \ 1671 else if (info->directRenderingEnabled) \ 1672 RADEONCPFlushIndirect(pScrn, 1); \ 1673 } \ 1674 if (!info->accel_state->XInited3D) \ 1675 RADEONInit3DEngine(pScrn); \ 1676 info->accel_state->engineMode = EXA_ENGINEMODE_3D; \ 1677} while (0); 1678#else 1679#define RADEON_SWITCH_TO_2D() 1680#define RADEON_SWITCH_TO_3D() 1681#endif 1682 1683static __inline__ void RADEON_MARK_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn) 1684{ 1685#ifdef USE_EXA 1686 if (info->useEXA) 1687 exaMarkSync(pScrn->pScreen); 1688#endif 1689#ifdef USE_XAA 1690 if (!info->useEXA) 1691 SET_SYNC_FLAG(info->accel_state->accel); 1692#endif 1693} 1694 1695static __inline__ void RADEON_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn) 1696{ 1697#ifdef USE_EXA 1698 if (info->useEXA && pScrn->pScreen) 1699 exaWaitSync(pScrn->pScreen); 1700#endif 1701#ifdef USE_XAA 1702 if (!info->useEXA && info->accel_state->accel) 1703 info->accel_state->accel->Sync(pScrn); 1704#endif 1705} 1706 1707static __inline__ void radeon_init_timeout(struct timeval *endtime, 1708 unsigned int timeout) 1709{ 1710 gettimeofday(endtime, NULL); 1711 endtime->tv_usec += timeout; 1712 endtime->tv_sec += endtime->tv_usec / 1000000; 1713 endtime->tv_usec %= 1000000; 1714} 1715 1716static __inline__ int radeon_timedout(const struct timeval *endtime) 1717{ 1718 struct timeval now; 1719 gettimeofday(&now, NULL); 1720 return now.tv_sec == endtime->tv_sec ? 1721 now.tv_usec > endtime->tv_usec : now.tv_sec > endtime->tv_sec; 1722} 1723 1724enum { 1725 RADEON_CREATE_PIXMAP_TILING_MACRO = 0x10000000, 1726 RADEON_CREATE_PIXMAP_TILING_MICRO = 0x20000000, 1727}; 1728 1729#endif /* _RADEON_H_ */ 1730