radeon.h revision b7e1c893 
1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 *                VA Linux Systems Inc., Fremont, California.
4 *
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation on the rights to use, copy, modify, merge,
11 * publish, distribute, sublicense, and/or sell copies of the Software,
12 * and to permit persons to whom the Software is furnished to do so,
13 * subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial
17 * portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
22 * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 */
28
29/*
30 * Authors:
31 *   Kevin E. Martin <martin@xfree86.org>
32 *   Rickard E. Faith <faith@valinux.com>
33 *   Alan Hourihane <alanh@fairlite.demon.co.uk>
34 *
35 */
36
37#ifndef _RADEON_H_
38#define _RADEON_H_
39
40#include <stdlib.h>		/* For abs() */
41#include <unistd.h>		/* For usleep() */
42#include <sys/time.h>		/* For gettimeofday() */
43
44#include "config.h"
45#include "xf86str.h"
46#include "compiler.h"
47#include "xf86fbman.h"
48
49				/* PCI support */
50#include "xf86Pci.h"
51
52#ifdef USE_EXA
53#include "exa.h"
54#endif
55#ifdef USE_XAA
56#include "xaa.h"
57#endif
58
59				/* Exa and Cursor Support */
60#include "vbe.h"
61#include "xf86Cursor.h"
62
63				/* DDC support */
64#include "xf86DDC.h"
65
66				/* Xv support */
67#include "xf86xv.h"
68
69#include "radeon_probe.h"
70#include "radeon_tv.h"
71
72				/* DRI support */
73#ifdef XF86DRI
74#define _XF86DRI_SERVER_
75#include "dri.h"
76#include "GL/glxint.h"
77#include "xf86drm.h"
78
79#ifdef DAMAGE
80#include "damage.h"
81#include "globals.h"
82#endif
83#endif
84
85#include "xf86Crtc.h"
86#include "X11/Xatom.h"
87
88				/* Render support */
89#ifdef RENDER
90#include "picturestr.h"
91#endif
92
93#include "atipcirename.h"
94
95#ifndef MAX
96#define MAX(a,b) ((a)>(b)?(a):(b))
97#endif
98#ifndef MIN
99#define MIN(a,b) ((a)>(b)?(b):(a))
100#endif
101
102#if HAVE_BYTESWAP_H
103#include <byteswap.h>
104#elif defined(USE_SYS_ENDIAN_H)
105#include <sys/endian.h>
106#else
107#define bswap_16(value)  \
108        ((((value) & 0xff) << 8) | ((value) >> 8))
109
110#define bswap_32(value) \
111        (((uint32_t)bswap_16((uint16_t)((value) & 0xffff)) << 16) | \
112        (uint32_t)bswap_16((uint16_t)((value) >> 16)))
113
114#define bswap_64(value) \
115        (((uint64_t)bswap_32((uint32_t)((value) & 0xffffffff)) \
116            << 32) | \
117        (uint64_t)bswap_32((uint32_t)((value) >> 32)))
118#endif
119
120#if X_BYTE_ORDER == X_BIG_ENDIAN
121#define le32_to_cpu(x) bswap_32(x)
122#define le16_to_cpu(x) bswap_16(x)
123#define cpu_to_le32(x) bswap_32(x)
124#define cpu_to_le16(x) bswap_16(x)
125#else
126#define le32_to_cpu(x) (x)
127#define le16_to_cpu(x) (x)
128#define cpu_to_le32(x) (x)
129#define cpu_to_le16(x) (x)
130#endif
131
132/* Provide substitutes for gcc's __FUNCTION__ on other compilers */
133#if !defined(__GNUC__) && !defined(__FUNCTION__)
134# define __FUNCTION__ __func__		/* C99 */
135#endif
136
137#ifndef HAVE_XF86MODEBANDWIDTH
138extern unsigned int xf86ModeBandwidth(DisplayModePtr mode, int depth);
139#define MODE_BANDWIDTH MODE_BAD
140#endif
141
142typedef enum {
143    OPTION_NOACCEL,
144    OPTION_SW_CURSOR,
145    OPTION_DAC_6BIT,
146    OPTION_DAC_8BIT,
147#ifdef XF86DRI
148    OPTION_BUS_TYPE,
149    OPTION_CP_PIO,
150    OPTION_USEC_TIMEOUT,
151    OPTION_AGP_MODE,
152    OPTION_AGP_FW,
153    OPTION_GART_SIZE,
154    OPTION_GART_SIZE_OLD,
155    OPTION_RING_SIZE,
156    OPTION_BUFFER_SIZE,
157    OPTION_DEPTH_MOVE,
158    OPTION_PAGE_FLIP,
159    OPTION_NO_BACKBUFFER,
160    OPTION_XV_DMA,
161    OPTION_FBTEX_PERCENT,
162    OPTION_DEPTH_BITS,
163    OPTION_PCIAPER_SIZE,
164#ifdef USE_EXA
165    OPTION_ACCEL_DFS,
166#endif
167#endif
168    OPTION_IGNORE_EDID,
169    OPTION_DISP_PRIORITY,
170    OPTION_PANEL_SIZE,
171    OPTION_MIN_DOTCLOCK,
172    OPTION_COLOR_TILING,
173#ifdef XvExtension
174    OPTION_VIDEO_KEY,
175    OPTION_RAGE_THEATRE_CRYSTAL,
176    OPTION_RAGE_THEATRE_TUNER_PORT,
177    OPTION_RAGE_THEATRE_COMPOSITE_PORT,
178    OPTION_RAGE_THEATRE_SVIDEO_PORT,
179    OPTION_TUNER_TYPE,
180    OPTION_RAGE_THEATRE_MICROC_PATH,
181    OPTION_RAGE_THEATRE_MICROC_TYPE,
182    OPTION_SCALER_WIDTH,
183#endif
184#ifdef RENDER
185    OPTION_RENDER_ACCEL,
186    OPTION_SUBPIXEL_ORDER,
187#endif
188    OPTION_SHOWCACHE,
189    OPTION_DYNAMIC_CLOCKS,
190    OPTION_BIOS_HOTKEYS,
191    OPTION_VGA_ACCESS,
192    OPTION_REVERSE_DDC,
193    OPTION_LVDS_PROBE_PLL,
194    OPTION_ACCELMETHOD,
195    OPTION_CONNECTORTABLE,
196    OPTION_DRI,
197    OPTION_DEFAULT_CONNECTOR_TABLE,
198#if defined(__powerpc__)
199    OPTION_MAC_MODEL,
200#endif
201    OPTION_DEFAULT_TMDS_PLL,
202    OPTION_TVDAC_LOAD_DETECT,
203    OPTION_FORCE_TVOUT,
204    OPTION_TVSTD,
205    OPTION_IGNORE_LID_STATUS,
206    OPTION_DEFAULT_TVDAC_ADJ,
207    OPTION_INT10,
208    OPTION_EXA_VSYNC,
209    OPTION_ATOM_TVOUT,
210    OPTION_R4XX_ATOM
211} RADEONOpts;
212
213
214#define RADEON_IDLE_RETRY      16 /* Fall out of idle loops after this count */
215#define RADEON_TIMEOUT    2000000 /* Fall out of wait loops after this count */
216
217#define RADEON_VSYNC_TIMEOUT	20000 /* Maximum wait for VSYNC (in usecs) */
218
219/* Buffer are aligned on 4096 byte boundaries */
220#define RADEON_BUFFER_ALIGN 0x00000fff
221#define RADEON_VBIOS_SIZE 0x00010000
222#define RADEON_USE_RMX 0x80000000 /* mode flag for using RMX
223				   * Need to comfirm this is not used
224				   * for something else.
225				   */
226
227#define xFixedToFloat(f) (((float) (f)) / 65536)
228
229#define RADEON_LOGLEVEL_DEBUG 4
230
231/* for Xv, outputs */
232#define MAKE_ATOM(a) MakeAtom(a, sizeof(a) - 1, TRUE)
233
234/* Other macros */
235#define RADEON_ARRAY_SIZE(x)  (sizeof(x)/sizeof(x[0]))
236#define RADEON_ALIGN(x,bytes) (((x) + ((bytes) - 1)) & ~((bytes) - 1))
237#define RADEONPTR(pScrn)      ((RADEONInfoPtr)(pScrn)->driverPrivate)
238
239typedef struct {
240    int    revision;
241    uint16_t rr1_offset;
242    uint16_t rr2_offset;
243    uint16_t dyn_clk_offset;
244    uint16_t pll_offset;
245    uint16_t mem_config_offset;
246    uint16_t mem_reset_offset;
247    uint16_t short_mem_offset;
248    uint16_t rr3_offset;
249    uint16_t rr4_offset;
250} RADEONBIOSInitTable;
251
252#define RADEON_PLL_USE_BIOS_DIVS   (1 << 0)
253#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
254#define RADEON_PLL_USE_REF_DIV     (1 << 2)
255#define RADEON_PLL_LEGACY          (1 << 3)
256#define RADEON_PLL_PREFER_LOW_REF_DIV   (1 << 4)
257#define RADEON_PLL_PREFER_HIGH_REF_DIV  (1 << 5)
258#define RADEON_PLL_PREFER_LOW_FB_DIV    (1 << 6)
259#define RADEON_PLL_PREFER_HIGH_FB_DIV   (1 << 7)
260#define RADEON_PLL_PREFER_LOW_POST_DIV  (1 << 8)
261#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
262
263typedef struct {
264    uint16_t          reference_freq;
265    uint16_t          reference_div;
266    uint32_t          pll_in_min;
267    uint32_t          pll_in_max;
268    uint32_t          pll_out_min;
269    uint32_t          pll_out_max;
270    uint16_t          xclk;
271
272    uint32_t          min_ref_div;
273    uint32_t          max_ref_div;
274    uint32_t          min_post_div;
275    uint32_t          max_post_div;
276    uint32_t          min_feedback_div;
277    uint32_t          max_feedback_div;
278    uint32_t          best_vco;
279} RADEONPLLRec, *RADEONPLLPtr;
280
281typedef struct {
282    int               bitsPerPixel;
283    int               depth;
284    int               displayWidth;
285    int               displayHeight;
286    int               pixel_code;
287    int               pixel_bytes;
288    DisplayModePtr    mode;
289} RADEONFBLayout;
290
291typedef enum {
292    CHIP_FAMILY_UNKNOW,
293    CHIP_FAMILY_LEGACY,
294    CHIP_FAMILY_RADEON,
295    CHIP_FAMILY_RV100,
296    CHIP_FAMILY_RS100,    /* U1 (IGP320M) or A3 (IGP320)*/
297    CHIP_FAMILY_RV200,
298    CHIP_FAMILY_RS200,    /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */
299    CHIP_FAMILY_R200,
300    CHIP_FAMILY_RV250,
301    CHIP_FAMILY_RS300,    /* RS300/RS350 */
302    CHIP_FAMILY_RV280,
303    CHIP_FAMILY_R300,
304    CHIP_FAMILY_R350,
305    CHIP_FAMILY_RV350,
306    CHIP_FAMILY_RV380,    /* RV370/RV380/M22/M24 */
307    CHIP_FAMILY_R420,     /* R420/R423/M18 */
308    CHIP_FAMILY_RV410,    /* RV410, M26 */
309    CHIP_FAMILY_RS400,    /* xpress 200, 200m (RS400) Intel */
310    CHIP_FAMILY_RS480,    /* xpress 200, 200m (RS410/480/482/485) AMD */
311    CHIP_FAMILY_RV515,    /* rv515 */
312    CHIP_FAMILY_R520,    /* r520 */
313    CHIP_FAMILY_RV530,    /* rv530 */
314    CHIP_FAMILY_R580,    /* r580 */
315    CHIP_FAMILY_RV560,   /* rv560 */
316    CHIP_FAMILY_RV570,   /* rv570 */
317    CHIP_FAMILY_RS600,
318    CHIP_FAMILY_RS690,
319    CHIP_FAMILY_RS740,
320    CHIP_FAMILY_R600,    /* r600 */
321    CHIP_FAMILY_R630,
322    CHIP_FAMILY_RV610,
323    CHIP_FAMILY_RV630,
324    CHIP_FAMILY_RV670,
325    CHIP_FAMILY_RV620,
326    CHIP_FAMILY_RV635,
327    CHIP_FAMILY_RS780,
328    CHIP_FAMILY_RS880,
329    CHIP_FAMILY_RV770,
330    CHIP_FAMILY_RV730,
331    CHIP_FAMILY_RV710,
332    CHIP_FAMILY_LAST
333} RADEONChipFamily;
334
335#define IS_RV100_VARIANT ((info->ChipFamily == CHIP_FAMILY_RV100)  ||  \
336        (info->ChipFamily == CHIP_FAMILY_RV200)  ||  \
337        (info->ChipFamily == CHIP_FAMILY_RS100)  ||  \
338        (info->ChipFamily == CHIP_FAMILY_RS200)  ||  \
339        (info->ChipFamily == CHIP_FAMILY_RV250)  ||  \
340        (info->ChipFamily == CHIP_FAMILY_RV280)  ||  \
341        (info->ChipFamily == CHIP_FAMILY_RS300))
342
343
344#define IS_R300_VARIANT ((info->ChipFamily == CHIP_FAMILY_R300)  ||  \
345        (info->ChipFamily == CHIP_FAMILY_RV350) ||  \
346        (info->ChipFamily == CHIP_FAMILY_R350)  ||  \
347        (info->ChipFamily == CHIP_FAMILY_RV380) ||  \
348        (info->ChipFamily == CHIP_FAMILY_R420)  ||  \
349        (info->ChipFamily == CHIP_FAMILY_RV410) ||  \
350        (info->ChipFamily == CHIP_FAMILY_RS400) ||  \
351        (info->ChipFamily == CHIP_FAMILY_RS480))
352
353#define IS_AVIVO_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV515))
354
355#define IS_DCE3_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV620))
356
357#define IS_DCE32_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV730))
358
359#define IS_R600_3D (info->ChipFamily >= CHIP_FAMILY_R600)
360
361#define IS_R500_3D ((info->ChipFamily == CHIP_FAMILY_RV515)  ||  \
362	(info->ChipFamily == CHIP_FAMILY_R520)   ||  \
363	(info->ChipFamily == CHIP_FAMILY_RV530)  ||  \
364	(info->ChipFamily == CHIP_FAMILY_R580)   ||  \
365	(info->ChipFamily == CHIP_FAMILY_RV560)  ||  \
366	(info->ChipFamily == CHIP_FAMILY_RV570))
367
368#define IS_R300_3D ((info->ChipFamily == CHIP_FAMILY_R300)  ||  \
369	(info->ChipFamily == CHIP_FAMILY_RV350) ||  \
370	(info->ChipFamily == CHIP_FAMILY_R350)  ||  \
371	(info->ChipFamily == CHIP_FAMILY_RV380) ||  \
372	(info->ChipFamily == CHIP_FAMILY_R420)  ||  \
373	(info->ChipFamily == CHIP_FAMILY_RV410) ||  \
374	(info->ChipFamily == CHIP_FAMILY_RS690) ||  \
375	(info->ChipFamily == CHIP_FAMILY_RS600) ||  \
376	(info->ChipFamily == CHIP_FAMILY_RS740) ||  \
377	(info->ChipFamily == CHIP_FAMILY_RS400) ||  \
378	(info->ChipFamily == CHIP_FAMILY_RS480))
379
380/*
381 * Errata workarounds
382 */
383typedef enum {
384       CHIP_ERRATA_R300_CG             = 0x00000001,
385       CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
386       CHIP_ERRATA_PLL_DELAY           = 0x00000004
387} RADEONErrata;
388
389typedef enum {
390    RADEON_DVOCHIP_NONE,
391    RADEON_SIL_164,
392    RADEON_SIL_1178
393} RADEONExtTMDSChip;
394
395#if defined(__powerpc__)
396typedef enum {
397    RADEON_MAC_NONE,
398    RADEON_MAC_IBOOK,
399    RADEON_MAC_POWERBOOK_EXTERNAL,
400    RADEON_MAC_POWERBOOK_INTERNAL,
401    RADEON_MAC_POWERBOOK_VGA,
402    RADEON_MAC_MINI_EXTERNAL,
403    RADEON_MAC_MINI_INTERNAL,
404    RADEON_MAC_IMAC_G5_ISIGHT,
405    RADEON_MAC_EMAC
406} RADEONMacModel;
407#endif
408
409typedef enum {
410	CARD_PCI,
411	CARD_AGP,
412	CARD_PCIE
413} RADEONCardType;
414
415typedef struct _atomBiosHandle *atomBiosHandlePtr;
416
417typedef struct {
418    uint32_t pci_device_id;
419    RADEONChipFamily chip_family;
420    int mobility;
421    int igp;
422    int nocrtc2;
423    int nointtvout;
424    int singledac;
425} RADEONCardInfo;
426
427#ifdef XF86DRI
428struct radeon_cp {
429    Bool              CPRuns;           /* CP is running */
430    Bool              CPInUse;          /* CP has been used by X server */
431    Bool              CPStarted;        /* CP has started */
432    int               CPMode;           /* CP mode that server/clients use */
433    int               CPFifoSize;       /* Size of the CP command FIFO */
434    int               CPusecTimeout;    /* CP timeout in usecs */
435    Bool              needCacheFlush;
436
437    /* CP accleration */
438    drmBufPtr         indirectBuffer;
439    int               indirectStart;
440
441    /* Debugging info for BEGIN_RING/ADVANCE_RING pairs. */
442    int               dma_begin_count;
443    char              *dma_debug_func;
444    int               dma_debug_lineno;
445
446    };
447
448typedef struct {
449    /* Nothing here yet */
450    int dummy;
451} RADEONConfigPrivRec, *RADEONConfigPrivPtr;
452
453typedef struct {
454#ifdef PER_CONTEXT_SAREA
455    drm_context_t ctx_id;
456    drm_handle_t sarea_handle;
457#else
458    /* Nothing here yet */
459    int dummy;
460#endif
461} RADEONDRIContextRec, *RADEONDRIContextPtr;
462
463struct radeon_dri {
464    Bool              noBackBuffer;
465
466    Bool              newMemoryMap;
467    drmVersionPtr     pLibDRMVersion;
468    drmVersionPtr     pKernelDRMVersion;
469    DRIInfoPtr        pDRIInfo;
470    int               drmFD;
471    int               numVisualConfigs;
472    __GLXvisualConfig *pVisualConfigs;
473    RADEONConfigPrivPtr pVisualConfigsPriv;
474    Bool             (*DRICloseScreen)(int, ScreenPtr);
475
476    drm_handle_t      fbHandle;
477
478    drmSize           registerSize;
479    drm_handle_t      registerHandle;
480
481    drmSize           pciSize;
482    drm_handle_t      pciMemHandle;
483    unsigned char     *PCI;             /* Map */
484
485    Bool              depthMoves;       /* Enable depth moves -- slow! */
486    Bool              allowPageFlip;    /* Enable 3d page flipping */
487#ifdef DAMAGE
488    DamagePtr         pDamage;
489    RegionRec         driRegion;
490#endif
491    Bool              have3DWindows;    /* Are there any 3d clients? */
492
493    int               pciAperSize;
494    drmSize           gartSize;
495    drm_handle_t      agpMemHandle;     /* Handle from drmAgpAlloc */
496    unsigned long     gartOffset;
497    unsigned char     *AGP;             /* Map */
498    int               agpMode;
499
500    uint32_t          pciCommand;
501
502    /* CP ring buffer data */
503    unsigned long     ringStart;        /* Offset into GART space */
504    drm_handle_t      ringHandle;       /* Handle from drmAddMap */
505    drmSize           ringMapSize;      /* Size of map */
506    int               ringSize;         /* Size of ring (in MB) */
507    drmAddress        ring;             /* Map */
508    int               ringSizeLog2QW;
509
510    unsigned long     ringReadOffset;   /* Offset into GART space */
511    drm_handle_t      ringReadPtrHandle; /* Handle from drmAddMap */
512    drmSize           ringReadMapSize;  /* Size of map */
513    drmAddress        ringReadPtr;      /* Map */
514
515    /* CP vertex/indirect buffer data */
516    unsigned long     bufStart;         /* Offset into GART space */
517    drm_handle_t      bufHandle;        /* Handle from drmAddMap */
518    drmSize           bufMapSize;       /* Size of map */
519    int               bufSize;          /* Size of buffers (in MB) */
520    drmAddress        buf;              /* Map */
521    int               bufNumBufs;       /* Number of buffers */
522    drmBufMapPtr      buffers;          /* Buffer map */
523
524    /* CP GART Texture data */
525    unsigned long     gartTexStart;      /* Offset into GART space */
526    drm_handle_t      gartTexHandle;     /* Handle from drmAddMap */
527    drmSize           gartTexMapSize;    /* Size of map */
528    int               gartTexSize;       /* Size of GART tex space (in MB) */
529    drmAddress        gartTex;           /* Map */
530    int               log2GARTTexGran;
531
532    /* DRI screen private data */
533    int               fbX;
534    int               fbY;
535    int               backX;
536    int               backY;
537    int               depthX;
538    int               depthY;
539
540    int               frontOffset;
541    int               frontPitch;
542    int               backOffset;
543    int               backPitch;
544    int               depthOffset;
545    int               depthPitch;
546    int               depthBits;
547    int               textureOffset;
548    int               textureSize;
549    int               log2TexGran;
550
551    int               pciGartSize;
552    uint32_t          pciGartOffset;
553    void              *pciGartBackup;
554
555    int               irq;
556
557#ifdef PER_CONTEXT_SAREA
558    int               perctx_sarea_size;
559#endif
560
561#ifdef USE_XAA
562    uint32_t          frontPitchOffset;
563    uint32_t          backPitchOffset;
564    uint32_t          depthPitchOffset;
565
566    /* offscreen memory management */
567    int               backLines;
568    FBAreaPtr         backArea;
569    int               depthTexLines;
570    FBAreaPtr         depthTexArea;
571#endif
572
573};
574#endif
575
576struct radeon_accel_state {
577    /* common accel data */
578    int               fifo_slots;       /* Free slots in the FIFO (64 max)   */
579				/* Computed values for Radeon */
580    uint32_t          dp_gui_master_cntl;
581    uint32_t          dp_gui_master_cntl_clip;
582    uint32_t          trans_color;
583				/* Saved values for ScreenToScreenCopy */
584    int               xdir;
585    int               ydir;
586    uint32_t          dst_pitch_offset;
587
588    /* render accel */
589    unsigned short    texW[2];
590    unsigned short    texH[2];
591    Bool              XInited3D; /* X itself has the 3D context */
592    int               num_gb_pipes;
593    Bool              has_tcl;
594
595#ifdef USE_EXA
596    /* EXA */
597    ExaDriverPtr      exa;
598    int               exaSyncMarker;
599    int               exaMarkerSynced;
600    int               engineMode;
601#define EXA_ENGINEMODE_UNKNOWN 0
602#define EXA_ENGINEMODE_2D      1
603#define EXA_ENGINEMODE_3D      2
604
605    Bool              is_transform[2];
606    PictTransform     *transform[2];
607    Bool              has_mask;
608    /* Whether we are tiling horizontally and vertically */
609    Bool              need_src_tile_x;
610    Bool              need_src_tile_y;
611    /* Size of tiles ... set to 65536x65536 if not tiling in that direction */
612    Bool              src_tile_width;
613    Bool              src_tile_height;
614
615    Bool              vsync;
616
617    drmBufPtr         ib;
618    int               vb_index;
619
620    // shader storage
621    ExaOffscreenArea  *shaders;
622    uint32_t          solid_vs_offset;
623    uint32_t          solid_ps_offset;
624    uint32_t          copy_vs_offset;
625    uint32_t          copy_ps_offset;
626    uint32_t          comp_vs_offset;
627    uint32_t          comp_ps_offset;
628    uint32_t          comp_mask_ps_offset;
629    uint32_t          xv_vs_offset;
630    uint32_t          xv_ps_offset;
631
632    //size/addr stuff
633    uint32_t          src_size[2];
634    uint64_t          src_mc_addr[2];
635    uint32_t          src_pitch[2];
636    uint32_t          src_width[2];
637    uint32_t          src_height[2];
638    uint32_t          src_bpp[2];
639    uint32_t          dst_size;
640    uint64_t          dst_mc_addr;
641    uint32_t          dst_pitch;
642    uint32_t          dst_height;
643    uint32_t          dst_bpp;
644    uint32_t          vs_size;
645    uint64_t          vs_mc_addr;
646    uint32_t          ps_size;
647    uint64_t          ps_mc_addr;
648    uint32_t          vb_size;
649    uint64_t          vb_mc_addr;
650
651    // UTS/DFS
652    drmBufPtr         scratch;
653
654    // copy
655    ExaOffscreenArea  *copy_area;
656    Bool              same_surface;
657    int               rop;
658    uint32_t          planemask;
659
660    // composite
661    Bool              component_alpha;
662    Bool              src_alpha;
663#endif
664
665#ifdef USE_XAA
666    /* XAA */
667    XAAInfoRecPtr     accel;
668				/* ScanlineScreenToScreenColorExpand support */
669    unsigned char     *scratch_buffer[1];
670    unsigned char     *scratch_save;
671    int               scanline_x;
672    int               scanline_y;
673    int               scanline_w;
674    int               scanline_h;
675    int               scanline_h_w;
676    int               scanline_words;
677    int               scanline_direct;
678    int               scanline_bpp;     /* Only used for ImageWrite */
679    int               scanline_fg;
680    int               scanline_bg;
681    int               scanline_hpass;
682    int               scanline_x1clip;
683    int               scanline_x2clip;
684				/* Saved values for DashedTwoPointLine */
685    int               dashLen;
686    uint32_t          dashPattern;
687    int               dash_fg;
688    int               dash_bg;
689
690    FBLinearPtr       RenderTex;
691    void              (*RenderCallback)(ScrnInfoPtr);
692    Time              RenderTimeout;
693    /*
694     * XAAForceTransBlit is used to change the behavior of the XAA
695     * SetupForScreenToScreenCopy function, to make it DGA-friendly.
696     */
697    Bool              XAAForceTransBlit;
698#endif
699
700};
701
702typedef struct {
703    EntityInfoPtr     pEnt;
704    pciVideoPtr       PciInfo;
705    PCITAG            PciTag;
706    int               Chipset;
707    RADEONChipFamily  ChipFamily;
708    RADEONErrata      ChipErrata;
709
710    unsigned long long     LinearAddr;       /* Frame buffer physical address     */
711    unsigned long long     MMIOAddr;         /* MMIO region physical address      */
712    unsigned long long     BIOSAddr;         /* BIOS physical address             */
713    uint32_t          fbLocation;
714    uint32_t          gartLocation;
715    uint32_t          mc_fb_location;
716    uint32_t          mc_agp_location;
717    uint32_t          mc_agp_location_hi;
718
719    void              *MMIO;            /* Map of MMIO region                */
720    void              *FB;              /* Map of frame buffer               */
721    uint8_t           *VBIOS;           /* Video BIOS pointer                */
722
723    Bool              IsAtomBios;       /* New BIOS used in R420 etc.        */
724    int               ROMHeaderStart;   /* Start of the ROM Info Table       */
725    int               MasterDataStart;  /* Offset for Master Data Table for ATOM BIOS */
726
727    uint32_t          MemCntl;
728    uint32_t          BusCntl;
729    unsigned long     MMIOSize;         /* MMIO region physical address      */
730    unsigned long     FbMapSize;        /* Size of frame buffer, in bytes    */
731    unsigned long     FbSecureSize;     /* Size of secured fb area at end of
732                                           framebuffer */
733
734    Bool              IsMobility;       /* Mobile chips for laptops */
735    Bool              IsIGP;            /* IGP chips */
736    Bool              HasSingleDAC;     /* only TVDAC on chip */
737    Bool              ddc_mode;         /* Validate mode by matching exactly
738					 * the modes supported in DDC data
739					 */
740    Bool              R300CGWorkaround;
741
742				/* EDID or BIOS values for FPs */
743    int               RefDivider;
744    int               FeedbackDivider;
745    int               PostDivider;
746    Bool              UseBiosDividers;
747				/* EDID data using DDC interface */
748    Bool              ddc_bios;
749    Bool              ddc1;
750    Bool              ddc2;
751
752    RADEONPLLRec      pll;
753
754    int               RamWidth;
755    float	      sclk;		/* in MHz */
756    float	      mclk;		/* in MHz */
757    Bool	      IsDDR;
758    int               DispPriority;
759
760    RADEONSavePtr     SavedReg;         /* Original (text) mode              */
761    RADEONSavePtr     ModeReg;          /* Current mode                      */
762    Bool              (*CloseScreen)(int, ScreenPtr);
763
764    void              (*BlockHandler)(int, pointer, pointer, pointer);
765
766    Bool              PaletteSavedOnVT; /* Palette saved on last VT switch   */
767
768    xf86CursorInfoPtr cursor;
769#ifdef ARGB_CURSOR
770    Bool	      cursor_argb;
771#endif
772    int               cursor_fg;
773    int               cursor_bg;
774
775    int               pix24bpp;         /* Depth of pixmap for 24bpp fb      */
776    Bool              dac6bits;         /* Use 6 bit DAC?                    */
777
778    DGAModePtr        DGAModes;
779    int               numDGAModes;
780    Bool              DGAactive;
781    int               DGAViewportStatus;
782    DGAFunctionRec    DGAFuncs;
783
784    RADEONFBLayout    CurrentLayout;
785
786#ifdef XF86DRI
787    Bool              directRenderingEnabled;
788    Bool              directRenderingInited;
789    RADEONCardType    cardType;            /* Current card is a PCI card */
790    struct radeon_cp  *cp;
791    struct radeon_dri  *dri;
792#ifdef USE_EXA
793    Bool              accelDFS;
794#endif
795    Bool              DMAForXv;
796#endif /* XF86DRI */
797
798    /* accel */
799    Bool              RenderAccel; /* Render */
800    Bool              allowColorTiling;
801    Bool              tilingEnabled; /* mirror of sarea->tiling_enabled */
802    struct radeon_accel_state *accel_state;
803    Bool              accelOn;
804    Bool              useEXA;
805#ifdef USE_EXA
806    XF86ModReqInfo    exaReq;
807#endif
808#ifdef USE_XAA
809    XF86ModReqInfo    xaaReq;
810#endif
811
812				/* XVideo */
813    XF86VideoAdaptorPtr adaptor;
814    void              (*VideoTimerCallback)(ScrnInfoPtr, Time);
815    int               videoKey;
816    int		      RageTheatreCrystal;
817    int               RageTheatreTunerPort;
818    int               RageTheatreCompositePort;
819    int               RageTheatreSVideoPort;
820    int               tunerType;
821    char*             RageTheatreMicrocPath;
822    char*             RageTheatreMicrocType;
823    Bool              MM_TABLE_valid;
824    struct {
825    	uint8_t table_revision;
826	uint8_t table_size;
827        uint8_t tuner_type;
828        uint8_t audio_chip;
829        uint8_t product_id;
830        uint8_t tuner_voltage_teletext_fm;
831        uint8_t i2s_config; /* configuration of the sound chip */
832        uint8_t video_decoder_type;
833        uint8_t video_decoder_host_config;
834        uint8_t input[5];
835    } MM_TABLE;
836    uint16_t video_decoder_type;
837    int overlay_scaler_buffer_width;
838    int ecp_div;
839
840    /* general */
841    Bool              showCache;
842    OptionInfoPtr     Options;
843
844    DisplayModePtr currentMode, savedCurrentMode;
845
846    /* special handlings for DELL triple-head server */
847    Bool              IsDellServer;
848
849    Bool              VGAAccess;
850
851    int               MaxSurfaceWidth;
852    int               MaxLines;
853
854    Bool want_vblank_interrupts;
855    RADEONBIOSConnector BiosConnector[RADEON_MAX_BIOS_CONNECTOR];
856    radeon_encoder_ptr encoders[RADEON_MAX_BIOS_CONNECTOR];
857    RADEONBIOSInitTable BiosTable;
858
859    /* save crtc state for console restore */
860    Bool              crtc_on;
861    Bool              crtc2_on;
862
863    Bool              InternalTVOut;
864
865#if defined(__powerpc__)
866    RADEONMacModel    MacModel;
867#endif
868    RADEONExtTMDSChip ext_tmds_chip;
869
870    atomBiosHandlePtr atomBIOS;
871    unsigned long FbFreeStart, FbFreeSize;
872    unsigned char*      BIOSCopy;
873
874    Rotation rotation;
875    void (*PointerMoved)(int, int, int);
876    CreateScreenResourcesProcPtr CreateScreenResources;
877
878    /* if no devices are connected at server startup */
879    Bool              first_load_no_devices;
880
881    Bool              IsSecondary;
882    Bool              IsPrimary;
883
884    Bool              r600_shadow_fb;
885    void *fb_shadow;
886
887    /* some server chips have a hardcoded edid in the bios so that they work with KVMs */
888    Bool get_hardcoded_edid_from_bios;
889
890    int               virtualX;
891    int               virtualY;
892
893    Bool              r4xx_atom;
894
895} RADEONInfoRec, *RADEONInfoPtr;
896
897#define RADEONWaitForFifo(pScrn, entries)				\
898do {									\
899    if (info->accel_state->fifo_slots < entries)			\
900	RADEONWaitForFifoFunction(pScrn, entries);			\
901    info->accel_state->fifo_slots -= entries;				\
902} while (0)
903
904/* legacy_crtc.c */
905extern void legacy_crtc_dpms(xf86CrtcPtr crtc, int mode);
906extern void legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
907				 DisplayModePtr adjusted_mode, int x, int y);
908extern void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn,
909					 RADEONSavePtr restore);
910extern void RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn,
911				       RADEONSavePtr restore);
912extern void RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn,
913					RADEONSavePtr restore);
914extern void RADEONRestorePLLRegisters(ScrnInfoPtr pScrn,
915				      RADEONSavePtr restore);
916extern void RADEONRestorePLL2Registers(ScrnInfoPtr pScrn,
917				       RADEONSavePtr restore);
918extern void RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
919extern void RADEONSaveCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
920extern void RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save);
921extern void RADEONSavePLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
922extern void RADEONSavePLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save);
923
924/* legacy_output.c */
925extern RADEONMonitorType legacy_dac_detect(xf86OutputPtr output);
926extern void legacy_output_dpms(xf86OutputPtr output, int mode);
927extern void legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode,
928				   DisplayModePtr adjusted_mode);
929extern I2CDevPtr RADEONDVODeviceInit(I2CBusPtr b, I2CSlaveAddr addr);
930extern Bool RADEONDVOReadByte(I2CDevPtr dvo, int addr, uint8_t *ch);
931extern Bool RADEONDVOWriteByte(I2CDevPtr dvo, int addr, uint8_t ch);
932extern void RADEONRestoreDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
933extern void RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
934extern void RADEONRestoreFP2Registers(ScrnInfoPtr pScrn, RADEONSavePtr restore);
935extern void RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
936extern void RADEONRestoreRMXRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
937extern void RADEONSaveDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
938extern void RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
939
940extern void RADEONGetTVDacAdjInfo(ScrnInfoPtr pScrn, radeon_tvdac_ptr tvdac);
941extern void RADEONGetTMDSInfoFromTable(ScrnInfoPtr pScrn, radeon_tmds_ptr tmds);
942extern void RADEONGetTMDSInfo(ScrnInfoPtr pScrn, radeon_tmds_ptr tmds);
943extern void RADEONGetExtTMDSInfo(ScrnInfoPtr pScrn, radeon_dvo_ptr dvo);
944extern void RADEONGetLVDSInfo(ScrnInfoPtr pScrn, radeon_lvds_ptr lvds);
945
946/* radeon_accel.c */
947extern Bool RADEONAccelInit(ScreenPtr pScreen);
948extern void RADEONEngineFlush(ScrnInfoPtr pScrn);
949extern void RADEONEngineInit(ScrnInfoPtr pScrn);
950extern void RADEONEngineReset(ScrnInfoPtr pScrn);
951extern void RADEONEngineRestore(ScrnInfoPtr pScrn);
952extern uint8_t *RADEONHostDataBlit(ScrnInfoPtr pScrn, unsigned int cpp,
953				 unsigned int w, uint32_t dstPitchOff,
954				 uint32_t *bufPitch, int x, int *y,
955				 unsigned int *h, unsigned int *hpass);
956extern void RADEONHostDataBlitCopyPass(ScrnInfoPtr pScrn,
957				       unsigned int bpp,
958				       uint8_t *dst, uint8_t *src,
959				       unsigned int hpass,
960				       unsigned int dstPitch,
961				       unsigned int srcPitch);
962extern void  RADEONCopySwap(uint8_t *dst, uint8_t *src, unsigned int size, int swap);
963extern void RADEONHostDataParams(ScrnInfoPtr pScrn, uint8_t *dst,
964				 uint32_t pitch, int cpp,
965				 uint32_t *dstPitchOffset, int *x, int *y);
966extern void RADEONInit3DEngine(ScrnInfoPtr pScrn);
967extern void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries);
968#ifdef XF86DRI
969extern drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn);
970extern void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard);
971extern void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn);
972extern int RADEONCPStop(ScrnInfoPtr pScrn,  RADEONInfoPtr info);
973#  ifdef USE_XAA
974extern Bool RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen);
975#  endif
976#endif
977
978#ifdef USE_XAA
979/* radeon_accelfuncs.c */
980extern void RADEONAccelInitMMIO(ScreenPtr pScreen, XAAInfoRecPtr a);
981extern Bool RADEONSetupMemXAA(int scrnIndex, ScreenPtr pScreen);
982#endif
983
984/* radeon_bios.c */
985extern Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10);
986extern Bool RADEONGetClockInfoFromBIOS(ScrnInfoPtr pScrn);
987extern Bool RADEONGetConnectorInfoFromBIOS(ScrnInfoPtr pScrn);
988extern Bool RADEONGetDAC2InfoFromBIOS(ScrnInfoPtr pScrn, radeon_tvdac_ptr tvdac);
989extern Bool RADEONGetExtTMDSInfoFromBIOS (ScrnInfoPtr pScrn, radeon_dvo_ptr dvo);
990extern xf86MonPtr RADEONGetHardCodedEDIDFromBIOS(xf86OutputPtr output);
991extern Bool RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn);
992extern Bool RADEONGetLVDSInfoFromBIOS(ScrnInfoPtr pScrn, radeon_lvds_ptr lvds);
993extern Bool RADEONGetTMDSInfoFromBIOS(ScrnInfoPtr pScrn, radeon_tmds_ptr tmds);
994extern Bool RADEONGetTVInfoFromBIOS(xf86OutputPtr output);
995extern Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output);
996extern Bool RADEONPostCardFromBIOSTables(ScrnInfoPtr pScrn);
997extern Bool radeon_card_posted(ScrnInfoPtr pScrn);
998
999/* radeon_commonfuncs.c */
1000#ifdef XF86DRI
1001extern void RADEONWaitForIdleCP(ScrnInfoPtr pScrn);
1002extern void RADEONWaitForVLineCP(ScrnInfoPtr pScrn, PixmapPtr pPix,
1003	int crtc, int start, int stop);
1004#endif
1005extern void RADEONWaitForIdleMMIO(ScrnInfoPtr pScrn);
1006extern void RADEONWaitForVLineMMIO(ScrnInfoPtr pScrn, PixmapPtr pPix,
1007	int crtc, int start, int stop);
1008
1009/* radeon_crtc.c */
1010extern void radeon_crtc_dpms(xf86CrtcPtr crtc, int mode);
1011extern void radeon_crtc_load_lut(xf86CrtcPtr crtc);
1012extern void radeon_crtc_modeset_ioctl(xf86CrtcPtr crtc, Bool post);
1013extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask);
1014extern void RADEONBlank(ScrnInfoPtr pScrn);
1015extern void RADEONComputePLL(RADEONPLLPtr pll, unsigned long freq,
1016			     uint32_t *chosen_dot_clock_freq,
1017			     uint32_t *chosen_feedback_div,
1018			     uint32_t *chosen_reference_div,
1019			     uint32_t *chosen_post_div, int flags);
1020extern DisplayModePtr RADEONCrtcFindClosestMode(xf86CrtcPtr crtc,
1021						DisplayModePtr pMode);
1022extern void RADEONUnblank(ScrnInfoPtr pScrn);
1023extern Bool RADEONSetTiling(ScrnInfoPtr pScrn);
1024extern void RADEONInitDispBandwidth(ScrnInfoPtr pScrn);
1025
1026/* radeon_cursor.c */
1027extern Bool RADEONCursorInit(ScreenPtr pScreen);
1028extern void radeon_crtc_hide_cursor(xf86CrtcPtr crtc);
1029extern void radeon_crtc_load_cursor_argb(xf86CrtcPtr crtc, CARD32 *image);
1030extern void radeon_crtc_set_cursor_colors(xf86CrtcPtr crtc, int bg, int fg);
1031extern void radeon_crtc_set_cursor_position(xf86CrtcPtr crtc, int x, int y);
1032extern void radeon_crtc_show_cursor(xf86CrtcPtr crtc);
1033
1034/* radeon_dga.c */
1035extern Bool RADEONDGAInit(ScreenPtr pScreen);
1036
1037#ifdef XF86DRI
1038/* radeon_dri.c */
1039extern void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen);
1040extern void RADEONDRICloseScreen(ScreenPtr pScreen);
1041extern Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen);
1042extern int RADEONDRIGetPciAperTableSize(ScrnInfoPtr pScrn);
1043extern Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn);
1044extern void RADEONDRIResume(ScreenPtr pScreen);
1045extern Bool RADEONDRIScreenInit(ScreenPtr pScreen);
1046extern int RADEONDRISetParam(ScrnInfoPtr pScrn,
1047			     unsigned int param, int64_t value);
1048extern Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on);
1049extern void RADEONDRIStop(ScreenPtr pScreen);
1050#endif
1051
1052/* radeon_driver.c */
1053extern void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool clone);
1054extern void RADEONChangeSurfaces(ScrnInfoPtr pScrn);
1055extern RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn);
1056extern int RADEONMinBits(int val);
1057extern unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr);
1058extern unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr);
1059extern unsigned RADEONINPCIE(ScrnInfoPtr pScrn, int addr);
1060extern void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, uint32_t data);
1061extern void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, uint32_t data);
1062extern void RADEONOUTPCIE(ScrnInfoPtr pScrn, int addr, uint32_t data);
1063extern void RADEONPllErrataAfterData(RADEONInfoPtr info);
1064extern void RADEONPllErrataAfterIndex(RADEONInfoPtr info);
1065extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn);
1066extern void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn);
1067extern void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
1068				      RADEONInfoPtr info);
1069extern void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
1070					 RADEONSavePtr restore);
1071
1072#ifdef USE_EXA
1073/* radeon_exa.c */
1074extern Bool RADEONSetupMemEXA(ScreenPtr pScreen);
1075
1076/* radeon_exa_funcs.c */
1077extern void RADEONCopyCP(PixmapPtr pDst, int srcX, int srcY, int dstX,
1078			 int dstY, int w, int h);
1079extern void RADEONCopyMMIO(PixmapPtr pDst, int srcX, int srcY, int dstX,
1080			   int dstY, int w, int h);
1081extern Bool RADEONDrawInitCP(ScreenPtr pScreen);
1082extern Bool RADEONDrawInitMMIO(ScreenPtr pScreen);
1083extern void RADEONDoPrepareCopyCP(ScrnInfoPtr pScrn,
1084				  uint32_t src_pitch_offset,
1085				  uint32_t dst_pitch_offset,
1086				  uint32_t datatype, int rop,
1087				  Pixel planemask);
1088extern void RADEONDoPrepareCopyMMIO(ScrnInfoPtr pScrn,
1089				    uint32_t src_pitch_offset,
1090				    uint32_t dst_pitch_offset,
1091				    uint32_t datatype, int rop,
1092				    Pixel planemask);
1093extern Bool R600DrawInit(ScreenPtr pScreen);
1094extern Bool R600LoadShaders(ScrnInfoPtr pScrn);
1095#endif
1096
1097#if defined(XF86DRI) && defined(USE_EXA)
1098/* radeon_exa.c */
1099extern Bool RADEONGetDatatypeBpp(int bpp, uint32_t *type);
1100extern Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix,
1101				       uint32_t *pitch_offset);
1102extern unsigned long long RADEONTexOffsetStart(PixmapPtr pPix);
1103#endif
1104
1105/* radeon_modes.c */
1106extern void RADEONSetPitch(ScrnInfoPtr pScrn);
1107extern DisplayModePtr RADEONProbeOutputModes(xf86OutputPtr output);
1108
1109/* radeon_output.c */
1110extern RADEONI2CBusRec atom_setup_i2c_bus(int ddc_line);
1111extern RADEONI2CBusRec legacy_setup_i2c_bus(int ddc_line);
1112extern void RADEONGetPanelInfo(ScrnInfoPtr pScrn);
1113extern void RADEONInitConnector(xf86OutputPtr output);
1114extern void RADEONPrintPortMap(ScrnInfoPtr pScrn);
1115extern void RADEONSetOutputType(ScrnInfoPtr pScrn,
1116				RADEONOutputPrivatePtr radeon_output);
1117extern Bool RADEONSetupConnectors(ScrnInfoPtr pScrn);
1118extern Bool RADEONI2CDoLock(xf86OutputPtr output, Bool lock_state);
1119
1120
1121/* radeon_tv.c */
1122extern void RADEONSaveTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
1123extern void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
1124					   DisplayModePtr mode, xf86OutputPtr output);
1125extern void RADEONAdjustPLLRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
1126					  DisplayModePtr mode, xf86OutputPtr output);
1127extern void RADEONAdjustCrtc2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
1128					   DisplayModePtr mode, xf86OutputPtr output);
1129extern void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
1130					  DisplayModePtr mode, xf86OutputPtr output);
1131extern void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
1132                                  DisplayModePtr mode, BOOL IsPrimary);
1133extern void RADEONRestoreTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
1134extern void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode);
1135
1136/* radeon_video.c */
1137extern void RADEONInitVideo(ScreenPtr pScreen);
1138extern void RADEONResetVideo(ScrnInfoPtr pScrn);
1139
1140/* radeon_legacy_memory.c */
1141extern uint32_t
1142radeon_legacy_allocate_memory(ScrnInfoPtr pScrn,
1143			      void **mem_struct,
1144			      int size,
1145			      int align);
1146extern void
1147radeon_legacy_free_memory(ScrnInfoPtr pScrn,
1148		          void *mem_struct);
1149
1150#ifdef XF86DRI
1151#  ifdef USE_XAA
1152/* radeon_accelfuncs.c */
1153extern void RADEONAccelInitCP(ScreenPtr pScreen, XAAInfoRecPtr a);
1154#  endif
1155
1156#define RADEONCP_START(pScrn, info)					\
1157do {									\
1158    int _ret = drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_START);	\
1159    if (_ret) {								\
1160	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,				\
1161		   "%s: CP start %d\n", __FUNCTION__, _ret);		\
1162    }									\
1163    info->cp->CPStarted = TRUE;                                         \
1164} while (0)
1165
1166#define RADEONCP_RELEASE(pScrn, info)					\
1167do {									\
1168    if (info->cp->CPInUse) {						\
1169	RADEON_PURGE_CACHE();						\
1170	RADEON_WAIT_UNTIL_IDLE();					\
1171	RADEONCPReleaseIndirect(pScrn);					\
1172	info->cp->CPInUse = FALSE;				        \
1173    }									\
1174} while (0)
1175
1176#define RADEONCP_STOP(pScrn, info)					\
1177do {									\
1178    int _ret;								\
1179    if (info->cp->CPStarted) {						\
1180        _ret = RADEONCPStop(pScrn, info);				\
1181        if (_ret) {							\
1182	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR,			\
1183		   "%s: CP stop %d\n", __FUNCTION__, _ret);		\
1184        }								\
1185        info->cp->CPStarted = FALSE;                                    \
1186    }									\
1187    if (info->ChipFamily < CHIP_FAMILY_R600)                            \
1188        RADEONEngineRestore(pScrn);					\
1189    info->cp->CPRuns = FALSE;						\
1190} while (0)
1191
1192#define RADEONCP_RESET(pScrn, info)					\
1193do {									\
1194	int _ret = drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_RESET);	\
1195	if (_ret) {							\
1196	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR,			\
1197		       "%s: CP reset %d\n", __FUNCTION__, _ret);	\
1198	}								\
1199} while (0)
1200
1201#define RADEONCP_REFRESH(pScrn, info)					\
1202do {									\
1203    if (!info->cp->CPInUse) {						\
1204	if (info->cp->needCacheFlush) {					\
1205	    RADEON_PURGE_CACHE();					\
1206	    RADEON_PURGE_ZCACHE();					\
1207	    info->cp->needCacheFlush = FALSE;				\
1208	}								\
1209	RADEON_WAIT_UNTIL_IDLE();					\
1210	info->cp->CPInUse = TRUE;					\
1211    }									\
1212} while (0)
1213
1214
1215#define CP_PACKET0(reg, n)						\
1216	(RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1217#define CP_PACKET1(reg0, reg1)						\
1218	(RADEON_CP_PACKET1 | (((reg1) >> 2) << 11) | ((reg0) >> 2))
1219#define CP_PACKET2()							\
1220	(RADEON_CP_PACKET2)
1221#define CP_PACKET3(pkt, n)						\
1222	(RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
1223
1224
1225#define RADEON_VERBOSE	0
1226
1227#define RING_LOCALS	uint32_t *__head = NULL; int __expected; int __count = 0
1228
1229#define BEGIN_RING(n) do {						\
1230    if (RADEON_VERBOSE) {						\
1231	xf86DrvMsg(pScrn->scrnIndex, X_INFO,				\
1232		   "BEGIN_RING(%d) in %s\n", (unsigned int)n, __FUNCTION__);\
1233    }									\
1234    if (++info->cp->dma_begin_count != 1) {				\
1235	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,				\
1236		   "BEGIN_RING without end at %s:%d\n",			\
1237		   info->cp->dma_debug_func, info->cp->dma_debug_lineno);	\
1238	info->cp->dma_begin_count = 1;					\
1239    }									\
1240    info->cp->dma_debug_func = __FILE__;				\
1241    info->cp->dma_debug_lineno = __LINE__;				\
1242    if (!info->cp->indirectBuffer) {					\
1243	info->cp->indirectBuffer = RADEONCPGetBuffer(pScrn);		\
1244	info->cp->indirectStart = 0;					\
1245    } else if (info->cp->indirectBuffer->used + (n) * (int)sizeof(uint32_t) >	\
1246	       info->cp->indirectBuffer->total) {		        \
1247	RADEONCPFlushIndirect(pScrn, 1);				\
1248    }									\
1249    __expected = n;							\
1250    __head = (pointer)((char *)info->cp->indirectBuffer->address +	\
1251		       info->cp->indirectBuffer->used);			\
1252    __count = 0;							\
1253} while (0)
1254
1255#define ADVANCE_RING() do {						\
1256    if (info->cp->dma_begin_count-- != 1) {				\
1257	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,				\
1258		   "ADVANCE_RING without begin at %s:%d\n",		\
1259		   __FILE__, __LINE__);					\
1260	info->cp->dma_begin_count = 0;					\
1261    }									\
1262    if (__count != __expected) {					\
1263	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,				\
1264		   "ADVANCE_RING count != expected (%d vs %d) at %s:%d\n", \
1265		   __count, __expected, __FILE__, __LINE__);		\
1266    }									\
1267    if (RADEON_VERBOSE) {						\
1268	xf86DrvMsg(pScrn->scrnIndex, X_INFO,				\
1269		   "ADVANCE_RING() start: %d used: %d count: %d\n",	\
1270		   info->cp->indirectStart,				\
1271		   info->cp->indirectBuffer->used,			\
1272		   __count * (int)sizeof(uint32_t));			\
1273    }									\
1274    info->cp->indirectBuffer->used += __count * (int)sizeof(uint32_t);	\
1275} while (0)
1276
1277#define OUT_RING(x) do {						\
1278    if (RADEON_VERBOSE) {						\
1279	xf86DrvMsg(pScrn->scrnIndex, X_INFO,				\
1280		   "   OUT_RING(0x%08x)\n", (unsigned int)(x));		\
1281    }									\
1282    __head[__count++] = (x);						\
1283} while (0)
1284
1285#define OUT_RING_REG(reg, val)						\
1286do {									\
1287    OUT_RING(CP_PACKET0(reg, 0));					\
1288    OUT_RING(val);							\
1289} while (0)
1290
1291#define FLUSH_RING()							\
1292do {									\
1293    if (RADEON_VERBOSE)							\
1294	xf86DrvMsg(pScrn->scrnIndex, X_INFO,				\
1295		   "FLUSH_RING in %s\n", __FUNCTION__);			\
1296    if (info->cp->indirectBuffer)					\
1297	RADEONCPFlushIndirect(pScrn, 0);				\
1298} while (0)
1299
1300
1301#define RADEON_WAIT_UNTIL_2D_IDLE()					\
1302do {									\
1303    if (info->ChipFamily < CHIP_FAMILY_R600) {                          \
1304	BEGIN_RING(2);                                                  \
1305	OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));                     \
1306	OUT_RING((RADEON_WAIT_2D_IDLECLEAN |                            \
1307		  RADEON_WAIT_HOST_IDLECLEAN));                         \
1308	ADVANCE_RING();                                                 \
1309    }                                                                   \
1310} while (0)
1311
1312#define RADEON_WAIT_UNTIL_3D_IDLE()					\
1313do {									\
1314    if (info->ChipFamily < CHIP_FAMILY_R600) {				\
1315	BEGIN_RING(2);							\
1316	OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));                     \
1317	OUT_RING((RADEON_WAIT_3D_IDLECLEAN |                            \
1318		  RADEON_WAIT_HOST_IDLECLEAN));                         \
1319	ADVANCE_RING();							\
1320    }                                                                   \
1321} while (0)
1322
1323#define RADEON_WAIT_UNTIL_IDLE()					\
1324do {									\
1325    if (RADEON_VERBOSE) {						\
1326	xf86DrvMsg(pScrn->scrnIndex, X_INFO,				\
1327		   "WAIT_UNTIL_IDLE() in %s\n", __FUNCTION__);		\
1328    }									\
1329    if (info->ChipFamily < CHIP_FAMILY_R600) {                          \
1330	BEGIN_RING(2);							\
1331	OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));                     \
1332	OUT_RING((RADEON_WAIT_2D_IDLECLEAN |                            \
1333                  RADEON_WAIT_3D_IDLECLEAN |                            \
1334		  RADEON_WAIT_HOST_IDLECLEAN));                         \
1335	ADVANCE_RING();							\
1336    }                                                                   \
1337} while (0)
1338
1339#define RADEON_PURGE_CACHE()						\
1340do {									\
1341    if (info->ChipFamily < CHIP_FAMILY_R600) {				\
1342	BEGIN_RING(2);							\
1343	if (info->ChipFamily <= CHIP_FAMILY_RV280) {			\
1344	    OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));	\
1345	    OUT_RING(RADEON_RB3D_DC_FLUSH_ALL);				\
1346	} else {							\
1347	    OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));	\
1348	    OUT_RING(R300_RB3D_DC_FLUSH_ALL);				\
1349	}								\
1350	ADVANCE_RING();							\
1351    }									\
1352} while (0)
1353
1354#define RADEON_PURGE_ZCACHE()						\
1355do {									\
1356    if (info->ChipFamily < CHIP_FAMILY_R600) {                          \
1357	BEGIN_RING(2);                                                  \
1358	if (info->ChipFamily <= CHIP_FAMILY_RV280) {                    \
1359	    OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));        \
1360	    OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL);                         \
1361	} else {                                                        \
1362	    OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));          \
1363	    OUT_RING(R300_ZC_FLUSH_ALL);                                \
1364	}                                                               \
1365	ADVANCE_RING();                                                 \
1366    }                                                                   \
1367} while (0)
1368
1369#endif /* XF86DRI */
1370
1371#if defined(XF86DRI) && defined(USE_EXA)
1372#define RADEON_SWITCH_TO_2D()						\
1373do {									\
1374	uint32_t flush = 0;                                             \
1375	switch (info->accel_state->engineMode) {			\
1376	case EXA_ENGINEMODE_UNKNOWN:					\
1377	case EXA_ENGINEMODE_3D:						\
1378	    flush = 1;                                                  \
1379	case EXA_ENGINEMODE_2D:						\
1380	    break;							\
1381	}								\
1382	if (flush && info->directRenderingEnabled)                      \
1383	    RADEONCPFlushIndirect(pScrn, 1);                            \
1384        info->accel_state->engineMode = EXA_ENGINEMODE_2D;              \
1385} while (0);
1386
1387#define RADEON_SWITCH_TO_3D()						\
1388do {									\
1389	uint32_t flush = 0;						\
1390	switch (info->accel_state->engineMode) {			\
1391	case EXA_ENGINEMODE_UNKNOWN:					\
1392	case EXA_ENGINEMODE_2D:						\
1393	    flush = 1;                                                  \
1394	case EXA_ENGINEMODE_3D:						\
1395	    break;							\
1396	}								\
1397	if (flush) {							\
1398	    if (info->directRenderingEnabled)				\
1399	        RADEONCPFlushIndirect(pScrn, 1);                        \
1400	    RADEONInit3DEngine(pScrn);                                  \
1401	}                                                               \
1402        info->accel_state->engineMode = EXA_ENGINEMODE_3D;              \
1403} while (0);
1404#else
1405#define RADEON_SWITCH_TO_2D()
1406#define RADEON_SWITCH_TO_3D()
1407#endif
1408
1409static __inline__ void RADEON_MARK_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn)
1410{
1411#ifdef USE_EXA
1412    if (info->useEXA)
1413	exaMarkSync(pScrn->pScreen);
1414#endif
1415#ifdef USE_XAA
1416    if (!info->useEXA)
1417	SET_SYNC_FLAG(info->accel_state->accel);
1418#endif
1419}
1420
1421static __inline__ void RADEON_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn)
1422{
1423#ifdef USE_EXA
1424    if (info->useEXA && pScrn->pScreen)
1425	exaWaitSync(pScrn->pScreen);
1426#endif
1427#ifdef USE_XAA
1428    if (!info->useEXA && info->accel_state->accel)
1429	info->accel_state->accel->Sync(pScrn);
1430#endif
1431}
1432
1433static __inline__ void radeon_init_timeout(struct timeval *endtime,
1434    unsigned int timeout)
1435{
1436    gettimeofday(endtime, NULL);
1437    endtime->tv_usec += timeout;
1438    endtime->tv_sec += endtime->tv_usec / 1000000;
1439    endtime->tv_usec %= 1000000;
1440}
1441
1442static __inline__ int radeon_timedout(const struct timeval *endtime)
1443{
1444    struct timeval now;
1445    gettimeofday(&now, NULL);
1446    return now.tv_sec == endtime->tv_sec ?
1447        now.tv_usec > endtime->tv_usec : now.tv_sec > endtime->tv_sec;
1448}
1449
1450#endif /* _RADEON_H_ */
1451