radeon_bios.c revision 2f39173d
1/* 2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario 3 * 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining 7 * a copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation on the rights to use, copy, modify, merge, 10 * publish, distribute, sublicense, and/or sell copies of the Software, 11 * and to permit persons to whom the Software is furnished to do so, 12 * subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial 16 * portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 21 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 22 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 * DEALINGS IN THE SOFTWARE. 26 */ 27 28#ifdef HAVE_CONFIG_H 29#include "config.h" 30#endif 31 32#include <string.h> 33 34#include "xf86.h" 35#include "xf86_OSproc.h" 36 37#include "xf86PciInfo.h" 38#include "radeon.h" 39#include "radeon_reg.h" 40#include "radeon_macros.h" 41#include "radeon_probe.h" 42#include "radeon_atombios.h" 43#include "vbe.h" 44 45typedef enum 46{ 47 DDC_NONE_DETECTED, 48 DDC_MONID, 49 DDC_DVI, 50 DDC_VGA, 51 DDC_CRT2, 52 DDC_LCD, 53 DDC_GPIO, 54} RADEONLegacyDDCType; 55 56typedef enum 57{ 58 CONNECTOR_NONE_LEGACY, 59 CONNECTOR_PROPRIETARY_LEGACY, 60 CONNECTOR_CRT_LEGACY, 61 CONNECTOR_DVI_I_LEGACY, 62 CONNECTOR_DVI_D_LEGACY, 63 CONNECTOR_CTV_LEGACY, 64 CONNECTOR_STV_LEGACY, 65 CONNECTOR_UNSUPPORTED_LEGACY 66} RADEONLegacyConnectorType; 67 68static Bool 69radeon_read_bios(ScrnInfoPtr pScrn) 70{ 71 RADEONInfoPtr info = RADEONPTR(pScrn); 72 73#ifdef XSERVER_LIBPCIACCESS 74 if (pci_device_read_rom(info->PciInfo, info->VBIOS)) { 75 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 76 "Failed to read PCI ROM!\n"); 77 return FALSE; 78 } 79#else 80 xf86ReadPciBIOS(0, info->PciTag, 0, info->VBIOS, RADEON_VBIOS_SIZE); 81 if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) { 82 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 83 "Video BIOS not detected in PCI space!\n"); 84 if (xf86IsEntityPrimary(info->pEnt->index)) { 85 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 86 "Attempting to read Video BIOS from " 87 "legacy ISA space!\n"); 88 info->BIOSAddr = 0x000c0000; 89 xf86ReadDomainMemory(info->PciTag, info->BIOSAddr, 90 RADEON_VBIOS_SIZE, info->VBIOS); 91 } 92 } 93#endif 94 if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) 95 return FALSE; 96 else 97 return TRUE; 98} 99 100static Bool 101radeon_read_disabled_bios(ScrnInfoPtr pScrn) 102{ 103 RADEONInfoPtr info = RADEONPTR(pScrn); 104 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 105 unsigned char *RADEONMMIO = info->MMIO; 106 Bool ret; 107 108 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Attempting to read un-POSTed bios\n"); 109 110 if (info->ChipFamily >= CHIP_FAMILY_RV770) { 111 uint32_t viph_control = INREG(RADEON_VIPH_CONTROL); 112 uint32_t bus_cntl = INREG(RADEON_BUS_CNTL); 113 uint32_t d1vga_control = INREG(AVIVO_D1VGA_CONTROL); 114 uint32_t d2vga_control = INREG(AVIVO_D2VGA_CONTROL); 115 uint32_t vga_render_control = INREG(AVIVO_VGA_RENDER_CONTROL); 116 uint32_t rom_cntl = INREG(R600_ROM_CNTL); 117 uint32_t cg_spll_func_cntl = 0; 118 uint32_t cg_spll_status; 119 120 /* disable VIP */ 121 OUTREG(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 122 123 /* enable the rom */ 124 OUTREG(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 125 126 /* Disable VGA mode */ 127 OUTREG(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 128 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 129 OUTREG(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 130 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 131 OUTREG(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 132 133 if (info->ChipFamily == CHIP_FAMILY_RV730) { 134 cg_spll_func_cntl = INREG(R600_CG_SPLL_FUNC_CNTL); 135 136 /* enable bypass mode */ 137 OUTREG(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | R600_SPLL_BYPASS_EN)); 138 139 /* wait for SPLL_CHG_STATUS to change to 1 */ 140 cg_spll_status = 0; 141 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 142 cg_spll_status = INREG(R600_CG_SPLL_STATUS); 143 144 OUTREG(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); 145 } else 146 OUTREG(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 147 148 ret = radeon_read_bios(pScrn); 149 150 /* restore regs */ 151 if (info->ChipFamily == CHIP_FAMILY_RV730) { 152 OUTREG(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); 153 154 /* wait for SPLL_CHG_STATUS to change to 1 */ 155 cg_spll_status = 0; 156 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 157 cg_spll_status = INREG(R600_CG_SPLL_STATUS); 158 } 159 OUTREG(RADEON_VIPH_CONTROL, viph_control); 160 OUTREG(RADEON_BUS_CNTL, bus_cntl); 161 OUTREG(AVIVO_D1VGA_CONTROL, d1vga_control); 162 OUTREG(AVIVO_D2VGA_CONTROL, d2vga_control); 163 OUTREG(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 164 OUTREG(R600_ROM_CNTL, rom_cntl); 165 } else if (info->ChipFamily >= CHIP_FAMILY_R600) { 166 uint32_t viph_control = INREG(RADEON_VIPH_CONTROL); 167 uint32_t bus_cntl = INREG(RADEON_BUS_CNTL); 168 uint32_t d1vga_control = INREG(AVIVO_D1VGA_CONTROL); 169 uint32_t d2vga_control = INREG(AVIVO_D2VGA_CONTROL); 170 uint32_t vga_render_control = INREG(AVIVO_VGA_RENDER_CONTROL); 171 uint32_t rom_cntl = INREG(R600_ROM_CNTL); 172 uint32_t general_pwrmgt = INREG(R600_GENERAL_PWRMGT); 173 uint32_t low_vid_lower_gpio_cntl = INREG(R600_LOW_VID_LOWER_GPIO_CNTL); 174 uint32_t medium_vid_lower_gpio_cntl = INREG(R600_MEDIUM_VID_LOWER_GPIO_CNTL); 175 uint32_t high_vid_lower_gpio_cntl = INREG(R600_HIGH_VID_LOWER_GPIO_CNTL); 176 uint32_t ctxsw_vid_lower_gpio_cntl = INREG(R600_CTXSW_VID_LOWER_GPIO_CNTL); 177 uint32_t lower_gpio_enable = INREG(R600_LOWER_GPIO_ENABLE); 178 179 /* disable VIP */ 180 OUTREG(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 181 182 /* enable the rom */ 183 OUTREG(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 184 185 /* Disable VGA mode */ 186 OUTREG(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 187 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 188 OUTREG(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 189 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 190 OUTREG(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 191 192 OUTREG(R600_ROM_CNTL, ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | 193 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | 194 R600_SCK_OVERWRITE)); 195 196 OUTREG(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 197 198 OUTREG(R600_LOW_VID_LOWER_GPIO_CNTL, (low_vid_lower_gpio_cntl & ~0x400)); 199 200 OUTREG(R600_MEDIUM_VID_LOWER_GPIO_CNTL, (medium_vid_lower_gpio_cntl & ~0x400)); 201 202 OUTREG(R600_HIGH_VID_LOWER_GPIO_CNTL, (high_vid_lower_gpio_cntl & ~0x400)); 203 204 OUTREG(R600_CTXSW_VID_LOWER_GPIO_CNTL, (ctxsw_vid_lower_gpio_cntl & ~0x400)); 205 206 OUTREG(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); 207 208 ret = radeon_read_bios(pScrn); 209 210 /* restore regs */ 211 OUTREG(RADEON_VIPH_CONTROL, viph_control); 212 OUTREG(RADEON_BUS_CNTL, bus_cntl); 213 OUTREG(AVIVO_D1VGA_CONTROL, d1vga_control); 214 OUTREG(AVIVO_D2VGA_CONTROL, d2vga_control); 215 OUTREG(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 216 OUTREG(R600_ROM_CNTL, rom_cntl); 217 OUTREG(R600_GENERAL_PWRMGT, general_pwrmgt); 218 OUTREG(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); 219 OUTREG(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); 220 OUTREG(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); 221 OUTREG(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); 222 OUTREG(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 223 224 } else if (info->ChipFamily >= CHIP_FAMILY_RV515) { 225 uint32_t seprom_cntl1 = INREG(RADEON_SEPROM_CNTL1); 226 uint32_t viph_control = INREG(RADEON_VIPH_CONTROL); 227 uint32_t bus_cntl = INREG(RADEON_BUS_CNTL); 228 uint32_t d1vga_control = INREG(AVIVO_D1VGA_CONTROL); 229 uint32_t d2vga_control = INREG(AVIVO_D2VGA_CONTROL); 230 uint32_t vga_render_control = INREG(AVIVO_VGA_RENDER_CONTROL); 231 uint32_t gpiopad_a = INREG(RADEON_GPIOPAD_A); 232 uint32_t gpiopad_en = INREG(RADEON_GPIOPAD_EN); 233 uint32_t gpiopad_mask = INREG(RADEON_GPIOPAD_MASK); 234 235 OUTREG(RADEON_SEPROM_CNTL1, ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 236 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 237 238 OUTREG(RADEON_GPIOPAD_A, 0); 239 OUTREG(RADEON_GPIOPAD_EN, 0); 240 OUTREG(RADEON_GPIOPAD_MASK, 0); 241 242 /* disable VIP */ 243 OUTREG(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 244 245 /* enable the rom */ 246 OUTREG(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 247 248 /* Disable VGA mode */ 249 OUTREG(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 250 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 251 OUTREG(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 252 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 253 OUTREG(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 254 255 ret = radeon_read_bios(pScrn); 256 257 /* restore regs */ 258 OUTREG(RADEON_SEPROM_CNTL1, seprom_cntl1); 259 OUTREG(RADEON_VIPH_CONTROL, viph_control); 260 OUTREG(RADEON_BUS_CNTL, bus_cntl); 261 OUTREG(AVIVO_D1VGA_CONTROL, d1vga_control); 262 OUTREG(AVIVO_D2VGA_CONTROL, d2vga_control); 263 OUTREG(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 264 OUTREG(RADEON_GPIOPAD_A, gpiopad_a); 265 OUTREG(RADEON_GPIOPAD_EN, gpiopad_en); 266 OUTREG(RADEON_GPIOPAD_MASK, gpiopad_mask); 267 268 } else { 269 uint32_t seprom_cntl1 = INREG(RADEON_SEPROM_CNTL1); 270 uint32_t viph_control = INREG(RADEON_VIPH_CONTROL); 271 uint32_t bus_cntl = INREG(RADEON_BUS_CNTL); 272 uint32_t crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); 273 uint32_t crtc2_gen_cntl = 0; 274 uint32_t crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL); 275 uint32_t fp2_gen_cntl = 0; 276 277 if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) 278 fp2_gen_cntl = INREG(RADEON_FP2_GEN_CNTL); 279 280 if (pRADEONEnt->HasCRTC2) 281 crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); 282 283 OUTREG(RADEON_SEPROM_CNTL1, ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 284 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 285 286 /* disable VIP */ 287 OUTREG(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 288 289 /* enable the rom */ 290 OUTREG(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 291 292 /* Turn off mem requests and CRTC for both controllers */ 293 OUTREG(RADEON_CRTC_GEN_CNTL, ((crtc_gen_cntl & ~RADEON_CRTC_EN) | 294 (RADEON_CRTC_DISP_REQ_EN_B | 295 RADEON_CRTC_EXT_DISP_EN))); 296 if (pRADEONEnt->HasCRTC2) 297 OUTREG(RADEON_CRTC2_GEN_CNTL, ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | 298 RADEON_CRTC2_DISP_REQ_EN_B)); 299 300 /* Turn off CRTC */ 301 OUTREG(RADEON_CRTC_EXT_CNTL, ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | 302 (RADEON_CRTC_SYNC_TRISTAT | 303 RADEON_CRTC_DISPLAY_DIS))); 304 305 if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) 306 OUTREG(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); 307 308 ret = radeon_read_bios(pScrn); 309 310 /* restore regs */ 311 OUTREG(RADEON_SEPROM_CNTL1, seprom_cntl1); 312 OUTREG(RADEON_VIPH_CONTROL, viph_control); 313 OUTREG(RADEON_BUS_CNTL, bus_cntl); 314 OUTREG(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 315 if (pRADEONEnt->HasCRTC2) 316 OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 317 OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 318 if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) 319 OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 320 } 321 return ret; 322} 323 324Bool 325radeon_card_posted(ScrnInfoPtr pScrn) 326{ 327 RADEONInfoPtr info = RADEONPTR(pScrn); 328 unsigned char *RADEONMMIO = info->MMIO; 329 uint32_t reg; 330 331 /* first check CRTCs */ 332 if (IS_AVIVO_VARIANT) { 333 reg = INREG(AVIVO_D1CRTC_CONTROL) | INREG(AVIVO_D2CRTC_CONTROL); 334 if (reg & AVIVO_CRTC_EN) 335 return TRUE; 336 } else { 337 reg = INREG(RADEON_CRTC_GEN_CNTL) | INREG(RADEON_CRTC2_GEN_CNTL); 338 if (reg & RADEON_CRTC_EN) 339 return TRUE; 340 } 341 342 /* then check MEM_SIZE, in case something turned the crtcs off */ 343 if (info->ChipFamily >= CHIP_FAMILY_R600) 344 reg = INREG(R600_CONFIG_MEMSIZE); 345 else 346 reg = INREG(RADEON_CONFIG_MEMSIZE); 347 348 if (reg) 349 return TRUE; 350 351 return FALSE; 352} 353 354/* Read the Video BIOS block and the FP registers (if applicable). */ 355Bool 356RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) 357{ 358 RADEONInfoPtr info = RADEONPTR(pScrn); 359 int tmp; 360 unsigned short dptr; 361 362#ifdef XSERVER_LIBPCIACCESS 363 int size = info->PciInfo->rom_size > RADEON_VBIOS_SIZE ? info->PciInfo->rom_size : RADEON_VBIOS_SIZE; 364 info->VBIOS = malloc(size); 365#else 366 info->VBIOS = malloc(RADEON_VBIOS_SIZE); 367#endif 368 if (!info->VBIOS) { 369 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 370 "Cannot allocate space for hold Video BIOS!\n"); 371 return FALSE; 372 } else { 373 if (pInt10) { 374 info->BIOSAddr = pInt10->BIOSseg << 4; 375 (void)memcpy(info->VBIOS, xf86int10Addr(pInt10, info->BIOSAddr), 376 RADEON_VBIOS_SIZE); 377 } else if (!radeon_read_bios(pScrn)) 378 (void)radeon_read_disabled_bios(pScrn); 379 } 380 381 if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) { 382 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 383 "Unrecognized BIOS signature, BIOS data will not be used\n"); 384 free (info->VBIOS); 385 info->VBIOS = NULL; 386 return FALSE; 387 } 388 389 /* Verify it's an x86 BIOS not OF firmware, copied from radeonfb */ 390 dptr = RADEON_BIOS16(0x18); 391 /* If PCI data signature is wrong assume x86 video BIOS anyway */ 392 if (RADEON_BIOS32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) { 393 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 394 "ROM PCI data signature incorrect, ignoring\n"); 395 } 396 else if (info->VBIOS[dptr + 0x14] != 0x0) { 397 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 398 "Not an x86 BIOS ROM image, BIOS data will not be used\n"); 399 free (info->VBIOS); 400 info->VBIOS = NULL; 401 return FALSE; 402 } 403 404 if (info->VBIOS) info->ROMHeaderStart = RADEON_BIOS16(0x48); 405 406 if(!info->ROMHeaderStart) { 407 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 408 "Invalid ROM pointer, BIOS data will not be used\n"); 409 free (info->VBIOS); 410 info->VBIOS = NULL; 411 return FALSE; 412 } 413 414 tmp = info->ROMHeaderStart + 4; 415 if ((RADEON_BIOS8(tmp) == 'A' && 416 RADEON_BIOS8(tmp+1) == 'T' && 417 RADEON_BIOS8(tmp+2) == 'O' && 418 RADEON_BIOS8(tmp+3) == 'M') || 419 (RADEON_BIOS8(tmp) == 'M' && 420 RADEON_BIOS8(tmp+1) == 'O' && 421 RADEON_BIOS8(tmp+2) == 'T' && 422 RADEON_BIOS8(tmp+3) == 'A')) 423 info->IsAtomBios = TRUE; 424 else 425 info->IsAtomBios = FALSE; 426 427 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s BIOS detected\n", 428 info->IsAtomBios ? "ATOM":"Legacy"); 429 430 if (info->IsAtomBios) { 431 AtomBiosArgRec atomBiosArg; 432 433 if (RHDAtomBiosFunc(pScrn->scrnIndex, NULL, ATOMBIOS_INIT, &atomBiosArg) 434 == ATOM_SUCCESS) { 435 info->atomBIOS = atomBiosArg.atomhandle; 436 } 437 438 atomBiosArg.fb.start = info->FbFreeStart; 439 atomBiosArg.fb.size = info->FbFreeSize; 440 if (RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, ATOMBIOS_ALLOCATE_FB_SCRATCH, 441 &atomBiosArg) == ATOM_SUCCESS) { 442 443 info->FbFreeStart = atomBiosArg.fb.start; 444 info->FbFreeSize = atomBiosArg.fb.size; 445 } 446 447 RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, GET_DEFAULT_ENGINE_CLOCK, 448 &atomBiosArg); 449 RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, GET_DEFAULT_MEMORY_CLOCK, 450 &atomBiosArg); 451 RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, 452 GET_MAX_PIXEL_CLOCK_PLL_OUTPUT, &atomBiosArg); 453 RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, 454 GET_MIN_PIXEL_CLOCK_PLL_OUTPUT, &atomBiosArg); 455 RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, 456 GET_MAX_PIXEL_CLOCK_PLL_INPUT, &atomBiosArg); 457 RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, 458 GET_MIN_PIXEL_CLOCK_PLL_INPUT, &atomBiosArg); 459 RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, 460 GET_MAX_PIXEL_CLK, &atomBiosArg); 461 RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, 462 GET_REF_CLOCK, &atomBiosArg); 463 464 info->MasterDataStart = RADEON_BIOS16 (info->ROMHeaderStart + 32); 465 } 466 467 /* We are a bit too quick at using this "unposted" to re-post the 468 * card. This causes some problems with VT switch on some machines, 469 * so let's work around this for now by only POSTing if none of the 470 * CRTCs are enabled 471 */ 472 if ((!radeon_card_posted(pScrn)) && info->VBIOS) { 473 if (info->IsAtomBios) { 474 if (!rhdAtomASICInit(info->atomBIOS)) 475 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 476 "%s: AsicInit failed.\n",__func__); 477 } else { 478#if 0 479 /* FIX ME */ 480 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Attempting to POST via legacy BIOS tables\n"); 481 RADEONGetBIOSInitTableOffsets(pScrn); 482 RADEONPostCardFromBIOSTables(pScrn); 483#endif 484 } 485 } 486 487 return TRUE; 488} 489 490static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn) 491{ 492 RADEONInfoPtr info = RADEONPTR (pScrn); 493 494 if (!info->VBIOS) return FALSE; 495 496 if (RADEONGetATOMConnectorInfoFromBIOSObject(pScrn)) 497 return TRUE; 498 499 if (RADEONGetATOMConnectorInfoFromBIOSConnectorTable(pScrn)) 500 return TRUE; 501 502 return FALSE; 503} 504 505static void RADEONApplyLegacyQuirks(ScrnInfoPtr pScrn, int index) 506{ 507 RADEONInfoPtr info = RADEONPTR (pScrn); 508 509 /* XPRESS DDC quirks */ 510 if ((info->ChipFamily == CHIP_FAMILY_RS400 || 511 info->ChipFamily == CHIP_FAMILY_RS480) && 512 info->BiosConnector[index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) { 513 info->BiosConnector[index].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); 514 } else if ((info->ChipFamily == CHIP_FAMILY_RS400 || 515 info->ChipFamily == CHIP_FAMILY_RS480) && 516 info->BiosConnector[index].ddc_i2c.mask_clk_reg == RADEON_GPIO_MONID) { 517 info->BiosConnector[index].ddc_i2c.valid = TRUE; 518 info->BiosConnector[index].ddc_i2c.mask_clk_mask = (0x20 << 8); 519 info->BiosConnector[index].ddc_i2c.mask_data_mask = 0x80; 520 info->BiosConnector[index].ddc_i2c.a_clk_mask = (0x20 << 8); 521 info->BiosConnector[index].ddc_i2c.a_data_mask = 0x80; 522 info->BiosConnector[index].ddc_i2c.put_clk_mask = (0x20 << 8); 523 info->BiosConnector[index].ddc_i2c.put_data_mask = 0x80; 524 info->BiosConnector[index].ddc_i2c.get_clk_mask = (0x20 << 8); 525 info->BiosConnector[index].ddc_i2c.get_data_mask = 0x80; 526 info->BiosConnector[index].ddc_i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; 527 info->BiosConnector[index].ddc_i2c.mask_data_reg = RADEON_GPIOPAD_MASK; 528 info->BiosConnector[index].ddc_i2c.a_clk_reg = RADEON_GPIOPAD_A; 529 info->BiosConnector[index].ddc_i2c.a_data_reg = RADEON_GPIOPAD_A; 530 info->BiosConnector[index].ddc_i2c.put_clk_reg = RADEON_GPIOPAD_EN; 531 info->BiosConnector[index].ddc_i2c.put_data_reg = RADEON_GPIOPAD_EN; 532 info->BiosConnector[index].ddc_i2c.get_clk_reg = RADEON_LCD_GPIO_Y_REG; 533 info->BiosConnector[index].ddc_i2c.get_data_reg = RADEON_LCD_GPIO_Y_REG; 534 } 535 536 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */ 537 if ((IS_R300_VARIANT) && 538 info->BiosConnector[index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) 539 info->BiosConnector[index].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); 540 541 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, 542 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ 543 if (info->Chipset == PCI_CHIP_RN50_515E && 544 PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1014) { 545 if (info->BiosConnector[index].ConnectorType == CONNECTOR_VGA && 546 info->BiosConnector[index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) { 547 info->BiosConnector[index].valid = FALSE; 548 } 549 } 550 551 /* X300 card with extra non-existent DVI port */ 552 if (info->Chipset == PCI_CHIP_RV370_5B60 && 553 PCI_SUB_VENDOR_ID(info->PciInfo) == 0x17af && 554 PCI_SUB_DEVICE_ID(info->PciInfo) == 0x201e && 555 index == 2) { 556 if (info->BiosConnector[index].ConnectorType == CONNECTOR_DVI_I) { 557 info->BiosConnector[index].valid = FALSE; 558 } 559 } 560 561 /* r200 card with primary dac routed to both VGA and DVI - disable load detection 562 * otherwise you end up detecing load if either port is attached 563 */ 564 if (info->Chipset == PCI_CHIP_R200_QL && 565 PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1569 && 566 PCI_SUB_DEVICE_ID(info->PciInfo) == 0x514c && 567 (info->BiosConnector[index].devices & ATOM_DEVICE_CRT1_SUPPORT)) { 568 info->BiosConnector[index].load_detection = FALSE; 569 } 570 571} 572 573static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) 574{ 575 RADEONInfoPtr info = RADEONPTR (pScrn); 576 int offset, i, entry, tmp, tmp0, tmp1; 577 RADEONLegacyDDCType DDCType; 578 RADEONLegacyConnectorType ConnectorType; 579 580 if (!info->VBIOS) return FALSE; 581 582 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x50); 583 if (offset) { 584 for (i = 0; i < 4; i++) { 585 entry = offset + 2 + i*2; 586 587 if (!RADEON_BIOS16(entry)) { 588 break; 589 } 590 info->BiosConnector[i].valid = TRUE; 591 tmp = RADEON_BIOS16(entry); 592 info->BiosConnector[i].ConnectorType = (tmp >> 12) & 0xf; 593 ConnectorType = (tmp >> 12) & 0xf; 594 switch (ConnectorType) { 595 case CONNECTOR_PROPRIETARY_LEGACY: 596 info->BiosConnector[i].ConnectorType = CONNECTOR_DVI_D; 597 if ((tmp >> 4) & 0x1) { 598 info->BiosConnector[i].devices |= ATOM_DEVICE_DFP2_SUPPORT; 599 if (!radeon_add_encoder(pScrn, 600 radeon_get_encoder_id_from_supported_device(pScrn, 601 ATOM_DEVICE_DFP2_SUPPORT, 602 0), 603 ATOM_DEVICE_DFP2_SUPPORT)) 604 return FALSE; 605 } else { 606 info->BiosConnector[i].devices |= ATOM_DEVICE_DFP1_SUPPORT; 607 if (!radeon_add_encoder(pScrn, 608 radeon_get_encoder_id_from_supported_device(pScrn, 609 ATOM_DEVICE_DFP1_SUPPORT, 610 0), 611 ATOM_DEVICE_DFP1_SUPPORT)) 612 return FALSE; 613 } 614 break; 615 case CONNECTOR_CRT_LEGACY: 616 info->BiosConnector[i].ConnectorType = CONNECTOR_VGA; 617 if (tmp & 0x1) { 618 info->BiosConnector[i].load_detection = FALSE; 619 info->BiosConnector[i].devices |= ATOM_DEVICE_CRT2_SUPPORT; 620 if (!radeon_add_encoder(pScrn, 621 radeon_get_encoder_id_from_supported_device(pScrn, 622 ATOM_DEVICE_CRT2_SUPPORT, 623 2), 624 ATOM_DEVICE_CRT2_SUPPORT)) 625 return FALSE; 626 } else { 627 info->BiosConnector[i].load_detection = TRUE; 628 info->BiosConnector[i].devices |= ATOM_DEVICE_CRT1_SUPPORT; 629 if (!radeon_add_encoder(pScrn, 630 radeon_get_encoder_id_from_supported_device(pScrn, 631 ATOM_DEVICE_CRT1_SUPPORT, 632 1), 633 ATOM_DEVICE_CRT1_SUPPORT)) 634 return FALSE; 635 } 636 break; 637 case CONNECTOR_DVI_I_LEGACY: 638 info->BiosConnector[i].ConnectorType = CONNECTOR_DVI_I; 639 if (tmp & 0x1) { 640 info->BiosConnector[i].load_detection = FALSE; 641 info->BiosConnector[i].devices |= ATOM_DEVICE_CRT2_SUPPORT; 642 if (!radeon_add_encoder(pScrn, 643 radeon_get_encoder_id_from_supported_device(pScrn, 644 ATOM_DEVICE_CRT2_SUPPORT, 645 2), 646 ATOM_DEVICE_CRT2_SUPPORT)) 647 return FALSE; 648 } else { 649 info->BiosConnector[i].load_detection = TRUE; 650 info->BiosConnector[i].devices |= ATOM_DEVICE_CRT1_SUPPORT; 651 if (!radeon_add_encoder(pScrn, 652 radeon_get_encoder_id_from_supported_device(pScrn, 653 ATOM_DEVICE_CRT1_SUPPORT, 654 1), 655 ATOM_DEVICE_CRT1_SUPPORT)) 656 return FALSE; 657 } 658 if ((tmp >> 4) & 0x1) { 659 info->BiosConnector[i].devices |= ATOM_DEVICE_DFP2_SUPPORT; 660 if (!radeon_add_encoder(pScrn, 661 radeon_get_encoder_id_from_supported_device(pScrn, 662 ATOM_DEVICE_DFP2_SUPPORT, 663 0), 664 ATOM_DEVICE_DFP2_SUPPORT)) 665 return FALSE; 666 } else { 667 info->BiosConnector[i].devices |= ATOM_DEVICE_DFP1_SUPPORT; 668 if (!radeon_add_encoder(pScrn, 669 radeon_get_encoder_id_from_supported_device(pScrn, 670 ATOM_DEVICE_DFP1_SUPPORT, 671 0), 672 ATOM_DEVICE_DFP1_SUPPORT)) 673 return FALSE; 674 } 675 break; 676 case CONNECTOR_DVI_D_LEGACY: 677 info->BiosConnector[i].ConnectorType = CONNECTOR_DVI_D; 678 if ((tmp >> 4) & 0x1) { 679 info->BiosConnector[i].devices |= ATOM_DEVICE_DFP2_SUPPORT; 680 if (!radeon_add_encoder(pScrn, 681 radeon_get_encoder_id_from_supported_device(pScrn, 682 ATOM_DEVICE_DFP2_SUPPORT, 683 0), 684 ATOM_DEVICE_DFP2_SUPPORT)) 685 return FALSE; 686 } else { 687 info->BiosConnector[i].devices |= ATOM_DEVICE_DFP1_SUPPORT; 688 if (!radeon_add_encoder(pScrn, 689 radeon_get_encoder_id_from_supported_device(pScrn, 690 ATOM_DEVICE_DFP1_SUPPORT, 691 0), 692 ATOM_DEVICE_DFP1_SUPPORT)) 693 return FALSE; 694 } 695 break; 696 case CONNECTOR_CTV_LEGACY: 697 info->BiosConnector[i].ConnectorType = CONNECTOR_CTV; 698 info->BiosConnector[i].load_detection = FALSE; 699 info->BiosConnector[i].devices = ATOM_DEVICE_TV1_SUPPORT; 700 if (!radeon_add_encoder(pScrn, 701 radeon_get_encoder_id_from_supported_device(pScrn, 702 ATOM_DEVICE_TV1_SUPPORT, 703 2), 704 ATOM_DEVICE_TV1_SUPPORT)) 705 return FALSE; 706 break; 707 case CONNECTOR_STV_LEGACY: 708 info->BiosConnector[i].ConnectorType = CONNECTOR_STV; 709 info->BiosConnector[i].load_detection = FALSE; 710 info->BiosConnector[i].devices = ATOM_DEVICE_TV1_SUPPORT; 711 if (!radeon_add_encoder(pScrn, 712 radeon_get_encoder_id_from_supported_device(pScrn, 713 ATOM_DEVICE_TV1_SUPPORT, 714 2), 715 ATOM_DEVICE_TV1_SUPPORT)) 716 return FALSE; 717 break; 718 default: 719 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown Connector Type: %d\n", ConnectorType); 720 info->BiosConnector[i].valid = FALSE; 721 break; 722 } 723 724 info->BiosConnector[i].ddc_i2c.valid = FALSE; 725 726 DDCType = (tmp >> 8) & 0xf; 727 switch (DDCType) { 728 case DDC_MONID: 729 info->BiosConnector[i].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); 730 break; 731 case DDC_DVI: 732 info->BiosConnector[i].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); 733 break; 734 case DDC_VGA: 735 info->BiosConnector[i].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); 736 break; 737 case DDC_CRT2: 738 info->BiosConnector[i].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); 739 break; 740 default: 741 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown DDC Type: %d\n", DDCType); 742 break; 743 } 744 745 RADEONApplyLegacyQuirks(pScrn, i); 746 747 } 748 } else { 749 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No Connector Info Table found!\n"); 750 751 /* old radeons and r128 didn't use connector tables you just check 752 * for LVDS, DVI, TV, etc. tables 753 */ 754 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x34); 755 if (offset) { 756 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 757 "Found DFP table, assuming DVI connector\n"); 758 info->BiosConnector[0].valid = TRUE; 759 info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I; 760 info->BiosConnector[0].load_detection = TRUE; 761 info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); 762 info->BiosConnector[0].devices = ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_DFP1_SUPPORT; 763 if (!radeon_add_encoder(pScrn, 764 radeon_get_encoder_id_from_supported_device(pScrn, 765 ATOM_DEVICE_DFP1_SUPPORT, 766 0), 767 ATOM_DEVICE_DFP1_SUPPORT)) 768 return FALSE; 769 if (!radeon_add_encoder(pScrn, 770 radeon_get_encoder_id_from_supported_device(pScrn, 771 ATOM_DEVICE_CRT1_SUPPORT, 772 1), 773 ATOM_DEVICE_CRT1_SUPPORT)) 774 return FALSE; 775 } else 776 return FALSE; 777 } 778 779 /* check LVDS table */ 780 /* IGP can be mobile or desktop so check the connectors */ 781 if (info->IsMobility || info->IsIGP) { 782 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x40); 783 if (offset) { 784 info->BiosConnector[4].valid = TRUE; 785 info->BiosConnector[4].ConnectorType = CONNECTOR_LVDS; 786 info->BiosConnector[4].ddc_i2c.valid = FALSE; 787 788 info->BiosConnector[4].devices = ATOM_DEVICE_LCD1_SUPPORT; 789 if (!radeon_add_encoder(pScrn, 790 radeon_get_encoder_id_from_supported_device(pScrn, 791 ATOM_DEVICE_LCD1_SUPPORT, 792 0), 793 ATOM_DEVICE_LCD1_SUPPORT)) 794 return FALSE; 795 796 tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x42); 797 if (tmp) { 798 tmp0 = RADEON_BIOS16(tmp + 0x15); 799 if (tmp0) { 800 tmp1 = RADEON_BIOS8(tmp0+2) & 0x07; 801 if (tmp1) { 802 DDCType = tmp1; 803 switch (DDCType) { 804 case DDC_NONE_DETECTED: 805 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "No DDC for LCD\n"); 806 break; 807 case DDC_MONID: 808 info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); 809 break; 810 case DDC_DVI: 811 info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); 812 break; 813 case DDC_VGA: 814 info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); 815 break; 816 case DDC_CRT2: 817 info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); 818 break; 819 case DDC_LCD: 820 info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_LCD_GPIO_MASK); 821 info->BiosConnector[4].ddc_i2c.mask_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 822 info->BiosConnector[4].ddc_i2c.mask_data_mask = RADEON_BIOS32(tmp0 + 0x07); 823 info->BiosConnector[4].ddc_i2c.a_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 824 info->BiosConnector[4].ddc_i2c.a_data_mask = RADEON_BIOS32(tmp0 + 0x07); 825 info->BiosConnector[4].ddc_i2c.put_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 826 info->BiosConnector[4].ddc_i2c.put_data_mask = RADEON_BIOS32(tmp0 + 0x07); 827 info->BiosConnector[4].ddc_i2c.get_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 828 info->BiosConnector[4].ddc_i2c.get_data_mask = RADEON_BIOS32(tmp0 + 0x07); 829 break; 830 case DDC_GPIO: 831 info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_MDGPIO_EN_REG); 832 info->BiosConnector[4].ddc_i2c.mask_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 833 info->BiosConnector[4].ddc_i2c.mask_data_mask = RADEON_BIOS32(tmp0 + 0x07); 834 info->BiosConnector[4].ddc_i2c.a_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 835 info->BiosConnector[4].ddc_i2c.a_data_mask = RADEON_BIOS32(tmp0 + 0x07); 836 info->BiosConnector[4].ddc_i2c.put_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 837 info->BiosConnector[4].ddc_i2c.put_data_mask = RADEON_BIOS32(tmp0 + 0x07); 838 info->BiosConnector[4].ddc_i2c.get_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 839 info->BiosConnector[4].ddc_i2c.get_data_mask = RADEON_BIOS32(tmp0 + 0x07); 840 break; 841 default: 842 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown DDC Type: %d\n", DDCType); 843 break; 844 } 845 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "LCD DDC Info Table found!\n"); 846 } 847 } 848 } else 849 info->BiosConnector[4].ddc_i2c.valid = FALSE; 850 } 851 } 852 853 /* check TV table */ 854 if (info->InternalTVOut) { 855 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x32); 856 if (offset) { 857 if (RADEON_BIOS8(offset + 6) == 'T') { 858 info->BiosConnector[5].valid = TRUE; 859 /* assume s-video for now */ 860 info->BiosConnector[5].ConnectorType = CONNECTOR_STV; 861 info->BiosConnector[5].load_detection = FALSE; 862 info->BiosConnector[5].ddc_i2c.valid = FALSE; 863 info->BiosConnector[5].devices = ATOM_DEVICE_TV1_SUPPORT; 864 if (!radeon_add_encoder(pScrn, 865 radeon_get_encoder_id_from_supported_device(pScrn, 866 ATOM_DEVICE_TV1_SUPPORT, 867 2), 868 ATOM_DEVICE_TV1_SUPPORT)) 869 return FALSE; 870 } 871 } 872 } 873 874 return TRUE; 875} 876 877Bool RADEONGetConnectorInfoFromBIOS (ScrnInfoPtr pScrn) 878{ 879 RADEONInfoPtr info = RADEONPTR (pScrn); 880 881 if(!info->VBIOS) return FALSE; 882 883 if (info->IsAtomBios) 884 return RADEONGetATOMConnectorInfoFromBIOS(pScrn); 885 else 886 return RADEONGetLegacyConnectorInfoFromBIOS(pScrn); 887} 888 889Bool RADEONGetTVInfoFromBIOS (xf86OutputPtr output) { 890 ScrnInfoPtr pScrn = output->scrn; 891 RADEONInfoPtr info = RADEONPTR(pScrn); 892 RADEONOutputPrivatePtr radeon_output = output->driver_private; 893 radeon_tvout_ptr tvout = &radeon_output->tvout; 894 int offset, refclk, stds; 895 896 if (!info->VBIOS) return FALSE; 897 898 if (info->IsAtomBios) 899 return RADEONGetATOMTVInfo(output); 900 else { 901 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x32); 902 if (offset) { 903 if (RADEON_BIOS8(offset + 6) == 'T') { 904 switch (RADEON_BIOS8(offset + 7) & 0xf) { 905 case 1: 906 tvout->default_tvStd = TV_STD_NTSC; 907 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: NTSC\n"); 908 break; 909 case 2: 910 tvout->default_tvStd = TV_STD_PAL; 911 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: PAL\n"); 912 break; 913 case 3: 914 tvout->default_tvStd = TV_STD_PAL_M; 915 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: PAL-M\n"); 916 break; 917 case 4: 918 tvout->default_tvStd = TV_STD_PAL_60; 919 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: PAL-60\n"); 920 break; 921 case 5: 922 tvout->default_tvStd = TV_STD_NTSC_J; 923 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: NTSC-J\n"); 924 break; 925 case 6: 926 tvout->default_tvStd = TV_STD_SCART_PAL; 927 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: SCART-PAL\n"); 928 break; 929 default: 930 tvout->default_tvStd = TV_STD_NTSC; 931 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Unknown TV standard; defaulting to NTSC\n"); 932 break; 933 } 934 tvout->tvStd = tvout->default_tvStd; 935 936 refclk = (RADEON_BIOS8(offset + 9) >> 2) & 0x3; 937 if (refclk == 0) 938 tvout->TVRefClk = 29.498928713; /* MHz */ 939 else if (refclk == 1) 940 tvout->TVRefClk = 28.636360000; 941 else if (refclk == 2) 942 tvout->TVRefClk = 14.318180000; 943 else if (refclk == 3) 944 tvout->TVRefClk = 27.000000000; 945 946 tvout->SupportedTVStds = tvout->default_tvStd; 947 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TV standards supported by chip: "); 948 stds = RADEON_BIOS8(offset + 10) & 0x1f; 949 if (stds & TV_STD_NTSC) { 950 tvout->SupportedTVStds |= TV_STD_NTSC; 951 ErrorF("NTSC "); 952 } 953 if (stds & TV_STD_PAL) { 954 tvout->SupportedTVStds |= TV_STD_PAL; 955 ErrorF("PAL "); 956 } 957 if (stds & TV_STD_PAL_M) { 958 tvout->SupportedTVStds |= TV_STD_PAL_M; 959 ErrorF("PAL-M "); 960 } 961 if (stds & TV_STD_PAL_60) { 962 tvout->SupportedTVStds |= TV_STD_PAL_60; 963 ErrorF("PAL-60 "); 964 } 965 if (stds & TV_STD_NTSC_J) { 966 tvout->SupportedTVStds |= TV_STD_NTSC_J; 967 ErrorF("NTSC-J "); 968 } 969 if (stds & TV_STD_SCART_PAL) { 970 tvout->SupportedTVStds |= TV_STD_SCART_PAL; 971 ErrorF("SCART-PAL"); 972 } 973 ErrorF("\n"); 974 975 return TRUE; 976 } 977 } 978 } 979 return FALSE; 980} 981 982/* Read PLL parameters from BIOS block. Default to typical values if there 983 is no BIOS. */ 984Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn) 985{ 986 RADEONInfoPtr info = RADEONPTR (pScrn); 987 RADEONPLLPtr pll = &info->pll; 988 uint16_t pll_info_block; 989 990 if (!info->VBIOS) { 991 return FALSE; 992 } else { 993 if (info->IsAtomBios) { 994 return RADEONGetATOMClockInfo(pScrn); 995 } else { 996 int rev; 997 998 pll_info_block = RADEON_BIOS16 (info->ROMHeaderStart + 0x30); 999 1000 rev = RADEON_BIOS8(pll_info_block); 1001 1002 pll->reference_freq = RADEON_BIOS16 (pll_info_block + 0x0e); 1003 pll->reference_div = RADEON_BIOS16 (pll_info_block + 0x10); 1004 pll->pll_out_min = RADEON_BIOS32 (pll_info_block + 0x12); 1005 pll->pll_out_max = RADEON_BIOS32 (pll_info_block + 0x16); 1006 1007 if (rev > 9) { 1008 pll->pll_in_min = RADEON_BIOS32(pll_info_block + 0x36); 1009 pll->pll_in_max = RADEON_BIOS32(pll_info_block + 0x3a); 1010 } else { 1011 pll->pll_in_min = 40; 1012 pll->pll_in_max = 500; 1013 } 1014 1015 pll->xclk = RADEON_BIOS16(pll_info_block + 0x08); 1016 1017 info->sclk = RADEON_BIOS16(pll_info_block + 10) / 100.0; 1018 info->mclk = RADEON_BIOS16(pll_info_block + 8) / 100.0; 1019 } 1020 1021 if (info->sclk == 0) info->sclk = 200; 1022 if (info->mclk == 0) info->mclk = 200; 1023 } 1024 1025 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "ref_freq: %d, min_out_pll: %u, " 1026 "max_out_pll: %u, min_in_pll: %u, max_in_pll: %u, xclk: %d, " 1027 "sclk: %f, mclk: %f\n", 1028 pll->reference_freq, (unsigned)pll->pll_out_min, 1029 (unsigned)pll->pll_out_max, (unsigned)pll->pll_in_min, 1030 (unsigned)pll->pll_in_max, pll->xclk, info->sclk, info->mclk); 1031 1032 return TRUE; 1033} 1034 1035Bool RADEONGetDAC2InfoFromBIOS (ScrnInfoPtr pScrn, radeon_tvdac_ptr tvdac) 1036{ 1037 RADEONInfoPtr info = RADEONPTR(pScrn); 1038 int offset, rev, bg, dac; 1039 1040 if (!info->VBIOS) return FALSE; 1041 1042 if (xf86ReturnOptValBool(info->Options, OPTION_DEFAULT_TVDAC_ADJ, FALSE)) 1043 return FALSE; 1044 1045 if (info->IsAtomBios) { 1046 /* not implemented yet */ 1047 return FALSE; 1048 } else { 1049 /* first check TV table */ 1050 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x32); 1051 if (offset) { 1052 rev = RADEON_BIOS8(offset + 0x3); 1053 if (rev > 4) { 1054 bg = RADEON_BIOS8(offset + 0xc) & 0xf; 1055 dac = RADEON_BIOS8(offset + 0xd) & 0xf; 1056 tvdac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1057 1058 bg = RADEON_BIOS8(offset + 0xe) & 0xf; 1059 dac = RADEON_BIOS8(offset + 0xf) & 0xf; 1060 tvdac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1061 1062 bg = RADEON_BIOS8(offset + 0x10) & 0xf; 1063 dac = RADEON_BIOS8(offset + 0x11) & 0xf; 1064 tvdac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1065 1066 return TRUE; 1067 } else if (rev > 1) { 1068 bg = RADEON_BIOS8(offset + 0xc) & 0xf; 1069 dac = (RADEON_BIOS8(offset + 0xc) >> 4) & 0xf; 1070 tvdac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1071 1072 bg = RADEON_BIOS8(offset + 0xd) & 0xf; 1073 dac = (RADEON_BIOS8(offset + 0xd) >> 4) & 0xf; 1074 tvdac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1075 1076 bg = RADEON_BIOS8(offset + 0xe) & 0xf; 1077 dac = (RADEON_BIOS8(offset + 0xe) >> 4) & 0xf; 1078 tvdac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1079 1080 return TRUE; 1081 } 1082 } 1083 /* then check CRT table */ 1084 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x60); 1085 if (offset) { 1086 rev = RADEON_BIOS8(offset) & 0x3; 1087 if (rev < 2) { 1088 bg = RADEON_BIOS8(offset + 0x3) & 0xf; 1089 dac = (RADEON_BIOS8(offset + 0x3) >> 4) & 0xf; 1090 tvdac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1091 tvdac->pal_tvdac_adj = tvdac->ps2_tvdac_adj; 1092 tvdac->ntsc_tvdac_adj = tvdac->ps2_tvdac_adj; 1093 1094 return TRUE; 1095 } else { 1096 bg = RADEON_BIOS8(offset + 0x4) & 0xf; 1097 dac = RADEON_BIOS8(offset + 0x5) & 0xf; 1098 tvdac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1099 tvdac->pal_tvdac_adj = tvdac->ps2_tvdac_adj; 1100 tvdac->ntsc_tvdac_adj = tvdac->ps2_tvdac_adj; 1101 1102 return TRUE; 1103 } 1104 } 1105 } 1106 1107 return FALSE; 1108} 1109 1110Bool 1111RADEONGetLVDSInfoFromBIOS(ScrnInfoPtr pScrn, radeon_lvds_ptr lvds) 1112{ 1113 RADEONInfoPtr info = RADEONPTR(pScrn); 1114 radeon_native_mode_ptr native_mode = &lvds->native_mode; 1115 unsigned long tmp, i; 1116 1117 if (!info->VBIOS) 1118 return FALSE; 1119 1120 if (!info->IsAtomBios) { 1121 tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x40); 1122 1123 if (!tmp) { 1124 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1125 "No Panel Info Table found in BIOS!\n"); 1126 return FALSE; 1127 } else { 1128 char stmp[30]; 1129 int tmp0; 1130 1131 for (i = 0; i < 24; i++) 1132 stmp[i] = RADEON_BIOS8(tmp+i+1); 1133 stmp[24] = 0; 1134 1135 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1136 "Panel ID string: %s\n", stmp); 1137 1138 native_mode->PanelXRes = RADEON_BIOS16(tmp+25); 1139 native_mode->PanelYRes = RADEON_BIOS16(tmp+27); 1140 xf86DrvMsg(0, X_INFO, "Panel Size from BIOS: %dx%d\n", 1141 native_mode->PanelXRes, native_mode->PanelYRes); 1142 1143 lvds->PanelPwrDly = RADEON_BIOS16(tmp+44); 1144 if (lvds->PanelPwrDly > 2000 || lvds->PanelPwrDly < 0) 1145 lvds->PanelPwrDly = 2000; 1146 1147 /* some panels only work well with certain divider combinations. 1148 */ 1149 info->RefDivider = RADEON_BIOS16(tmp+46); 1150 info->PostDivider = RADEON_BIOS8(tmp+48); 1151 info->FeedbackDivider = RADEON_BIOS16(tmp+49); 1152 if ((info->RefDivider != 0) && 1153 (info->FeedbackDivider > 3)) { 1154 info->UseBiosDividers = TRUE; 1155 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1156 "BIOS provided dividers will be used.\n"); 1157 } 1158 1159 /* We don't use a while loop here just in case we have a corrupted BIOS image. 1160 The max number of table entries is 23 at present, but may grow in future. 1161 To ensure it works with future revisions we loop it to 32. 1162 */ 1163 for (i = 0; i < 32; i++) { 1164 tmp0 = RADEON_BIOS16(tmp+64+i*2); 1165 if (tmp0 == 0) break; 1166 if ((RADEON_BIOS16(tmp0) == native_mode->PanelXRes) && 1167 (RADEON_BIOS16(tmp0+2) == native_mode->PanelYRes)) { 1168 native_mode->HBlank = (RADEON_BIOS16(tmp0+17) - 1169 RADEON_BIOS16(tmp0+19)) * 8; 1170 native_mode->HOverPlus = (RADEON_BIOS16(tmp0+21) - 1171 RADEON_BIOS16(tmp0+19) - 1) * 8; 1172 native_mode->HSyncWidth = RADEON_BIOS8(tmp0+23) * 8; 1173 native_mode->VBlank = (RADEON_BIOS16(tmp0+24) - 1174 RADEON_BIOS16(tmp0+26)); 1175 native_mode->VOverPlus = ((RADEON_BIOS16(tmp0+28) & 0x7ff) - 1176 RADEON_BIOS16(tmp0+26)); 1177 native_mode->VSyncWidth = ((RADEON_BIOS16(tmp0+28) & 0xf800) >> 11); 1178 native_mode->DotClock = RADEON_BIOS16(tmp0+9) * 10; 1179 native_mode->Flags = 0; 1180 } 1181 } 1182 } 1183 1184 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1185 "LVDS Info:\n" 1186 "XRes: %d, YRes: %d, DotClock: %d\n" 1187 "HBlank: %d, HOverPlus: %d, HSyncWidth: %d\n" 1188 "VBlank: %d, VOverPlus: %d, VSyncWidth: %d\n", 1189 native_mode->PanelXRes, native_mode->PanelYRes, native_mode->DotClock, 1190 native_mode->HBlank, native_mode->HOverPlus, native_mode->HSyncWidth, 1191 native_mode->VBlank, native_mode->VOverPlus, native_mode->VSyncWidth); 1192 1193 return TRUE; 1194 } 1195 return FALSE; 1196} 1197 1198xf86MonPtr RADEONGetHardCodedEDIDFromBIOS (xf86OutputPtr output) 1199{ 1200 ScrnInfoPtr pScrn = output->scrn; 1201 RADEONInfoPtr info = RADEONPTR(pScrn); 1202 unsigned long tmp; 1203 unsigned char edid[256]; 1204 xf86MonPtr mon = NULL; 1205 1206 if (!info->VBIOS) 1207 return mon; 1208 1209 if (!info->IsAtomBios) { 1210 tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x4c); 1211 if (tmp) { 1212 memcpy(edid, (unsigned char*)(info->VBIOS + tmp), 256); 1213 if (edid[1] == 0xff) 1214 mon = xf86InterpretEDID(output->scrn->scrnIndex, edid); 1215 } 1216 } 1217 1218 return mon; 1219} 1220 1221Bool RADEONGetTMDSInfoFromBIOS (ScrnInfoPtr pScrn, radeon_tmds_ptr tmds) 1222{ 1223 RADEONInfoPtr info = RADEONPTR(pScrn); 1224 uint32_t tmp, maxfreq; 1225 int i, n; 1226 1227 if (!info->VBIOS) return FALSE; 1228 1229 if (info->IsAtomBios) { 1230 if((tmp = RADEON_BIOS16 (info->MasterDataStart + 18))) { 1231 1232 maxfreq = RADEON_BIOS16(tmp+4); 1233 1234 for (i=0; i<4; i++) { 1235 tmds->tmds_pll[i].freq = RADEON_BIOS16(tmp+i*6+6); 1236 /* This assumes each field in TMDS_PLL has 6 bit as in R300/R420 */ 1237 tmds->tmds_pll[i].value = ((RADEON_BIOS8(tmp+i*6+8) & 0x3f) | 1238 ((RADEON_BIOS8(tmp+i*6+10) & 0x3f)<<6) | 1239 ((RADEON_BIOS8(tmp+i*6+9) & 0xf)<<12) | 1240 ((RADEON_BIOS8(tmp+i*6+11) & 0xf)<<16)); 1241 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1242 "TMDS PLL from BIOS: %u %x\n", 1243 (unsigned)tmds->tmds_pll[i].freq, 1244 (unsigned)tmds->tmds_pll[i].value); 1245 1246 if (maxfreq == tmds->tmds_pll[i].freq) { 1247 tmds->tmds_pll[i].freq = 0xffffffff; 1248 break; 1249 } 1250 } 1251 return TRUE; 1252 } 1253 } else { 1254 1255 tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x34); 1256 if (tmp) { 1257 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1258 "DFP table revision: %d\n", RADEON_BIOS8(tmp)); 1259 if (RADEON_BIOS8(tmp) == 3) { 1260 n = RADEON_BIOS8(tmp + 5) + 1; 1261 if (n > 4) n = 4; 1262 for (i=0; i<n; i++) { 1263 tmds->tmds_pll[i].value = RADEON_BIOS32(tmp+i*10+0x08); 1264 tmds->tmds_pll[i].freq = RADEON_BIOS16(tmp+i*10+0x10); 1265 } 1266 return TRUE; 1267 } else if (RADEON_BIOS8(tmp) == 4) { 1268 int stride = 0; 1269 n = RADEON_BIOS8(tmp + 5) + 1; 1270 if (n > 4) n = 4; 1271 for (i=0; i<n; i++) { 1272 tmds->tmds_pll[i].value = RADEON_BIOS32(tmp+stride+0x08); 1273 tmds->tmds_pll[i].freq = RADEON_BIOS16(tmp+stride+0x10); 1274 if (i == 0) stride += 10; 1275 else stride += 6; 1276 } 1277 return TRUE; 1278 } 1279 } 1280 } 1281 return FALSE; 1282} 1283 1284static RADEONI2CBusRec 1285RADEONLookupI2CBlock(ScrnInfoPtr pScrn, int id) 1286{ 1287 RADEONInfoPtr info = RADEONPTR (pScrn); 1288 int offset, blocks, i; 1289 RADEONI2CBusRec i2c; 1290 1291 memset(&i2c, 0, sizeof(RADEONI2CBusRec)); 1292 i2c.valid = FALSE; 1293 1294 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x70); 1295 if (offset) { 1296 blocks = RADEON_BIOS8(offset + 2); 1297 for (i = 0; i < blocks; i++) { 1298 int i2c_id = RADEON_BIOS8(offset + 3 + (i * 5) + 0); 1299 if (id == i2c_id) { 1300 int clock_shift = RADEON_BIOS8(offset + 3 + (i * 5) + 3); 1301 int data_shift = RADEON_BIOS8(offset + 3 + (i * 5) + 4); 1302 1303 i2c.mask_clk_mask = (1 << clock_shift); 1304 i2c.mask_data_mask = (1 << data_shift); 1305 i2c.a_clk_mask = (1 << clock_shift); 1306 i2c.a_data_mask = (1 << data_shift); 1307 i2c.put_clk_mask = (1 << clock_shift); 1308 i2c.put_data_mask = (1 << data_shift); 1309 i2c.get_clk_mask = (1 << clock_shift); 1310 i2c.get_data_mask = (1 << data_shift); 1311 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; 1312 i2c.mask_data_reg = RADEON_GPIOPAD_MASK; 1313 i2c.a_clk_reg = RADEON_GPIOPAD_A; 1314 i2c.a_data_reg = RADEON_GPIOPAD_A; 1315 i2c.put_clk_reg = RADEON_GPIOPAD_EN; 1316 i2c.put_data_reg = RADEON_GPIOPAD_EN; 1317 i2c.get_clk_reg = RADEON_LCD_GPIO_Y_REG; 1318 i2c.get_data_reg = RADEON_LCD_GPIO_Y_REG; 1319 i2c.valid = TRUE; 1320 break; 1321 } 1322 } 1323 } 1324 return i2c; 1325} 1326 1327Bool RADEONGetExtTMDSInfoFromBIOS (ScrnInfoPtr pScrn, radeon_dvo_ptr dvo) 1328{ 1329 RADEONInfoPtr info = RADEONPTR(pScrn); 1330 int offset, table_start, max_freq, gpio_reg, flags; 1331 1332 if (!info->VBIOS) 1333 return FALSE; 1334 1335 if (info->IsAtomBios) 1336 return FALSE; 1337 else if (info->IsIGP) { 1338 /* RS4xx TMDS stuff is in the mobile table */ 1339 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x42); 1340 if (offset) { 1341 int rev = RADEON_BIOS8(offset); 1342 if (rev >= 6) { 1343 offset = RADEON_BIOS16(offset + 0x17); 1344 if (offset) { 1345 offset = RADEON_BIOS16(offset + 2); 1346 rev = RADEON_BIOS8(offset); 1347 if (offset && (rev > 1)) { 1348 int blocks = RADEON_BIOS8(offset + 3); 1349 int index = offset + 4; 1350 dvo->dvo_i2c.valid = FALSE; 1351 while (blocks > 0) { 1352 int id = RADEON_BIOS16(index); 1353 index += 2; 1354 switch (id >> 13) { 1355 case 0: 1356 index += 6; 1357 break; 1358 case 2: 1359 index += 10; 1360 break; 1361 case 3: 1362 index += 2; 1363 break; 1364 case 4: 1365 index += 2; 1366 break; 1367 case 6: 1368 dvo->dvo_i2c_slave_addr = 1369 RADEON_BIOS16(index) & 0xff; 1370 index += 2; 1371 dvo->dvo_i2c = 1372 RADEONLookupI2CBlock(pScrn, RADEON_BIOS8(index)); 1373 return TRUE; 1374 default: 1375 break; 1376 } 1377 blocks--; 1378 } 1379 } 1380 } 1381 } 1382 } else { 1383 dvo->dvo_i2c_slave_addr = 0x70; 1384 dvo->dvo_i2c = RADEONLookupI2CBlock(pScrn, 136); 1385 info->ext_tmds_chip = RADEON_SIL_164; 1386 } 1387 } else { 1388 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x58); 1389 if (offset) { 1390 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1391 "External TMDS Table revision: %d\n", 1392 RADEON_BIOS8(offset)); 1393 table_start = offset+4; 1394 max_freq = RADEON_BIOS16(table_start); 1395 dvo->dvo_i2c_slave_addr = RADEON_BIOS8(table_start+2); 1396 dvo->dvo_i2c.valid = FALSE; 1397 gpio_reg = RADEON_BIOS8(table_start+3); 1398 if (gpio_reg == 1) 1399 dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); 1400 else if (gpio_reg == 2) 1401 dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); 1402 else if (gpio_reg == 3) 1403 dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); 1404 else if (gpio_reg == 4) { 1405 if (IS_R300_VARIANT) 1406 dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); 1407 else 1408 dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); 1409 } else if (gpio_reg == 5) { 1410 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1411 "unsupported MM gpio_reg\n"); 1412 return FALSE; 1413 } else { 1414 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1415 "Unknown gpio reg: %d\n", gpio_reg); 1416 return FALSE; 1417 } 1418 flags = RADEON_BIOS8(table_start+5); 1419 dvo->dvo_duallink = flags & 0x01; 1420 if (dvo->dvo_duallink) { 1421 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1422 "Duallink TMDS detected\n"); 1423 } 1424 return TRUE; 1425 } 1426 } 1427 1428 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1429 "No External TMDS Table found\n"); 1430 1431 return FALSE; 1432} 1433 1434Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output) 1435{ 1436 ScrnInfoPtr pScrn = output->scrn; 1437 RADEONInfoPtr info = RADEONPTR(pScrn); 1438 unsigned char *RADEONMMIO = info->MMIO; 1439 radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); 1440 radeon_dvo_ptr dvo = NULL; 1441 int offset, index, id; 1442 uint32_t val, reg, and_mask, or_mask; 1443 1444 if (radeon_encoder == NULL) 1445 return FALSE; 1446 1447 dvo = (radeon_dvo_ptr)radeon_encoder->dev_priv; 1448 1449 if (dvo == NULL) 1450 return FALSE; 1451 1452 if (!info->VBIOS) 1453 return FALSE; 1454 1455 if (info->IsAtomBios) 1456 return FALSE; 1457 else if (info->IsIGP) { 1458 /* RS4xx TMDS stuff is in the mobile table */ 1459 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x42); 1460 if (offset) { 1461 int rev = RADEON_BIOS8(offset); 1462 if (rev >= 6) { 1463 offset = RADEON_BIOS16(offset + 0x17); 1464 if (offset) { 1465 offset = RADEON_BIOS16(offset + 2); 1466 rev = RADEON_BIOS8(offset); 1467 if (offset && (rev > 1)) { 1468 int blocks = RADEON_BIOS8(offset + 3); 1469 index = offset + 4; 1470 while (blocks > 0) { 1471 id = RADEON_BIOS16(index); 1472 index += 2; 1473 switch (id >> 13) { 1474 case 0: 1475 reg = (id & 0x1fff) * 4; 1476 val = RADEON_BIOS32(index); 1477 index += 4; 1478 ErrorF("MMIO: 0x%x 0x%x\n", 1479 (unsigned)reg, (unsigned)val); 1480 OUTREG(reg, val); 1481 break; 1482 case 2: 1483 reg = (id & 0x1fff) * 4; 1484 and_mask = RADEON_BIOS32(index); 1485 index += 4; 1486 or_mask = RADEON_BIOS32(index); 1487 index += 4; 1488 ErrorF("MMIO mask: 0x%x 0x%x 0x%x\n", 1489 (unsigned)reg, (unsigned)and_mask, (unsigned)or_mask); 1490 val = INREG(reg); 1491 val = (val & and_mask) | or_mask; 1492 OUTREG(reg, val); 1493 break; 1494 case 3: 1495 val = RADEON_BIOS16(index); 1496 index += 2; 1497 ErrorF("delay: %u\n", (unsigned)val); 1498 usleep(val); 1499 break; 1500 case 4: 1501 val = RADEON_BIOS16(index); 1502 index += 2; 1503 ErrorF("delay: %u\n", (unsigned)val * 1000); 1504 usleep(val * 1000); 1505 break; 1506 case 6: 1507 index++; 1508 reg = RADEON_BIOS8(index); 1509 index++; 1510 val = RADEON_BIOS8(index); 1511 index++; 1512 ErrorF("i2c write: 0x%x, 0x%x\n", (unsigned)reg, 1513 (unsigned)val); 1514 RADEONDVOWriteByte(dvo->DVOChip, reg, val); 1515 break; 1516 default: 1517 ErrorF("unknown id %d\n", id>>13); 1518 return FALSE; 1519 } 1520 blocks--; 1521 } 1522 return TRUE; 1523 } 1524 } 1525 } 1526 } 1527 } else { 1528 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x58); 1529 if (offset) { 1530 index = offset+10; 1531 id = RADEON_BIOS16(index); 1532 while (id != 0xffff) { 1533 index += 2; 1534 switch(id >> 13) { 1535 case 0: 1536 reg = (id & 0x1fff) * 4; 1537 val = RADEON_BIOS32(index); 1538 index += 4; 1539 ErrorF("MMIO: 0x%x 0x%x\n", 1540 (unsigned)reg, (unsigned)val); 1541 OUTREG(reg, val); 1542 break; 1543 case 2: 1544 reg = (id & 0x1fff) * 4; 1545 and_mask = RADEON_BIOS32(index); 1546 index += 4; 1547 or_mask = RADEON_BIOS32(index); 1548 index += 4; 1549 val = INREG(reg); 1550 val = (val & and_mask) | or_mask; 1551 ErrorF("MMIO mask: 0x%x 0x%x 0x%x\n", 1552 (unsigned)reg, (unsigned)and_mask, (unsigned)or_mask); 1553 OUTREG(reg, val); 1554 break; 1555 case 4: 1556 val = RADEON_BIOS16(index); 1557 index += 2; 1558 ErrorF("delay: %u\n", (unsigned)val); 1559 usleep(val); 1560 break; 1561 case 5: 1562 reg = id & 0x1fff; 1563 and_mask = RADEON_BIOS32(index); 1564 index += 4; 1565 or_mask = RADEON_BIOS32(index); 1566 index += 4; 1567 ErrorF("PLL mask: 0x%x 0x%x 0x%x\n", 1568 (unsigned)reg, (unsigned)and_mask, (unsigned)or_mask); 1569 val = INPLL(pScrn, reg); 1570 val = (val & and_mask) | or_mask; 1571 OUTPLL(pScrn, reg, val); 1572 break; 1573 case 6: 1574 reg = id & 0x1fff; 1575 val = RADEON_BIOS8(index); 1576 index += 1; 1577 ErrorF("i2c write: 0x%x, 0x%x\n", (unsigned)reg, 1578 (unsigned)val); 1579 RADEONDVOWriteByte(dvo->DVOChip, reg, val); 1580 break; 1581 default: 1582 ErrorF("unknown id %d\n", id>>13); 1583 return FALSE; 1584 }; 1585 id = RADEON_BIOS16(index); 1586 } 1587 return TRUE; 1588 } 1589 } 1590 1591 return FALSE; 1592} 1593 1594/* support for init from bios tables 1595 * 1596 * Based heavily on the netbsd radeonfb driver 1597 * Written by Garrett D'Amore 1598 * Copyright (c) 2006 Itronix Inc. 1599 * 1600 */ 1601 1602/* bios table defines */ 1603 1604#define RADEON_TABLE_ENTRY_FLAG_MASK 0xe000 1605#define RADEON_TABLE_ENTRY_INDEX_MASK 0x1fff 1606#define RADEON_TABLE_ENTRY_COMMAND_MASK 0x00ff 1607 1608#define RADEON_TABLE_FLAG_WRITE_INDEXED 0x0000 1609#define RADEON_TABLE_FLAG_WRITE_DIRECT 0x2000 1610#define RADEON_TABLE_FLAG_MASK_INDEXED 0x4000 1611#define RADEON_TABLE_FLAG_MASK_DIRECT 0x6000 1612#define RADEON_TABLE_FLAG_DELAY 0x8000 1613#define RADEON_TABLE_FLAG_SCOMMAND 0xa000 1614 1615#define RADEON_TABLE_SCOMMAND_WAIT_MC_BUSY_MASK 0x03 1616#define RADEON_TABLE_SCOMMAND_WAIT_MEM_PWRUP_COMPLETE 0x08 1617 1618#define RADEON_PLL_FLAG_MASK 0xc0 1619#define RADEON_PLL_INDEX_MASK 0x3f 1620 1621#define RADEON_PLL_FLAG_WRITE 0x00 1622#define RADEON_PLL_FLAG_MASK_BYTE 0x40 1623#define RADEON_PLL_FLAG_WAIT 0x80 1624 1625#define RADEON_PLL_WAIT_150MKS 1 1626#define RADEON_PLL_WAIT_5MS 2 1627#define RADEON_PLL_WAIT_MC_BUSY_MASK 3 1628#define RADEON_PLL_WAIT_DLL_READY_MASK 4 1629#define RADEON_PLL_WAIT_CHK_SET_CLK_PWRMGT_CNTL24 5 1630 1631static uint16_t 1632RADEONValidateBIOSOffset(ScrnInfoPtr pScrn, uint16_t offset) 1633{ 1634 RADEONInfoPtr info = RADEONPTR (pScrn); 1635 uint8_t revision = RADEON_BIOS8(offset - 1); 1636 1637 if (revision > 0x10) { 1638 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1639 "Bad revision %d for BIOS table\n", revision); 1640 return 0; 1641 } 1642 1643 if (offset < 0x60) { 1644 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1645 "Bad offset 0x%x for BIOS Table\n", offset); 1646 return 0; 1647 } 1648 1649 return offset; 1650} 1651 1652Bool 1653RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn) 1654{ 1655 RADEONInfoPtr info = RADEONPTR (pScrn); 1656 uint8_t val; 1657 1658 if (!info->VBIOS) { 1659 return FALSE; 1660 } else { 1661 if (info->IsAtomBios) { 1662 return FALSE; 1663 } else { 1664 info->BiosTable.revision = RADEON_BIOS8(info->ROMHeaderStart + 4); 1665 info->BiosTable.rr1_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x0c); 1666 if (info->BiosTable.rr1_offset) { 1667 info->BiosTable.rr1_offset = 1668 RADEONValidateBIOSOffset(pScrn, info->BiosTable.rr1_offset); 1669 } 1670 if (info->BiosTable.revision > 0x09) 1671 return TRUE; 1672 info->BiosTable.rr2_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x4e); 1673 if (info->BiosTable.rr2_offset) { 1674 info->BiosTable.rr2_offset = 1675 RADEONValidateBIOSOffset(pScrn, info->BiosTable.rr2_offset); 1676 } 1677 info->BiosTable.dyn_clk_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x52); 1678 if (info->BiosTable.dyn_clk_offset) { 1679 info->BiosTable.dyn_clk_offset = 1680 RADEONValidateBIOSOffset(pScrn, info->BiosTable.dyn_clk_offset); 1681 } 1682 info->BiosTable.pll_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x46); 1683 if (info->BiosTable.pll_offset) { 1684 info->BiosTable.pll_offset = 1685 RADEONValidateBIOSOffset(pScrn, info->BiosTable.pll_offset); 1686 } 1687 info->BiosTable.mem_config_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x48); 1688 if (info->BiosTable.mem_config_offset) { 1689 info->BiosTable.mem_config_offset = 1690 RADEONValidateBIOSOffset(pScrn, info->BiosTable.mem_config_offset); 1691 } 1692 if (info->BiosTable.mem_config_offset) { 1693 info->BiosTable.mem_reset_offset = info->BiosTable.mem_config_offset; 1694 if (info->BiosTable.mem_reset_offset) { 1695 while (RADEON_BIOS8(info->BiosTable.mem_reset_offset)) 1696 info->BiosTable.mem_reset_offset++; 1697 info->BiosTable.mem_reset_offset++; 1698 info->BiosTable.mem_reset_offset += 2; 1699 } 1700 } 1701 if (info->BiosTable.mem_config_offset) { 1702 info->BiosTable.short_mem_offset = info->BiosTable.mem_config_offset; 1703 if ((info->BiosTable.short_mem_offset != 0) && 1704 (RADEON_BIOS8(info->BiosTable.short_mem_offset - 2) <= 64)) 1705 info->BiosTable.short_mem_offset += 1706 RADEON_BIOS8(info->BiosTable.short_mem_offset - 3); 1707 } 1708 if (info->BiosTable.rr2_offset) { 1709 info->BiosTable.rr3_offset = info->BiosTable.rr2_offset; 1710 if (info->BiosTable.rr3_offset) { 1711 while ((val = RADEON_BIOS8(info->BiosTable.rr3_offset + 1)) != 0) { 1712 if (val & 0x40) 1713 info->BiosTable.rr3_offset += 10; 1714 else if (val & 0x80) 1715 info->BiosTable.rr3_offset += 4; 1716 else 1717 info->BiosTable.rr3_offset += 6; 1718 } 1719 info->BiosTable.rr3_offset += 2; 1720 } 1721 } 1722 1723 if (info->BiosTable.rr3_offset) { 1724 info->BiosTable.rr4_offset = info->BiosTable.rr3_offset; 1725 if (info->BiosTable.rr4_offset) { 1726 while ((val = RADEON_BIOS8(info->BiosTable.rr4_offset + 1)) != 0) { 1727 if (val & 0x40) 1728 info->BiosTable.rr4_offset += 10; 1729 else if (val & 0x80) 1730 info->BiosTable.rr4_offset += 4; 1731 else 1732 info->BiosTable.rr4_offset += 6; 1733 } 1734 info->BiosTable.rr4_offset += 2; 1735 } 1736 } 1737 1738 if (info->BiosTable.rr3_offset + 1 == info->BiosTable.pll_offset) { 1739 info->BiosTable.rr3_offset = 0; 1740 info->BiosTable.rr4_offset = 0; 1741 } 1742 1743 return TRUE; 1744 1745 } 1746 } 1747} 1748 1749static void 1750RADEONRestoreBIOSRegBlock(ScrnInfoPtr pScrn, uint16_t table_offset) 1751{ 1752 RADEONInfoPtr info = RADEONPTR (pScrn); 1753 unsigned char *RADEONMMIO = info->MMIO; 1754 uint16_t offset = table_offset; 1755 uint16_t value, flag, index, count; 1756 uint32_t andmask, ormask, val, channel_complete_mask; 1757 uint8_t command; 1758 1759 if (offset == 0) 1760 return; 1761 1762 while ((value = RADEON_BIOS16(offset)) != 0) { 1763 flag = value & RADEON_TABLE_ENTRY_FLAG_MASK; 1764 index = value & RADEON_TABLE_ENTRY_INDEX_MASK; 1765 command = value & RADEON_TABLE_ENTRY_COMMAND_MASK; 1766 1767 offset += 2; 1768 1769 switch (flag) { 1770 case RADEON_TABLE_FLAG_WRITE_INDEXED: 1771 val = RADEON_BIOS32(offset); 1772 ErrorF("WRITE INDEXED: 0x%x 0x%x\n", 1773 index, (unsigned)val); 1774 OUTREG(RADEON_MM_INDEX, index); 1775 OUTREG(RADEON_MM_DATA, val); 1776 offset += 4; 1777 break; 1778 1779 case RADEON_TABLE_FLAG_WRITE_DIRECT: 1780 val = RADEON_BIOS32(offset); 1781 ErrorF("WRITE DIRECT: 0x%x 0x%x\n", index, (unsigned)val); 1782 OUTREG(index, val); 1783 offset += 4; 1784 break; 1785 1786 case RADEON_TABLE_FLAG_MASK_INDEXED: 1787 andmask = RADEON_BIOS32(offset); 1788 offset += 4; 1789 ormask = RADEON_BIOS32(offset); 1790 offset += 4; 1791 ErrorF("MASK INDEXED: 0x%x 0x%x 0x%x\n", 1792 index, (unsigned)andmask, (unsigned)ormask); 1793 OUTREG(RADEON_MM_INDEX, index); 1794 val = INREG(RADEON_MM_DATA); 1795 val = (val & andmask) | ormask; 1796 OUTREG(RADEON_MM_DATA, val); 1797 break; 1798 1799 case RADEON_TABLE_FLAG_MASK_DIRECT: 1800 andmask = RADEON_BIOS32(offset); 1801 offset += 4; 1802 ormask = RADEON_BIOS32(offset); 1803 offset += 4; 1804 ErrorF("MASK DIRECT: 0x%x 0x%x 0x%x\n", 1805 index, (unsigned)andmask, (unsigned)ormask); 1806 val = INREG(index); 1807 val = (val & andmask) | ormask; 1808 OUTREG(index, val); 1809 break; 1810 1811 case RADEON_TABLE_FLAG_DELAY: 1812 count = RADEON_BIOS16(offset); 1813 ErrorF("delay: %d\n", count); 1814 usleep(count); 1815 offset += 2; 1816 break; 1817 1818 case RADEON_TABLE_FLAG_SCOMMAND: 1819 ErrorF("SCOMMAND 0x%x\n", command); 1820 switch (command) { 1821 case RADEON_TABLE_SCOMMAND_WAIT_MC_BUSY_MASK: 1822 count = RADEON_BIOS16(offset); 1823 ErrorF("SCOMMAND_WAIT_MC_BUSY_MASK %d\n", count); 1824 while (count--) { 1825 if (!(INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL) & 1826 RADEON_MC_BUSY)) 1827 break; 1828 } 1829 break; 1830 1831 case RADEON_TABLE_SCOMMAND_WAIT_MEM_PWRUP_COMPLETE: 1832 count = RADEON_BIOS16(offset); 1833 ErrorF("SCOMMAND_WAIT_MEM_PWRUP_COMPLETE %d\n", count); 1834 /* may need to take into account how many memory channels 1835 * each card has 1836 */ 1837 if (IS_R300_VARIANT) 1838 channel_complete_mask = R300_MEM_PWRUP_COMPLETE; 1839 else 1840 channel_complete_mask = RADEON_MEM_PWRUP_COMPLETE; 1841 while (count--) { 1842 /* XXX: may need indexed access */ 1843 if ((INREG(RADEON_MEM_STR_CNTL) & 1844 channel_complete_mask) == 1845 channel_complete_mask) 1846 break; 1847 } 1848 break; 1849 1850 } 1851 offset += 2; 1852 break; 1853 } 1854 } 1855} 1856 1857static void 1858RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, uint16_t table_offset) 1859{ 1860 RADEONInfoPtr info = RADEONPTR (pScrn); 1861 unsigned char *RADEONMMIO = info->MMIO; 1862 uint16_t offset = table_offset; 1863 uint16_t count; 1864 uint32_t ormask, val, channel_complete_mask; 1865 uint8_t index; 1866 1867 if (offset == 0) 1868 return; 1869 1870 while ((index = RADEON_BIOS8(offset)) != 0xff) { 1871 offset++; 1872 if (index == 0x0f) { 1873 count = 20000; 1874 ErrorF("MEM_WAIT_MEM_PWRUP_COMPLETE %d\n", count); 1875 /* may need to take into account how many memory channels 1876 * each card has 1877 */ 1878 if (IS_R300_VARIANT) 1879 channel_complete_mask = R300_MEM_PWRUP_COMPLETE; 1880 else 1881 channel_complete_mask = RADEON_MEM_PWRUP_COMPLETE; 1882 while (count--) { 1883 /* XXX: may need indexed access */ 1884 if ((INREG(RADEON_MEM_STR_CNTL) & 1885 channel_complete_mask) == 1886 channel_complete_mask) 1887 break; 1888 } 1889 } else { 1890 ormask = RADEON_BIOS16(offset); 1891 offset += 2; 1892 1893 ErrorF("INDEX RADEON_MEM_SDRAM_MODE_REG %x %x\n", 1894 RADEON_SDRAM_MODE_MASK, (unsigned)ormask); 1895 1896 /* can this use direct access? */ 1897 OUTREG(RADEON_MM_INDEX, RADEON_MEM_SDRAM_MODE_REG); 1898 val = INREG(RADEON_MM_DATA); 1899 val = (val & RADEON_SDRAM_MODE_MASK) | ormask; 1900 OUTREG(RADEON_MM_DATA, val); 1901 1902 ormask = (uint32_t)index << 24; 1903 1904 ErrorF("INDEX RADEON_MEM_SDRAM_MODE_REG %x %x\n", 1905 RADEON_B3MEM_RESET_MASK, (unsigned)ormask); 1906 1907 /* can this use direct access? */ 1908 OUTREG(RADEON_MM_INDEX, RADEON_MEM_SDRAM_MODE_REG); 1909 val = INREG(RADEON_MM_DATA); 1910 val = (val & RADEON_B3MEM_RESET_MASK) | ormask; 1911 OUTREG(RADEON_MM_DATA, val); 1912 } 1913 } 1914} 1915 1916static void 1917RADEONRestoreBIOSPllBlock(ScrnInfoPtr pScrn, uint16_t table_offset) 1918{ 1919 RADEONInfoPtr info = RADEONPTR (pScrn); 1920 uint16_t offset = table_offset; 1921 uint8_t index, shift; 1922 uint32_t andmask, ormask, val, clk_pwrmgt_cntl; 1923 uint16_t count; 1924 1925 if (offset == 0) 1926 return; 1927 1928 while ((index = RADEON_BIOS8(offset)) != 0) { 1929 offset++; 1930 1931 switch (index & RADEON_PLL_FLAG_MASK) { 1932 case RADEON_PLL_FLAG_WAIT: 1933 switch (index & RADEON_PLL_INDEX_MASK) { 1934 case RADEON_PLL_WAIT_150MKS: 1935 ErrorF("delay: 150 us\n"); 1936 usleep(150); 1937 break; 1938 case RADEON_PLL_WAIT_5MS: 1939 ErrorF("delay: 5 ms\n"); 1940 usleep(5000); 1941 break; 1942 1943 case RADEON_PLL_WAIT_MC_BUSY_MASK: 1944 count = 1000; 1945 ErrorF("PLL_WAIT_MC_BUSY_MASK %d\n", count); 1946 while (count--) { 1947 if (!(INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL) & 1948 RADEON_MC_BUSY)) 1949 break; 1950 } 1951 break; 1952 1953 case RADEON_PLL_WAIT_DLL_READY_MASK: 1954 count = 1000; 1955 ErrorF("PLL_WAIT_DLL_READY_MASK %d\n", count); 1956 while (count--) { 1957 if (INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL) & 1958 RADEON_DLL_READY) 1959 break; 1960 } 1961 break; 1962 1963 case RADEON_PLL_WAIT_CHK_SET_CLK_PWRMGT_CNTL24: 1964 ErrorF("PLL_WAIT_CHK_SET_CLK_PWRMGT_CNTL24\n"); 1965 clk_pwrmgt_cntl = INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL); 1966 if (clk_pwrmgt_cntl & RADEON_CG_NO1_DEBUG_0) { 1967 val = INPLL(pScrn, RADEON_MCLK_CNTL); 1968 /* is this right? */ 1969 val = (val & 0xFFFF0000) | 0x1111; /* seems like we should clear these... */ 1970 OUTPLL(pScrn, RADEON_MCLK_CNTL, val); 1971 usleep(10000); 1972 OUTPLL(pScrn, RADEON_CLK_PWRMGT_CNTL, 1973 clk_pwrmgt_cntl & ~RADEON_CG_NO1_DEBUG_0); 1974 usleep(10000); 1975 } 1976 break; 1977 } 1978 break; 1979 1980 case RADEON_PLL_FLAG_MASK_BYTE: 1981 shift = RADEON_BIOS8(offset) * 8; 1982 offset++; 1983 1984 andmask = 1985 (((uint32_t)RADEON_BIOS8(offset)) << shift) | 1986 ~((uint32_t)0xff << shift); 1987 offset++; 1988 1989 ormask = ((uint32_t)RADEON_BIOS8(offset)) << shift; 1990 offset++; 1991 1992 ErrorF("PLL_MASK_BYTE 0x%x 0x%x 0x%x 0x%x\n", 1993 index, shift, (unsigned)andmask, (unsigned)ormask); 1994 val = INPLL(pScrn, index); 1995 val = (val & andmask) | ormask; 1996 OUTPLL(pScrn, index, val); 1997 break; 1998 1999 case RADEON_PLL_FLAG_WRITE: 2000 val = RADEON_BIOS32(offset); 2001 ErrorF("PLL_WRITE 0x%x 0x%x\n", index, (unsigned)val); 2002 OUTPLL(pScrn, index, val); 2003 offset += 4; 2004 break; 2005 } 2006 } 2007} 2008 2009Bool 2010RADEONPostCardFromBIOSTables(ScrnInfoPtr pScrn) 2011{ 2012 RADEONInfoPtr info = RADEONPTR (pScrn); 2013 2014 if (!info->VBIOS) { 2015 return FALSE; 2016 } else { 2017 if (info->IsAtomBios) { 2018 return FALSE; 2019 } else { 2020 if (info->BiosTable.rr1_offset) { 2021 ErrorF("rr1 restore, 0x%x\n", info->BiosTable.rr1_offset); 2022 RADEONRestoreBIOSRegBlock(pScrn, info->BiosTable.rr1_offset); 2023 } 2024 if (info->BiosTable.revision < 0x09) { 2025 if (info->BiosTable.pll_offset) { 2026 ErrorF("pll restore, 0x%x\n", info->BiosTable.pll_offset); 2027 RADEONRestoreBIOSPllBlock(pScrn, info->BiosTable.pll_offset); 2028 } 2029 if (info->BiosTable.rr2_offset) { 2030 ErrorF("rr2 restore, 0x%x\n", info->BiosTable.rr2_offset); 2031 RADEONRestoreBIOSRegBlock(pScrn, info->BiosTable.rr2_offset); 2032 } 2033 if (info->BiosTable.rr4_offset) { 2034 ErrorF("rr4 restore, 0x%x\n", info->BiosTable.rr4_offset); 2035 RADEONRestoreBIOSRegBlock(pScrn, info->BiosTable.rr4_offset); 2036 } 2037 if (info->BiosTable.mem_reset_offset) { 2038 ErrorF("mem reset restore, 0x%x\n", info->BiosTable.mem_reset_offset); 2039 RADEONRestoreBIOSMemBlock(pScrn, info->BiosTable.mem_reset_offset); 2040 } 2041 if (info->BiosTable.rr3_offset) { 2042 ErrorF("rr3 restore, 0x%x\n", info->BiosTable.rr3_offset); 2043 RADEONRestoreBIOSRegBlock(pScrn, info->BiosTable.rr3_offset); 2044 } 2045 if (info->BiosTable.dyn_clk_offset) { 2046 ErrorF("dyn_clk restore, 0x%x\n", info->BiosTable.dyn_clk_offset); 2047 RADEONRestoreBIOSPllBlock(pScrn, info->BiosTable.dyn_clk_offset); 2048 } 2049 } 2050 } 2051 } 2052 return TRUE; 2053} 2054