radeon_bios.c revision ad43ddac
1/* 2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario 3 * 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining 7 * a copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation on the rights to use, copy, modify, merge, 10 * publish, distribute, sublicense, and/or sell copies of the Software, 11 * and to permit persons to whom the Software is furnished to do so, 12 * subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial 16 * portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 21 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 22 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 * DEALINGS IN THE SOFTWARE. 26 */ 27 28#ifdef HAVE_CONFIG_H 29#include "config.h" 30#endif 31 32#include <string.h> 33 34#include "xf86.h" 35#include "xf86_OSproc.h" 36 37#include "xf86PciInfo.h" 38#include "radeon.h" 39#include "radeon_reg.h" 40#include "radeon_macros.h" 41#include "radeon_probe.h" 42#include "radeon_atombios.h" 43#include "vbe.h" 44 45typedef enum 46{ 47 DDC_NONE_DETECTED, 48 DDC_MONID, 49 DDC_DVI, 50 DDC_VGA, 51 DDC_CRT2, 52 DDC_LCD, 53 DDC_GPIO, 54} RADEONLegacyDDCType; 55 56typedef enum 57{ 58 CONNECTOR_NONE_LEGACY, 59 CONNECTOR_PROPRIETARY_LEGACY, 60 CONNECTOR_CRT_LEGACY, 61 CONNECTOR_DVI_I_LEGACY, 62 CONNECTOR_DVI_D_LEGACY, 63 CONNECTOR_CTV_LEGACY, 64 CONNECTOR_STV_LEGACY, 65 CONNECTOR_UNSUPPORTED_LEGACY 66} RADEONLegacyConnectorType; 67 68static Bool 69radeon_read_bios(ScrnInfoPtr pScrn) 70{ 71 RADEONInfoPtr info = RADEONPTR(pScrn); 72 73#ifdef XSERVER_LIBPCIACCESS 74 if (pci_device_read_rom(info->PciInfo, info->VBIOS)) { 75 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 76 "Failed to read PCI ROM!\n"); 77 return FALSE; 78 } 79#else 80 xf86ReadPciBIOS(0, info->PciTag, 0, info->VBIOS, RADEON_VBIOS_SIZE); 81 if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) { 82 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 83 "Video BIOS not detected in PCI space!\n"); 84 if (xf86IsEntityPrimary(info->pEnt->index)) { 85 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 86 "Attempting to read Video BIOS from " 87 "legacy ISA space!\n"); 88 info->BIOSAddr = 0x000c0000; 89 xf86ReadDomainMemory(info->PciTag, info->BIOSAddr, 90 RADEON_VBIOS_SIZE, info->VBIOS); 91 } 92 } 93#endif 94 if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) 95 return FALSE; 96 else 97 return TRUE; 98} 99 100static Bool 101radeon_read_disabled_bios(ScrnInfoPtr pScrn) 102{ 103 RADEONInfoPtr info = RADEONPTR(pScrn); 104 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 105 unsigned char *RADEONMMIO = info->MMIO; 106 Bool ret; 107 108 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Attempting to read un-POSTed bios\n"); 109 110 if (info->ChipFamily >= CHIP_FAMILY_RV770) { 111 uint32_t viph_control = INREG(RADEON_VIPH_CONTROL); 112 uint32_t bus_cntl = INREG(RADEON_BUS_CNTL); 113 uint32_t d1vga_control = INREG(AVIVO_D1VGA_CONTROL); 114 uint32_t d2vga_control = INREG(AVIVO_D2VGA_CONTROL); 115 uint32_t vga_render_control = INREG(AVIVO_VGA_RENDER_CONTROL); 116 uint32_t rom_cntl = INREG(R600_ROM_CNTL); 117 uint32_t cg_spll_func_cntl = 0; 118 uint32_t cg_spll_status; 119 120 /* disable VIP */ 121 OUTREG(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 122 123 /* enable the rom */ 124 OUTREG(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 125 126 /* Disable VGA mode */ 127 OUTREG(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 128 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 129 OUTREG(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 130 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 131 OUTREG(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 132 133 if (info->ChipFamily == CHIP_FAMILY_RV730) { 134 cg_spll_func_cntl = INREG(R600_CG_SPLL_FUNC_CNTL); 135 136 /* enable bypass mode */ 137 OUTREG(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | R600_SPLL_BYPASS_EN)); 138 139 /* wait for SPLL_CHG_STATUS to change to 1 */ 140 cg_spll_status = 0; 141 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 142 cg_spll_status = INREG(R600_CG_SPLL_STATUS); 143 144 OUTREG(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); 145 } else 146 OUTREG(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 147 148 ret = radeon_read_bios(pScrn); 149 150 /* restore regs */ 151 if (info->ChipFamily == CHIP_FAMILY_RV730) { 152 OUTREG(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); 153 154 /* wait for SPLL_CHG_STATUS to change to 1 */ 155 cg_spll_status = 0; 156 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 157 cg_spll_status = INREG(R600_CG_SPLL_STATUS); 158 } 159 OUTREG(RADEON_VIPH_CONTROL, viph_control); 160 OUTREG(RADEON_BUS_CNTL, bus_cntl); 161 OUTREG(AVIVO_D1VGA_CONTROL, d1vga_control); 162 OUTREG(AVIVO_D2VGA_CONTROL, d2vga_control); 163 OUTREG(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 164 OUTREG(R600_ROM_CNTL, rom_cntl); 165 } else if (info->ChipFamily >= CHIP_FAMILY_R600) { 166 uint32_t viph_control = INREG(RADEON_VIPH_CONTROL); 167 uint32_t bus_cntl = INREG(RADEON_BUS_CNTL); 168 uint32_t d1vga_control = INREG(AVIVO_D1VGA_CONTROL); 169 uint32_t d2vga_control = INREG(AVIVO_D2VGA_CONTROL); 170 uint32_t vga_render_control = INREG(AVIVO_VGA_RENDER_CONTROL); 171 uint32_t rom_cntl = INREG(R600_ROM_CNTL); 172 uint32_t general_pwrmgt = INREG(R600_GENERAL_PWRMGT); 173 uint32_t low_vid_lower_gpio_cntl = INREG(R600_LOW_VID_LOWER_GPIO_CNTL); 174 uint32_t medium_vid_lower_gpio_cntl = INREG(R600_MEDIUM_VID_LOWER_GPIO_CNTL); 175 uint32_t high_vid_lower_gpio_cntl = INREG(R600_HIGH_VID_LOWER_GPIO_CNTL); 176 uint32_t ctxsw_vid_lower_gpio_cntl = INREG(R600_CTXSW_VID_LOWER_GPIO_CNTL); 177 uint32_t lower_gpio_enable = INREG(R600_LOWER_GPIO_ENABLE); 178 179 /* disable VIP */ 180 OUTREG(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 181 182 /* enable the rom */ 183 OUTREG(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 184 185 /* Disable VGA mode */ 186 OUTREG(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 187 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 188 OUTREG(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 189 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 190 OUTREG(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 191 192 OUTREG(R600_ROM_CNTL, ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | 193 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | 194 R600_SCK_OVERWRITE)); 195 196 OUTREG(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 197 198 OUTREG(R600_LOW_VID_LOWER_GPIO_CNTL, (low_vid_lower_gpio_cntl & ~0x400)); 199 200 OUTREG(R600_MEDIUM_VID_LOWER_GPIO_CNTL, (medium_vid_lower_gpio_cntl & ~0x400)); 201 202 OUTREG(R600_HIGH_VID_LOWER_GPIO_CNTL, (high_vid_lower_gpio_cntl & ~0x400)); 203 204 OUTREG(R600_CTXSW_VID_LOWER_GPIO_CNTL, (ctxsw_vid_lower_gpio_cntl & ~0x400)); 205 206 OUTREG(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); 207 208 ret = radeon_read_bios(pScrn); 209 210 /* restore regs */ 211 OUTREG(RADEON_VIPH_CONTROL, viph_control); 212 OUTREG(RADEON_BUS_CNTL, bus_cntl); 213 OUTREG(AVIVO_D1VGA_CONTROL, d1vga_control); 214 OUTREG(AVIVO_D2VGA_CONTROL, d2vga_control); 215 OUTREG(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 216 OUTREG(R600_ROM_CNTL, rom_cntl); 217 OUTREG(R600_GENERAL_PWRMGT, general_pwrmgt); 218 OUTREG(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); 219 OUTREG(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); 220 OUTREG(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); 221 OUTREG(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); 222 OUTREG(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 223 224 } else if (info->ChipFamily >= CHIP_FAMILY_RV515) { 225 uint32_t seprom_cntl1 = INREG(RADEON_SEPROM_CNTL1); 226 uint32_t viph_control = INREG(RADEON_VIPH_CONTROL); 227 uint32_t bus_cntl = INREG(RADEON_BUS_CNTL); 228 uint32_t d1vga_control = INREG(AVIVO_D1VGA_CONTROL); 229 uint32_t d2vga_control = INREG(AVIVO_D2VGA_CONTROL); 230 uint32_t vga_render_control = INREG(AVIVO_VGA_RENDER_CONTROL); 231 uint32_t gpiopad_a = INREG(RADEON_GPIOPAD_A); 232 uint32_t gpiopad_en = INREG(RADEON_GPIOPAD_EN); 233 uint32_t gpiopad_mask = INREG(RADEON_GPIOPAD_MASK); 234 235 OUTREG(RADEON_SEPROM_CNTL1, ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 236 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 237 238 OUTREG(RADEON_GPIOPAD_A, 0); 239 OUTREG(RADEON_GPIOPAD_EN, 0); 240 OUTREG(RADEON_GPIOPAD_MASK, 0); 241 242 /* disable VIP */ 243 OUTREG(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 244 245 /* enable the rom */ 246 OUTREG(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 247 248 /* Disable VGA mode */ 249 OUTREG(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 250 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 251 OUTREG(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 252 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 253 OUTREG(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 254 255 ret = radeon_read_bios(pScrn); 256 257 /* restore regs */ 258 OUTREG(RADEON_SEPROM_CNTL1, seprom_cntl1); 259 OUTREG(RADEON_VIPH_CONTROL, viph_control); 260 OUTREG(RADEON_BUS_CNTL, bus_cntl); 261 OUTREG(AVIVO_D1VGA_CONTROL, d1vga_control); 262 OUTREG(AVIVO_D2VGA_CONTROL, d2vga_control); 263 OUTREG(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 264 OUTREG(RADEON_GPIOPAD_A, gpiopad_a); 265 OUTREG(RADEON_GPIOPAD_EN, gpiopad_en); 266 OUTREG(RADEON_GPIOPAD_MASK, gpiopad_mask); 267 268 } else { 269 uint32_t seprom_cntl1 = INREG(RADEON_SEPROM_CNTL1); 270 uint32_t viph_control = INREG(RADEON_VIPH_CONTROL); 271 uint32_t bus_cntl = INREG(RADEON_BUS_CNTL); 272 uint32_t crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); 273 uint32_t crtc2_gen_cntl = 0; 274 uint32_t crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL); 275 uint32_t fp2_gen_cntl = 0; 276 277 if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) 278 fp2_gen_cntl = INREG(RADEON_FP2_GEN_CNTL); 279 280 if (pRADEONEnt->HasCRTC2) 281 crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); 282 283 OUTREG(RADEON_SEPROM_CNTL1, ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 284 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 285 286 /* disable VIP */ 287 OUTREG(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 288 289 /* enable the rom */ 290 OUTREG(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 291 292 /* Turn off mem requests and CRTC for both controllers */ 293 OUTREG(RADEON_CRTC_GEN_CNTL, ((crtc_gen_cntl & ~RADEON_CRTC_EN) | 294 (RADEON_CRTC_DISP_REQ_EN_B | 295 RADEON_CRTC_EXT_DISP_EN))); 296 if (pRADEONEnt->HasCRTC2) 297 OUTREG(RADEON_CRTC2_GEN_CNTL, ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | 298 RADEON_CRTC2_DISP_REQ_EN_B)); 299 300 /* Turn off CRTC */ 301 OUTREG(RADEON_CRTC_EXT_CNTL, ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | 302 (RADEON_CRTC_SYNC_TRISTAT | 303 RADEON_CRTC_DISPLAY_DIS))); 304 305 if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) 306 OUTREG(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); 307 308 ret = radeon_read_bios(pScrn); 309 310 /* restore regs */ 311 OUTREG(RADEON_SEPROM_CNTL1, seprom_cntl1); 312 OUTREG(RADEON_VIPH_CONTROL, viph_control); 313 OUTREG(RADEON_BUS_CNTL, bus_cntl); 314 OUTREG(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 315 if (pRADEONEnt->HasCRTC2) 316 OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 317 OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 318 if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) 319 OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 320 } 321 return ret; 322} 323 324Bool 325radeon_card_posted(ScrnInfoPtr pScrn) 326{ 327 RADEONInfoPtr info = RADEONPTR(pScrn); 328 unsigned char *RADEONMMIO = info->MMIO; 329 uint32_t reg; 330 331 /* first check CRTCs */ 332 if (IS_AVIVO_VARIANT) { 333 reg = INREG(AVIVO_D1CRTC_CONTROL) | INREG(AVIVO_D2CRTC_CONTROL); 334 if (reg & AVIVO_CRTC_EN) 335 return TRUE; 336 } else { 337 reg = INREG(RADEON_CRTC_GEN_CNTL) | INREG(RADEON_CRTC2_GEN_CNTL); 338 if (reg & RADEON_CRTC_EN) 339 return TRUE; 340 } 341 342 /* then check MEM_SIZE, in case something turned the crtcs off */ 343 if (info->ChipFamily >= CHIP_FAMILY_R600) 344 reg = INREG(R600_CONFIG_MEMSIZE); 345 else 346 reg = INREG(RADEON_CONFIG_MEMSIZE); 347 348 if (reg) 349 return TRUE; 350 351 return FALSE; 352} 353 354/* Read the Video BIOS block and the FP registers (if applicable). */ 355Bool 356RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) 357{ 358 RADEONInfoPtr info = RADEONPTR(pScrn); 359 int tmp; 360 unsigned short dptr; 361 362#ifdef XSERVER_LIBPCIACCESS 363 int size = info->PciInfo->rom_size > RADEON_VBIOS_SIZE ? info->PciInfo->rom_size : RADEON_VBIOS_SIZE; 364 info->VBIOS = xalloc(size); 365#else 366 info->VBIOS = xalloc(RADEON_VBIOS_SIZE); 367#endif 368 if (!info->VBIOS) { 369 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 370 "Cannot allocate space for hold Video BIOS!\n"); 371 return FALSE; 372 } else { 373 if (pInt10) { 374 info->BIOSAddr = pInt10->BIOSseg << 4; 375 (void)memcpy(info->VBIOS, xf86int10Addr(pInt10, info->BIOSAddr), 376 RADEON_VBIOS_SIZE); 377 } else if (!radeon_read_bios(pScrn)) 378 (void)radeon_read_disabled_bios(pScrn); 379 } 380 381 if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) { 382 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 383 "Unrecognized BIOS signature, BIOS data will not be used\n"); 384 xfree (info->VBIOS); 385 info->VBIOS = NULL; 386 return FALSE; 387 } 388 389 /* Verify it's an x86 BIOS not OF firmware, copied from radeonfb */ 390 dptr = RADEON_BIOS16(0x18); 391 /* If PCI data signature is wrong assume x86 video BIOS anyway */ 392 if (RADEON_BIOS32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) { 393 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 394 "ROM PCI data signature incorrect, ignoring\n"); 395 } 396 else if (info->VBIOS[dptr + 0x14] != 0x0) { 397 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 398 "Not an x86 BIOS ROM image, BIOS data will not be used\n"); 399 xfree (info->VBIOS); 400 info->VBIOS = NULL; 401 return FALSE; 402 } 403 404 if (info->VBIOS) info->ROMHeaderStart = RADEON_BIOS16(0x48); 405 406 if(!info->ROMHeaderStart) { 407 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 408 "Invalid ROM pointer, BIOS data will not be used\n"); 409 xfree (info->VBIOS); 410 info->VBIOS = NULL; 411 return FALSE; 412 } 413 414 tmp = info->ROMHeaderStart + 4; 415 if ((RADEON_BIOS8(tmp) == 'A' && 416 RADEON_BIOS8(tmp+1) == 'T' && 417 RADEON_BIOS8(tmp+2) == 'O' && 418 RADEON_BIOS8(tmp+3) == 'M') || 419 (RADEON_BIOS8(tmp) == 'M' && 420 RADEON_BIOS8(tmp+1) == 'O' && 421 RADEON_BIOS8(tmp+2) == 'T' && 422 RADEON_BIOS8(tmp+3) == 'A')) 423 info->IsAtomBios = TRUE; 424 else 425 info->IsAtomBios = FALSE; 426 427 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s BIOS detected\n", 428 info->IsAtomBios ? "ATOM":"Legacy"); 429 430 if (info->IsAtomBios) { 431 AtomBiosArgRec atomBiosArg; 432 433 if (RHDAtomBiosFunc(pScrn->scrnIndex, NULL, ATOMBIOS_INIT, &atomBiosArg) 434 == ATOM_SUCCESS) { 435 info->atomBIOS = atomBiosArg.atomhandle; 436 } 437 438 atomBiosArg.fb.start = info->FbFreeStart; 439 atomBiosArg.fb.size = info->FbFreeSize; 440 if (RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, ATOMBIOS_ALLOCATE_FB_SCRATCH, 441 &atomBiosArg) == ATOM_SUCCESS) { 442 443 info->FbFreeStart = atomBiosArg.fb.start; 444 info->FbFreeSize = atomBiosArg.fb.size; 445 } 446 447 RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, GET_DEFAULT_ENGINE_CLOCK, 448 &atomBiosArg); 449 RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, GET_DEFAULT_MEMORY_CLOCK, 450 &atomBiosArg); 451 RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, 452 GET_MAX_PIXEL_CLOCK_PLL_OUTPUT, &atomBiosArg); 453 RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, 454 GET_MIN_PIXEL_CLOCK_PLL_OUTPUT, &atomBiosArg); 455 RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, 456 GET_MAX_PIXEL_CLOCK_PLL_INPUT, &atomBiosArg); 457 RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, 458 GET_MIN_PIXEL_CLOCK_PLL_INPUT, &atomBiosArg); 459 RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, 460 GET_MAX_PIXEL_CLK, &atomBiosArg); 461 RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, 462 GET_REF_CLOCK, &atomBiosArg); 463 464 info->MasterDataStart = RADEON_BIOS16 (info->ROMHeaderStart + 32); 465 } 466 467 /* We are a bit too quick at using this "unposted" to re-post the 468 * card. This causes some problems with VT switch on some machines, 469 * so let's work around this for now by only POSTing if none of the 470 * CRTCs are enabled 471 */ 472 if ((!radeon_card_posted(pScrn)) && info->VBIOS) { 473 if (info->IsAtomBios) { 474 if (!rhdAtomASICInit(info->atomBIOS)) 475 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 476 "%s: AsicInit failed.\n",__func__); 477 } else { 478#if 0 479 /* FIX ME */ 480 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Attempting to POST via legacy BIOS tables\n"); 481 RADEONGetBIOSInitTableOffsets(pScrn); 482 RADEONPostCardFromBIOSTables(pScrn); 483#endif 484 } 485 } 486 487 return TRUE; 488} 489 490static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn) 491{ 492 RADEONInfoPtr info = RADEONPTR (pScrn); 493 494 if (!info->VBIOS) return FALSE; 495 496 if (RADEONGetATOMConnectorInfoFromBIOSObject(pScrn)) 497 return TRUE; 498 499 if (RADEONGetATOMConnectorInfoFromBIOSConnectorTable(pScrn)) 500 return TRUE; 501 502 return FALSE; 503} 504 505static void RADEONApplyLegacyQuirks(ScrnInfoPtr pScrn, int index) 506{ 507 RADEONInfoPtr info = RADEONPTR (pScrn); 508 509 /* XPRESS DDC quirks */ 510 if ((info->ChipFamily == CHIP_FAMILY_RS400 || 511 info->ChipFamily == CHIP_FAMILY_RS480) && 512 info->BiosConnector[index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) { 513 info->BiosConnector[index].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); 514 } else if ((info->ChipFamily == CHIP_FAMILY_RS400 || 515 info->ChipFamily == CHIP_FAMILY_RS480) && 516 info->BiosConnector[index].ddc_i2c.mask_clk_reg == RADEON_GPIO_MONID) { 517 info->BiosConnector[index].ddc_i2c.valid = TRUE; 518 info->BiosConnector[index].ddc_i2c.mask_clk_mask = (0x20 << 8); 519 info->BiosConnector[index].ddc_i2c.mask_data_mask = 0x80; 520 info->BiosConnector[index].ddc_i2c.a_clk_mask = (0x20 << 8); 521 info->BiosConnector[index].ddc_i2c.a_data_mask = 0x80; 522 info->BiosConnector[index].ddc_i2c.put_clk_mask = (0x20 << 8); 523 info->BiosConnector[index].ddc_i2c.put_data_mask = 0x80; 524 info->BiosConnector[index].ddc_i2c.get_clk_mask = (0x20 << 8); 525 info->BiosConnector[index].ddc_i2c.get_data_mask = 0x80; 526 info->BiosConnector[index].ddc_i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; 527 info->BiosConnector[index].ddc_i2c.mask_data_reg = RADEON_GPIOPAD_MASK; 528 info->BiosConnector[index].ddc_i2c.a_clk_reg = RADEON_GPIOPAD_A; 529 info->BiosConnector[index].ddc_i2c.a_data_reg = RADEON_GPIOPAD_A; 530 info->BiosConnector[index].ddc_i2c.put_clk_reg = RADEON_GPIOPAD_EN; 531 info->BiosConnector[index].ddc_i2c.put_data_reg = RADEON_GPIOPAD_EN; 532 info->BiosConnector[index].ddc_i2c.get_clk_reg = RADEON_LCD_GPIO_Y_REG; 533 info->BiosConnector[index].ddc_i2c.get_data_reg = RADEON_LCD_GPIO_Y_REG; 534 } 535 536 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */ 537 if ((IS_R300_VARIANT) && 538 info->BiosConnector[index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) 539 info->BiosConnector[index].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); 540 541 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, 542 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ 543 if (info->Chipset == PCI_CHIP_RN50_515E && 544 PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1014) { 545 if (info->BiosConnector[index].ConnectorType == CONNECTOR_VGA && 546 info->BiosConnector[index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) { 547 info->BiosConnector[index].valid = FALSE; 548 } 549 } 550 551 /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */ 552 if (info->Chipset == PCI_CHIP_RV100_QY && 553 PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1002 && 554 PCI_SUB_DEVICE_ID(info->PciInfo) == 0x013a) { 555 if (info->BiosConnector[index].ConnectorType == CONNECTOR_DVI_I) { 556 info->BiosConnector[index].ConnectorType = CONNECTOR_VGA; 557 } 558 } 559 560 /* X300 card with extra non-existent DVI port */ 561 if (info->Chipset == PCI_CHIP_RV370_5B60 && 562 PCI_SUB_VENDOR_ID(info->PciInfo) == 0x17af && 563 PCI_SUB_DEVICE_ID(info->PciInfo) == 0x201e && 564 index == 2) { 565 if (info->BiosConnector[index].ConnectorType == CONNECTOR_DVI_I) { 566 info->BiosConnector[index].valid = FALSE; 567 } 568 } 569 570 /* r200 card with primary dac routed to both VGA and DVI - disable load detection 571 * otherwise you end up detecing load if either port is attached 572 */ 573 if (info->Chipset == PCI_CHIP_R200_QL && 574 PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1569 && 575 PCI_SUB_DEVICE_ID(info->PciInfo) == 0x514c && 576 (info->BiosConnector[index].devices & ATOM_DEVICE_CRT1_SUPPORT)) { 577 info->BiosConnector[index].load_detection = FALSE; 578 } 579 580} 581 582static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) 583{ 584 RADEONInfoPtr info = RADEONPTR (pScrn); 585 int offset, i, entry, tmp, tmp0, tmp1; 586 RADEONLegacyDDCType DDCType; 587 RADEONLegacyConnectorType ConnectorType; 588 589 if (!info->VBIOS) return FALSE; 590 591 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x50); 592 if (offset) { 593 for (i = 0; i < 4; i++) { 594 entry = offset + 2 + i*2; 595 596 if (!RADEON_BIOS16(entry)) { 597 break; 598 } 599 info->BiosConnector[i].valid = TRUE; 600 tmp = RADEON_BIOS16(entry); 601 info->BiosConnector[i].ConnectorType = (tmp >> 12) & 0xf; 602 ConnectorType = (tmp >> 12) & 0xf; 603 switch (ConnectorType) { 604 case CONNECTOR_PROPRIETARY_LEGACY: 605 info->BiosConnector[i].ConnectorType = CONNECTOR_DVI_D; 606 if ((tmp >> 4) & 0x1) { 607 info->BiosConnector[i].devices |= ATOM_DEVICE_DFP2_SUPPORT; 608 if (!radeon_add_encoder(pScrn, 609 radeon_get_encoder_id_from_supported_device(pScrn, 610 ATOM_DEVICE_DFP2_SUPPORT, 611 0), 612 ATOM_DEVICE_DFP2_SUPPORT)) 613 return FALSE; 614 } else { 615 info->BiosConnector[i].devices |= ATOM_DEVICE_DFP1_SUPPORT; 616 if (!radeon_add_encoder(pScrn, 617 radeon_get_encoder_id_from_supported_device(pScrn, 618 ATOM_DEVICE_DFP1_SUPPORT, 619 0), 620 ATOM_DEVICE_DFP1_SUPPORT)) 621 return FALSE; 622 } 623 break; 624 case CONNECTOR_CRT_LEGACY: 625 info->BiosConnector[i].ConnectorType = CONNECTOR_VGA; 626 if (tmp & 0x1) { 627 info->BiosConnector[i].load_detection = FALSE; 628 info->BiosConnector[i].devices |= ATOM_DEVICE_CRT2_SUPPORT; 629 if (!radeon_add_encoder(pScrn, 630 radeon_get_encoder_id_from_supported_device(pScrn, 631 ATOM_DEVICE_CRT2_SUPPORT, 632 2), 633 ATOM_DEVICE_CRT2_SUPPORT)) 634 return FALSE; 635 } else { 636 info->BiosConnector[i].load_detection = TRUE; 637 info->BiosConnector[i].devices |= ATOM_DEVICE_CRT1_SUPPORT; 638 if (!radeon_add_encoder(pScrn, 639 radeon_get_encoder_id_from_supported_device(pScrn, 640 ATOM_DEVICE_CRT1_SUPPORT, 641 1), 642 ATOM_DEVICE_CRT1_SUPPORT)) 643 return FALSE; 644 } 645 break; 646 case CONNECTOR_DVI_I_LEGACY: 647 info->BiosConnector[i].ConnectorType = CONNECTOR_DVI_I; 648 if (tmp & 0x1) { 649 info->BiosConnector[i].load_detection = FALSE; 650 info->BiosConnector[i].devices |= ATOM_DEVICE_CRT2_SUPPORT; 651 if (!radeon_add_encoder(pScrn, 652 radeon_get_encoder_id_from_supported_device(pScrn, 653 ATOM_DEVICE_CRT2_SUPPORT, 654 2), 655 ATOM_DEVICE_CRT2_SUPPORT)) 656 return FALSE; 657 } else { 658 info->BiosConnector[i].load_detection = TRUE; 659 info->BiosConnector[i].devices |= ATOM_DEVICE_CRT1_SUPPORT; 660 if (!radeon_add_encoder(pScrn, 661 radeon_get_encoder_id_from_supported_device(pScrn, 662 ATOM_DEVICE_CRT1_SUPPORT, 663 1), 664 ATOM_DEVICE_CRT1_SUPPORT)) 665 return FALSE; 666 } 667 if ((tmp >> 4) & 0x1) { 668 info->BiosConnector[i].devices |= ATOM_DEVICE_DFP2_SUPPORT; 669 if (!radeon_add_encoder(pScrn, 670 radeon_get_encoder_id_from_supported_device(pScrn, 671 ATOM_DEVICE_DFP2_SUPPORT, 672 0), 673 ATOM_DEVICE_DFP2_SUPPORT)) 674 return FALSE; 675 } else { 676 info->BiosConnector[i].devices |= ATOM_DEVICE_DFP1_SUPPORT; 677 if (!radeon_add_encoder(pScrn, 678 radeon_get_encoder_id_from_supported_device(pScrn, 679 ATOM_DEVICE_DFP1_SUPPORT, 680 0), 681 ATOM_DEVICE_DFP1_SUPPORT)) 682 return FALSE; 683 } 684 break; 685 case CONNECTOR_DVI_D_LEGACY: 686 info->BiosConnector[i].ConnectorType = CONNECTOR_DVI_D; 687 if ((tmp >> 4) & 0x1) { 688 info->BiosConnector[i].devices |= ATOM_DEVICE_DFP2_SUPPORT; 689 if (!radeon_add_encoder(pScrn, 690 radeon_get_encoder_id_from_supported_device(pScrn, 691 ATOM_DEVICE_DFP2_SUPPORT, 692 0), 693 ATOM_DEVICE_DFP2_SUPPORT)) 694 return FALSE; 695 } else { 696 info->BiosConnector[i].devices |= ATOM_DEVICE_DFP1_SUPPORT; 697 if (!radeon_add_encoder(pScrn, 698 radeon_get_encoder_id_from_supported_device(pScrn, 699 ATOM_DEVICE_DFP1_SUPPORT, 700 0), 701 ATOM_DEVICE_DFP1_SUPPORT)) 702 return FALSE; 703 } 704 break; 705 case CONNECTOR_CTV_LEGACY: 706 info->BiosConnector[i].ConnectorType = CONNECTOR_CTV; 707 info->BiosConnector[i].load_detection = FALSE; 708 info->BiosConnector[i].devices = ATOM_DEVICE_TV1_SUPPORT; 709 if (!radeon_add_encoder(pScrn, 710 radeon_get_encoder_id_from_supported_device(pScrn, 711 ATOM_DEVICE_TV1_SUPPORT, 712 2), 713 ATOM_DEVICE_TV1_SUPPORT)) 714 return FALSE; 715 break; 716 case CONNECTOR_STV_LEGACY: 717 info->BiosConnector[i].ConnectorType = CONNECTOR_STV; 718 info->BiosConnector[i].load_detection = FALSE; 719 info->BiosConnector[i].devices = ATOM_DEVICE_TV1_SUPPORT; 720 if (!radeon_add_encoder(pScrn, 721 radeon_get_encoder_id_from_supported_device(pScrn, 722 ATOM_DEVICE_TV1_SUPPORT, 723 2), 724 ATOM_DEVICE_TV1_SUPPORT)) 725 return FALSE; 726 break; 727 default: 728 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown Connector Type: %d\n", ConnectorType); 729 info->BiosConnector[i].valid = FALSE; 730 break; 731 } 732 733 info->BiosConnector[i].ddc_i2c.valid = FALSE; 734 735 DDCType = (tmp >> 8) & 0xf; 736 switch (DDCType) { 737 case DDC_MONID: 738 info->BiosConnector[i].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); 739 break; 740 case DDC_DVI: 741 info->BiosConnector[i].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); 742 break; 743 case DDC_VGA: 744 info->BiosConnector[i].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); 745 break; 746 case DDC_CRT2: 747 info->BiosConnector[i].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); 748 break; 749 default: 750 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown DDC Type: %d\n", DDCType); 751 break; 752 } 753 754 RADEONApplyLegacyQuirks(pScrn, i); 755 756 } 757 } else { 758 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No Connector Info Table found!\n"); 759 760 /* old radeons and r128 didn't use connector tables you just check 761 * for LVDS, DVI, TV, etc. tables 762 */ 763 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x34); 764 if (offset) { 765 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 766 "Found DFP table, assuming DVI connector\n"); 767 info->BiosConnector[0].valid = TRUE; 768 info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I; 769 info->BiosConnector[0].load_detection = TRUE; 770 info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); 771 info->BiosConnector[0].devices = ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_DFP1_SUPPORT; 772 if (!radeon_add_encoder(pScrn, 773 radeon_get_encoder_id_from_supported_device(pScrn, 774 ATOM_DEVICE_DFP1_SUPPORT, 775 0), 776 ATOM_DEVICE_DFP1_SUPPORT)) 777 return FALSE; 778 if (!radeon_add_encoder(pScrn, 779 radeon_get_encoder_id_from_supported_device(pScrn, 780 ATOM_DEVICE_CRT1_SUPPORT, 781 1), 782 ATOM_DEVICE_CRT1_SUPPORT)) 783 return FALSE; 784 } else 785 return FALSE; 786 } 787 788 /* check LVDS table */ 789 /* IGP can be mobile or desktop so check the connectors */ 790 if (info->IsMobility || info->IsIGP) { 791 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x40); 792 if (offset) { 793 info->BiosConnector[4].valid = TRUE; 794 info->BiosConnector[4].ConnectorType = CONNECTOR_LVDS; 795 info->BiosConnector[4].ddc_i2c.valid = FALSE; 796 797 info->BiosConnector[4].devices = ATOM_DEVICE_LCD1_SUPPORT; 798 if (!radeon_add_encoder(pScrn, 799 radeon_get_encoder_id_from_supported_device(pScrn, 800 ATOM_DEVICE_LCD1_SUPPORT, 801 0), 802 ATOM_DEVICE_LCD1_SUPPORT)) 803 return FALSE; 804 805 tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x42); 806 if (tmp) { 807 tmp0 = RADEON_BIOS16(tmp + 0x15); 808 if (tmp0) { 809 tmp1 = RADEON_BIOS8(tmp0+2) & 0x07; 810 if (tmp1) { 811 DDCType = tmp1; 812 switch (DDCType) { 813 case DDC_NONE_DETECTED: 814 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "No DDC for LCD\n"); 815 break; 816 case DDC_MONID: 817 info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); 818 break; 819 case DDC_DVI: 820 info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); 821 break; 822 case DDC_VGA: 823 info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); 824 break; 825 case DDC_CRT2: 826 info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); 827 break; 828 case DDC_LCD: 829 info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_LCD_GPIO_MASK); 830 info->BiosConnector[4].ddc_i2c.mask_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 831 info->BiosConnector[4].ddc_i2c.mask_data_mask = RADEON_BIOS32(tmp0 + 0x07); 832 info->BiosConnector[4].ddc_i2c.a_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 833 info->BiosConnector[4].ddc_i2c.a_data_mask = RADEON_BIOS32(tmp0 + 0x07); 834 info->BiosConnector[4].ddc_i2c.put_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 835 info->BiosConnector[4].ddc_i2c.put_data_mask = RADEON_BIOS32(tmp0 + 0x07); 836 info->BiosConnector[4].ddc_i2c.get_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 837 info->BiosConnector[4].ddc_i2c.get_data_mask = RADEON_BIOS32(tmp0 + 0x07); 838 break; 839 case DDC_GPIO: 840 info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_MDGPIO_EN_REG); 841 info->BiosConnector[4].ddc_i2c.mask_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 842 info->BiosConnector[4].ddc_i2c.mask_data_mask = RADEON_BIOS32(tmp0 + 0x07); 843 info->BiosConnector[4].ddc_i2c.a_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 844 info->BiosConnector[4].ddc_i2c.a_data_mask = RADEON_BIOS32(tmp0 + 0x07); 845 info->BiosConnector[4].ddc_i2c.put_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 846 info->BiosConnector[4].ddc_i2c.put_data_mask = RADEON_BIOS32(tmp0 + 0x07); 847 info->BiosConnector[4].ddc_i2c.get_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 848 info->BiosConnector[4].ddc_i2c.get_data_mask = RADEON_BIOS32(tmp0 + 0x07); 849 break; 850 default: 851 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown DDC Type: %d\n", DDCType); 852 break; 853 } 854 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "LCD DDC Info Table found!\n"); 855 } 856 } 857 } else 858 info->BiosConnector[4].ddc_i2c.valid = FALSE; 859 } 860 } 861 862 /* check TV table */ 863 if (info->InternalTVOut) { 864 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x32); 865 if (offset) { 866 if (RADEON_BIOS8(offset + 6) == 'T') { 867 info->BiosConnector[5].valid = TRUE; 868 /* assume s-video for now */ 869 info->BiosConnector[5].ConnectorType = CONNECTOR_STV; 870 info->BiosConnector[5].load_detection = FALSE; 871 info->BiosConnector[5].ddc_i2c.valid = FALSE; 872 info->BiosConnector[5].devices = ATOM_DEVICE_TV1_SUPPORT; 873 if (!radeon_add_encoder(pScrn, 874 radeon_get_encoder_id_from_supported_device(pScrn, 875 ATOM_DEVICE_TV1_SUPPORT, 876 2), 877 ATOM_DEVICE_TV1_SUPPORT)) 878 return FALSE; 879 } 880 } 881 } 882 883 return TRUE; 884} 885 886Bool RADEONGetConnectorInfoFromBIOS (ScrnInfoPtr pScrn) 887{ 888 RADEONInfoPtr info = RADEONPTR (pScrn); 889 890 if(!info->VBIOS) return FALSE; 891 892 if (info->IsAtomBios) 893 return RADEONGetATOMConnectorInfoFromBIOS(pScrn); 894 else 895 return RADEONGetLegacyConnectorInfoFromBIOS(pScrn); 896} 897 898Bool RADEONGetTVInfoFromBIOS (xf86OutputPtr output) { 899 ScrnInfoPtr pScrn = output->scrn; 900 RADEONInfoPtr info = RADEONPTR(pScrn); 901 RADEONOutputPrivatePtr radeon_output = output->driver_private; 902 radeon_tvout_ptr tvout = &radeon_output->tvout; 903 int offset, refclk, stds; 904 905 if (!info->VBIOS) return FALSE; 906 907 if (info->IsAtomBios) 908 return RADEONGetATOMTVInfo(output); 909 else { 910 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x32); 911 if (offset) { 912 if (RADEON_BIOS8(offset + 6) == 'T') { 913 switch (RADEON_BIOS8(offset + 7) & 0xf) { 914 case 1: 915 tvout->default_tvStd = TV_STD_NTSC; 916 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: NTSC\n"); 917 break; 918 case 2: 919 tvout->default_tvStd = TV_STD_PAL; 920 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: PAL\n"); 921 break; 922 case 3: 923 tvout->default_tvStd = TV_STD_PAL_M; 924 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: PAL-M\n"); 925 break; 926 case 4: 927 tvout->default_tvStd = TV_STD_PAL_60; 928 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: PAL-60\n"); 929 break; 930 case 5: 931 tvout->default_tvStd = TV_STD_NTSC_J; 932 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: NTSC-J\n"); 933 break; 934 case 6: 935 tvout->default_tvStd = TV_STD_SCART_PAL; 936 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: SCART-PAL\n"); 937 break; 938 default: 939 tvout->default_tvStd = TV_STD_NTSC; 940 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Unknown TV standard; defaulting to NTSC\n"); 941 break; 942 } 943 tvout->tvStd = tvout->default_tvStd; 944 945 refclk = (RADEON_BIOS8(offset + 9) >> 2) & 0x3; 946 if (refclk == 0) 947 tvout->TVRefClk = 29.498928713; /* MHz */ 948 else if (refclk == 1) 949 tvout->TVRefClk = 28.636360000; 950 else if (refclk == 2) 951 tvout->TVRefClk = 14.318180000; 952 else if (refclk == 3) 953 tvout->TVRefClk = 27.000000000; 954 955 tvout->SupportedTVStds = tvout->default_tvStd; 956 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TV standards supported by chip: "); 957 stds = RADEON_BIOS8(offset + 10) & 0x1f; 958 if (stds & TV_STD_NTSC) { 959 tvout->SupportedTVStds |= TV_STD_NTSC; 960 ErrorF("NTSC "); 961 } 962 if (stds & TV_STD_PAL) { 963 tvout->SupportedTVStds |= TV_STD_PAL; 964 ErrorF("PAL "); 965 } 966 if (stds & TV_STD_PAL_M) { 967 tvout->SupportedTVStds |= TV_STD_PAL_M; 968 ErrorF("PAL-M "); 969 } 970 if (stds & TV_STD_PAL_60) { 971 tvout->SupportedTVStds |= TV_STD_PAL_60; 972 ErrorF("PAL-60 "); 973 } 974 if (stds & TV_STD_NTSC_J) { 975 tvout->SupportedTVStds |= TV_STD_NTSC_J; 976 ErrorF("NTSC-J "); 977 } 978 if (stds & TV_STD_SCART_PAL) { 979 tvout->SupportedTVStds |= TV_STD_SCART_PAL; 980 ErrorF("SCART-PAL"); 981 } 982 ErrorF("\n"); 983 984 return TRUE; 985 } 986 } 987 } 988 return FALSE; 989} 990 991/* Read PLL parameters from BIOS block. Default to typical values if there 992 is no BIOS. */ 993Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn) 994{ 995 RADEONInfoPtr info = RADEONPTR (pScrn); 996 RADEONPLLPtr pll = &info->pll; 997 uint16_t pll_info_block; 998 999 if (!info->VBIOS) { 1000 return FALSE; 1001 } else { 1002 if (info->IsAtomBios) { 1003 return RADEONGetATOMClockInfo(pScrn); 1004 } else { 1005 int rev; 1006 1007 pll_info_block = RADEON_BIOS16 (info->ROMHeaderStart + 0x30); 1008 1009 rev = RADEON_BIOS8(pll_info_block); 1010 1011 pll->reference_freq = RADEON_BIOS16 (pll_info_block + 0x0e); 1012 pll->reference_div = RADEON_BIOS16 (pll_info_block + 0x10); 1013 pll->pll_out_min = RADEON_BIOS32 (pll_info_block + 0x12); 1014 pll->pll_out_max = RADEON_BIOS32 (pll_info_block + 0x16); 1015 1016 if (rev > 9) { 1017 pll->pll_in_min = RADEON_BIOS32(pll_info_block + 0x36); 1018 pll->pll_in_max = RADEON_BIOS32(pll_info_block + 0x3a); 1019 } else { 1020 pll->pll_in_min = 40; 1021 pll->pll_in_max = 500; 1022 } 1023 1024 pll->xclk = RADEON_BIOS16(pll_info_block + 0x08); 1025 1026 info->sclk = RADEON_BIOS16(pll_info_block + 10) / 100.0; 1027 info->mclk = RADEON_BIOS16(pll_info_block + 8) / 100.0; 1028 } 1029 1030 if (info->sclk == 0) info->sclk = 200; 1031 if (info->mclk == 0) info->mclk = 200; 1032 } 1033 1034 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "ref_freq: %d, min_out_pll: %u, " 1035 "max_out_pll: %u, min_in_pll: %u, max_in_pll: %u, xclk: %d, " 1036 "sclk: %f, mclk: %f\n", 1037 pll->reference_freq, (unsigned)pll->pll_out_min, 1038 (unsigned)pll->pll_out_max, (unsigned)pll->pll_in_min, 1039 (unsigned)pll->pll_in_max, pll->xclk, info->sclk, info->mclk); 1040 1041 return TRUE; 1042} 1043 1044Bool RADEONGetDAC2InfoFromBIOS (ScrnInfoPtr pScrn, radeon_tvdac_ptr tvdac) 1045{ 1046 RADEONInfoPtr info = RADEONPTR(pScrn); 1047 int offset, rev, bg, dac; 1048 1049 if (!info->VBIOS) return FALSE; 1050 1051 if (xf86ReturnOptValBool(info->Options, OPTION_DEFAULT_TVDAC_ADJ, FALSE)) 1052 return FALSE; 1053 1054 if (info->IsAtomBios) { 1055 /* not implemented yet */ 1056 return FALSE; 1057 } else { 1058 /* first check TV table */ 1059 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x32); 1060 if (offset) { 1061 rev = RADEON_BIOS8(offset + 0x3); 1062 if (rev > 4) { 1063 bg = RADEON_BIOS8(offset + 0xc) & 0xf; 1064 dac = RADEON_BIOS8(offset + 0xd) & 0xf; 1065 tvdac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1066 1067 bg = RADEON_BIOS8(offset + 0xe) & 0xf; 1068 dac = RADEON_BIOS8(offset + 0xf) & 0xf; 1069 tvdac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1070 1071 bg = RADEON_BIOS8(offset + 0x10) & 0xf; 1072 dac = RADEON_BIOS8(offset + 0x11) & 0xf; 1073 tvdac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1074 1075 return TRUE; 1076 } else if (rev > 1) { 1077 bg = RADEON_BIOS8(offset + 0xc) & 0xf; 1078 dac = (RADEON_BIOS8(offset + 0xc) >> 4) & 0xf; 1079 tvdac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1080 1081 bg = RADEON_BIOS8(offset + 0xd) & 0xf; 1082 dac = (RADEON_BIOS8(offset + 0xd) >> 4) & 0xf; 1083 tvdac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1084 1085 bg = RADEON_BIOS8(offset + 0xe) & 0xf; 1086 dac = (RADEON_BIOS8(offset + 0xe) >> 4) & 0xf; 1087 tvdac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1088 1089 return TRUE; 1090 } 1091 } 1092 /* then check CRT table */ 1093 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x60); 1094 if (offset) { 1095 rev = RADEON_BIOS8(offset) & 0x3; 1096 if (rev < 2) { 1097 bg = RADEON_BIOS8(offset + 0x3) & 0xf; 1098 dac = (RADEON_BIOS8(offset + 0x3) >> 4) & 0xf; 1099 tvdac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1100 tvdac->pal_tvdac_adj = tvdac->ps2_tvdac_adj; 1101 tvdac->ntsc_tvdac_adj = tvdac->ps2_tvdac_adj; 1102 1103 return TRUE; 1104 } else { 1105 bg = RADEON_BIOS8(offset + 0x4) & 0xf; 1106 dac = RADEON_BIOS8(offset + 0x5) & 0xf; 1107 tvdac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1108 tvdac->pal_tvdac_adj = tvdac->ps2_tvdac_adj; 1109 tvdac->ntsc_tvdac_adj = tvdac->ps2_tvdac_adj; 1110 1111 return TRUE; 1112 } 1113 } 1114 } 1115 1116 return FALSE; 1117} 1118 1119Bool 1120RADEONGetLVDSInfoFromBIOS(ScrnInfoPtr pScrn, radeon_lvds_ptr lvds) 1121{ 1122 RADEONInfoPtr info = RADEONPTR(pScrn); 1123 radeon_native_mode_ptr native_mode = &lvds->native_mode; 1124 unsigned long tmp, i; 1125 1126 if (!info->VBIOS) 1127 return FALSE; 1128 1129 if (!info->IsAtomBios) { 1130 tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x40); 1131 1132 if (!tmp) { 1133 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1134 "No Panel Info Table found in BIOS!\n"); 1135 return FALSE; 1136 } else { 1137 char stmp[30]; 1138 int tmp0; 1139 1140 for (i = 0; i < 24; i++) 1141 stmp[i] = RADEON_BIOS8(tmp+i+1); 1142 stmp[24] = 0; 1143 1144 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1145 "Panel ID string: %s\n", stmp); 1146 1147 native_mode->PanelXRes = RADEON_BIOS16(tmp+25); 1148 native_mode->PanelYRes = RADEON_BIOS16(tmp+27); 1149 xf86DrvMsg(0, X_INFO, "Panel Size from BIOS: %dx%d\n", 1150 native_mode->PanelXRes, native_mode->PanelYRes); 1151 1152 lvds->PanelPwrDly = RADEON_BIOS16(tmp+44); 1153 if (lvds->PanelPwrDly > 2000 || lvds->PanelPwrDly < 0) 1154 lvds->PanelPwrDly = 2000; 1155 1156 /* some panels only work well with certain divider combinations. 1157 */ 1158 info->RefDivider = RADEON_BIOS16(tmp+46); 1159 info->PostDivider = RADEON_BIOS8(tmp+48); 1160 info->FeedbackDivider = RADEON_BIOS16(tmp+49); 1161 if ((info->RefDivider != 0) && 1162 (info->FeedbackDivider > 3)) { 1163 info->UseBiosDividers = TRUE; 1164 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1165 "BIOS provided dividers will be used.\n"); 1166 } 1167 1168 /* We don't use a while loop here just in case we have a corrupted BIOS image. 1169 The max number of table entries is 23 at present, but may grow in future. 1170 To ensure it works with future revisions we loop it to 32. 1171 */ 1172 for (i = 0; i < 32; i++) { 1173 tmp0 = RADEON_BIOS16(tmp+64+i*2); 1174 if (tmp0 == 0) break; 1175 if ((RADEON_BIOS16(tmp0) == native_mode->PanelXRes) && 1176 (RADEON_BIOS16(tmp0+2) == native_mode->PanelYRes)) { 1177 native_mode->HBlank = (RADEON_BIOS16(tmp0+17) - 1178 RADEON_BIOS16(tmp0+19)) * 8; 1179 native_mode->HOverPlus = (RADEON_BIOS16(tmp0+21) - 1180 RADEON_BIOS16(tmp0+19) - 1) * 8; 1181 native_mode->HSyncWidth = RADEON_BIOS8(tmp0+23) * 8; 1182 native_mode->VBlank = (RADEON_BIOS16(tmp0+24) - 1183 RADEON_BIOS16(tmp0+26)); 1184 native_mode->VOverPlus = ((RADEON_BIOS16(tmp0+28) & 0x7ff) - 1185 RADEON_BIOS16(tmp0+26)); 1186 native_mode->VSyncWidth = ((RADEON_BIOS16(tmp0+28) & 0xf800) >> 11); 1187 native_mode->DotClock = RADEON_BIOS16(tmp0+9) * 10; 1188 native_mode->Flags = 0; 1189 } 1190 } 1191 } 1192 1193 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1194 "LVDS Info:\n" 1195 "XRes: %d, YRes: %d, DotClock: %d\n" 1196 "HBlank: %d, HOverPlus: %d, HSyncWidth: %d\n" 1197 "VBlank: %d, VOverPlus: %d, VSyncWidth: %d\n", 1198 native_mode->PanelXRes, native_mode->PanelYRes, native_mode->DotClock, 1199 native_mode->HBlank, native_mode->HOverPlus, native_mode->HSyncWidth, 1200 native_mode->VBlank, native_mode->VOverPlus, native_mode->VSyncWidth); 1201 1202 return TRUE; 1203 } 1204 return FALSE; 1205} 1206 1207xf86MonPtr RADEONGetHardCodedEDIDFromBIOS (xf86OutputPtr output) 1208{ 1209 ScrnInfoPtr pScrn = output->scrn; 1210 RADEONInfoPtr info = RADEONPTR(pScrn); 1211 unsigned long tmp; 1212 unsigned char edid[256]; 1213 xf86MonPtr mon = NULL; 1214 1215 if (!info->VBIOS) 1216 return mon; 1217 1218 if (!info->IsAtomBios) { 1219 tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x4c); 1220 if (tmp) { 1221 memcpy(edid, (unsigned char*)(info->VBIOS + tmp), 256); 1222 if (edid[1] == 0xff) 1223 mon = xf86InterpretEDID(output->scrn->scrnIndex, edid); 1224 } 1225 } 1226 1227 return mon; 1228} 1229 1230Bool RADEONGetTMDSInfoFromBIOS (ScrnInfoPtr pScrn, radeon_tmds_ptr tmds) 1231{ 1232 RADEONInfoPtr info = RADEONPTR(pScrn); 1233 uint32_t tmp, maxfreq; 1234 int i, n; 1235 1236 if (!info->VBIOS) return FALSE; 1237 1238 if (info->IsAtomBios) { 1239 if((tmp = RADEON_BIOS16 (info->MasterDataStart + 18))) { 1240 1241 maxfreq = RADEON_BIOS16(tmp+4); 1242 1243 for (i=0; i<4; i++) { 1244 tmds->tmds_pll[i].freq = RADEON_BIOS16(tmp+i*6+6); 1245 /* This assumes each field in TMDS_PLL has 6 bit as in R300/R420 */ 1246 tmds->tmds_pll[i].value = ((RADEON_BIOS8(tmp+i*6+8) & 0x3f) | 1247 ((RADEON_BIOS8(tmp+i*6+10) & 0x3f)<<6) | 1248 ((RADEON_BIOS8(tmp+i*6+9) & 0xf)<<12) | 1249 ((RADEON_BIOS8(tmp+i*6+11) & 0xf)<<16)); 1250 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1251 "TMDS PLL from BIOS: %u %x\n", 1252 (unsigned)tmds->tmds_pll[i].freq, 1253 (unsigned)tmds->tmds_pll[i].value); 1254 1255 if (maxfreq == tmds->tmds_pll[i].freq) { 1256 tmds->tmds_pll[i].freq = 0xffffffff; 1257 break; 1258 } 1259 } 1260 return TRUE; 1261 } 1262 } else { 1263 1264 tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x34); 1265 if (tmp) { 1266 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1267 "DFP table revision: %d\n", RADEON_BIOS8(tmp)); 1268 if (RADEON_BIOS8(tmp) == 3) { 1269 n = RADEON_BIOS8(tmp + 5) + 1; 1270 if (n > 4) n = 4; 1271 for (i=0; i<n; i++) { 1272 tmds->tmds_pll[i].value = RADEON_BIOS32(tmp+i*10+0x08); 1273 tmds->tmds_pll[i].freq = RADEON_BIOS16(tmp+i*10+0x10); 1274 } 1275 return TRUE; 1276 } else if (RADEON_BIOS8(tmp) == 4) { 1277 int stride = 0; 1278 n = RADEON_BIOS8(tmp + 5) + 1; 1279 if (n > 4) n = 4; 1280 for (i=0; i<n; i++) { 1281 tmds->tmds_pll[i].value = RADEON_BIOS32(tmp+stride+0x08); 1282 tmds->tmds_pll[i].freq = RADEON_BIOS16(tmp+stride+0x10); 1283 if (i == 0) stride += 10; 1284 else stride += 6; 1285 } 1286 return TRUE; 1287 } 1288 } 1289 } 1290 return FALSE; 1291} 1292 1293static RADEONI2CBusRec 1294RADEONLookupI2CBlock(ScrnInfoPtr pScrn, int id) 1295{ 1296 RADEONInfoPtr info = RADEONPTR (pScrn); 1297 int offset, blocks, i; 1298 RADEONI2CBusRec i2c; 1299 1300 memset(&i2c, 0, sizeof(RADEONI2CBusRec)); 1301 i2c.valid = FALSE; 1302 1303 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x70); 1304 if (offset) { 1305 blocks = RADEON_BIOS8(offset + 2); 1306 for (i = 0; i < blocks; i++) { 1307 int i2c_id = RADEON_BIOS8(offset + 3 + (i * 5) + 0); 1308 if (id == i2c_id) { 1309 int clock_shift = RADEON_BIOS8(offset + 3 + (i * 5) + 3); 1310 int data_shift = RADEON_BIOS8(offset + 3 + (i * 5) + 4); 1311 1312 i2c.mask_clk_mask = (1 << clock_shift); 1313 i2c.mask_data_mask = (1 << data_shift); 1314 i2c.a_clk_mask = (1 << clock_shift); 1315 i2c.a_data_mask = (1 << data_shift); 1316 i2c.put_clk_mask = (1 << clock_shift); 1317 i2c.put_data_mask = (1 << data_shift); 1318 i2c.get_clk_mask = (1 << clock_shift); 1319 i2c.get_data_mask = (1 << data_shift); 1320 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; 1321 i2c.mask_data_reg = RADEON_GPIOPAD_MASK; 1322 i2c.a_clk_reg = RADEON_GPIOPAD_A; 1323 i2c.a_data_reg = RADEON_GPIOPAD_A; 1324 i2c.put_clk_reg = RADEON_GPIOPAD_EN; 1325 i2c.put_data_reg = RADEON_GPIOPAD_EN; 1326 i2c.get_clk_reg = RADEON_LCD_GPIO_Y_REG; 1327 i2c.get_data_reg = RADEON_LCD_GPIO_Y_REG; 1328 i2c.valid = TRUE; 1329 break; 1330 } 1331 } 1332 } 1333 return i2c; 1334} 1335 1336Bool RADEONGetExtTMDSInfoFromBIOS (ScrnInfoPtr pScrn, radeon_dvo_ptr dvo) 1337{ 1338 RADEONInfoPtr info = RADEONPTR(pScrn); 1339 int offset, table_start, max_freq, gpio_reg, flags; 1340 1341 if (!info->VBIOS) 1342 return FALSE; 1343 1344 if (info->IsAtomBios) 1345 return FALSE; 1346 else if (info->IsIGP) { 1347 /* RS4xx TMDS stuff is in the mobile table */ 1348 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x42); 1349 if (offset) { 1350 int rev = RADEON_BIOS8(offset); 1351 if (rev >= 6) { 1352 offset = RADEON_BIOS16(offset + 0x17); 1353 if (offset) { 1354 offset = RADEON_BIOS16(offset + 2); 1355 rev = RADEON_BIOS8(offset); 1356 if (offset && (rev > 1)) { 1357 int blocks = RADEON_BIOS8(offset + 3); 1358 int index = offset + 4; 1359 dvo->dvo_i2c.valid = FALSE; 1360 while (blocks > 0) { 1361 int id = RADEON_BIOS16(index); 1362 index += 2; 1363 switch (id >> 13) { 1364 case 0: 1365 index += 6; 1366 break; 1367 case 2: 1368 index += 10; 1369 break; 1370 case 3: 1371 index += 2; 1372 break; 1373 case 4: 1374 index += 2; 1375 break; 1376 case 6: 1377 dvo->dvo_i2c_slave_addr = 1378 RADEON_BIOS16(index) & 0xff; 1379 index += 2; 1380 dvo->dvo_i2c = 1381 RADEONLookupI2CBlock(pScrn, RADEON_BIOS8(index)); 1382 return TRUE; 1383 default: 1384 break; 1385 } 1386 blocks--; 1387 } 1388 } 1389 } 1390 } 1391 } else { 1392 dvo->dvo_i2c_slave_addr = 0x70; 1393 dvo->dvo_i2c = RADEONLookupI2CBlock(pScrn, 136); 1394 info->ext_tmds_chip = RADEON_SIL_164; 1395 } 1396 } else { 1397 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x58); 1398 if (offset) { 1399 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1400 "External TMDS Table revision: %d\n", 1401 RADEON_BIOS8(offset)); 1402 table_start = offset+4; 1403 max_freq = RADEON_BIOS16(table_start); 1404 dvo->dvo_i2c_slave_addr = RADEON_BIOS8(table_start+2); 1405 dvo->dvo_i2c.valid = FALSE; 1406 gpio_reg = RADEON_BIOS8(table_start+3); 1407 if (gpio_reg == 1) 1408 dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); 1409 else if (gpio_reg == 2) 1410 dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); 1411 else if (gpio_reg == 3) 1412 dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); 1413 else if (gpio_reg == 4) { 1414 if (IS_R300_VARIANT) 1415 dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); 1416 else 1417 dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); 1418 } else if (gpio_reg == 5) { 1419 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1420 "unsupported MM gpio_reg\n"); 1421 return FALSE; 1422 } else { 1423 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1424 "Unknown gpio reg: %d\n", gpio_reg); 1425 return FALSE; 1426 } 1427 flags = RADEON_BIOS8(table_start+5); 1428 dvo->dvo_duallink = flags & 0x01; 1429 if (dvo->dvo_duallink) { 1430 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1431 "Duallink TMDS detected\n"); 1432 } 1433 return TRUE; 1434 } 1435 } 1436 1437 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1438 "No External TMDS Table found\n"); 1439 1440 return FALSE; 1441} 1442 1443Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output) 1444{ 1445 ScrnInfoPtr pScrn = output->scrn; 1446 RADEONInfoPtr info = RADEONPTR(pScrn); 1447 unsigned char *RADEONMMIO = info->MMIO; 1448 radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); 1449 radeon_dvo_ptr dvo = NULL; 1450 int offset, index, id; 1451 uint32_t val, reg, and_mask, or_mask; 1452 1453 if (radeon_encoder == NULL) 1454 return FALSE; 1455 1456 dvo = (radeon_dvo_ptr)radeon_encoder->dev_priv; 1457 1458 if (dvo == NULL) 1459 return FALSE; 1460 1461 if (!info->VBIOS) 1462 return FALSE; 1463 1464 if (info->IsAtomBios) 1465 return FALSE; 1466 else if (info->IsIGP) { 1467 /* RS4xx TMDS stuff is in the mobile table */ 1468 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x42); 1469 if (offset) { 1470 int rev = RADEON_BIOS8(offset); 1471 if (rev >= 6) { 1472 offset = RADEON_BIOS16(offset + 0x17); 1473 if (offset) { 1474 offset = RADEON_BIOS16(offset + 2); 1475 rev = RADEON_BIOS8(offset); 1476 if (offset && (rev > 1)) { 1477 int blocks = RADEON_BIOS8(offset + 3); 1478 index = offset + 4; 1479 while (blocks > 0) { 1480 id = RADEON_BIOS16(index); 1481 index += 2; 1482 switch (id >> 13) { 1483 case 0: 1484 reg = (id & 0x1fff) * 4; 1485 val = RADEON_BIOS32(index); 1486 index += 4; 1487 ErrorF("MMIO: 0x%x 0x%x\n", 1488 (unsigned)reg, (unsigned)val); 1489 OUTREG(reg, val); 1490 break; 1491 case 2: 1492 reg = (id & 0x1fff) * 4; 1493 and_mask = RADEON_BIOS32(index); 1494 index += 4; 1495 or_mask = RADEON_BIOS32(index); 1496 index += 4; 1497 ErrorF("MMIO mask: 0x%x 0x%x 0x%x\n", 1498 (unsigned)reg, (unsigned)and_mask, (unsigned)or_mask); 1499 val = INREG(reg); 1500 val = (val & and_mask) | or_mask; 1501 OUTREG(reg, val); 1502 break; 1503 case 3: 1504 val = RADEON_BIOS16(index); 1505 index += 2; 1506 ErrorF("delay: %u\n", (unsigned)val); 1507 usleep(val); 1508 break; 1509 case 4: 1510 val = RADEON_BIOS16(index); 1511 index += 2; 1512 ErrorF("delay: %u\n", (unsigned)val * 1000); 1513 usleep(val * 1000); 1514 break; 1515 case 6: 1516 index++; 1517 reg = RADEON_BIOS8(index); 1518 index++; 1519 val = RADEON_BIOS8(index); 1520 index++; 1521 ErrorF("i2c write: 0x%x, 0x%x\n", (unsigned)reg, 1522 (unsigned)val); 1523 RADEONDVOWriteByte(dvo->DVOChip, reg, val); 1524 break; 1525 default: 1526 ErrorF("unknown id %d\n", id>>13); 1527 return FALSE; 1528 } 1529 blocks--; 1530 } 1531 return TRUE; 1532 } 1533 } 1534 } 1535 } 1536 } else { 1537 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x58); 1538 if (offset) { 1539 index = offset+10; 1540 id = RADEON_BIOS16(index); 1541 while (id != 0xffff) { 1542 index += 2; 1543 switch(id >> 13) { 1544 case 0: 1545 reg = (id & 0x1fff) * 4; 1546 val = RADEON_BIOS32(index); 1547 index += 4; 1548 ErrorF("MMIO: 0x%x 0x%x\n", 1549 (unsigned)reg, (unsigned)val); 1550 OUTREG(reg, val); 1551 break; 1552 case 2: 1553 reg = (id & 0x1fff) * 4; 1554 and_mask = RADEON_BIOS32(index); 1555 index += 4; 1556 or_mask = RADEON_BIOS32(index); 1557 index += 4; 1558 val = INREG(reg); 1559 val = (val & and_mask) | or_mask; 1560 ErrorF("MMIO mask: 0x%x 0x%x 0x%x\n", 1561 (unsigned)reg, (unsigned)and_mask, (unsigned)or_mask); 1562 OUTREG(reg, val); 1563 break; 1564 case 4: 1565 val = RADEON_BIOS16(index); 1566 index += 2; 1567 ErrorF("delay: %u\n", (unsigned)val); 1568 usleep(val); 1569 break; 1570 case 5: 1571 reg = id & 0x1fff; 1572 and_mask = RADEON_BIOS32(index); 1573 index += 4; 1574 or_mask = RADEON_BIOS32(index); 1575 index += 4; 1576 ErrorF("PLL mask: 0x%x 0x%x 0x%x\n", 1577 (unsigned)reg, (unsigned)and_mask, (unsigned)or_mask); 1578 val = INPLL(pScrn, reg); 1579 val = (val & and_mask) | or_mask; 1580 OUTPLL(pScrn, reg, val); 1581 break; 1582 case 6: 1583 reg = id & 0x1fff; 1584 val = RADEON_BIOS8(index); 1585 index += 1; 1586 ErrorF("i2c write: 0x%x, 0x%x\n", (unsigned)reg, 1587 (unsigned)val); 1588 RADEONDVOWriteByte(dvo->DVOChip, reg, val); 1589 break; 1590 default: 1591 ErrorF("unknown id %d\n", id>>13); 1592 return FALSE; 1593 }; 1594 id = RADEON_BIOS16(index); 1595 } 1596 return TRUE; 1597 } 1598 } 1599 1600 return FALSE; 1601} 1602 1603/* support for init from bios tables 1604 * 1605 * Based heavily on the netbsd radeonfb driver 1606 * Written by Garrett D'Amore 1607 * Copyright (c) 2006 Itronix Inc. 1608 * 1609 */ 1610 1611/* bios table defines */ 1612 1613#define RADEON_TABLE_ENTRY_FLAG_MASK 0xe000 1614#define RADEON_TABLE_ENTRY_INDEX_MASK 0x1fff 1615#define RADEON_TABLE_ENTRY_COMMAND_MASK 0x00ff 1616 1617#define RADEON_TABLE_FLAG_WRITE_INDEXED 0x0000 1618#define RADEON_TABLE_FLAG_WRITE_DIRECT 0x2000 1619#define RADEON_TABLE_FLAG_MASK_INDEXED 0x4000 1620#define RADEON_TABLE_FLAG_MASK_DIRECT 0x6000 1621#define RADEON_TABLE_FLAG_DELAY 0x8000 1622#define RADEON_TABLE_FLAG_SCOMMAND 0xa000 1623 1624#define RADEON_TABLE_SCOMMAND_WAIT_MC_BUSY_MASK 0x03 1625#define RADEON_TABLE_SCOMMAND_WAIT_MEM_PWRUP_COMPLETE 0x08 1626 1627#define RADEON_PLL_FLAG_MASK 0xc0 1628#define RADEON_PLL_INDEX_MASK 0x3f 1629 1630#define RADEON_PLL_FLAG_WRITE 0x00 1631#define RADEON_PLL_FLAG_MASK_BYTE 0x40 1632#define RADEON_PLL_FLAG_WAIT 0x80 1633 1634#define RADEON_PLL_WAIT_150MKS 1 1635#define RADEON_PLL_WAIT_5MS 2 1636#define RADEON_PLL_WAIT_MC_BUSY_MASK 3 1637#define RADEON_PLL_WAIT_DLL_READY_MASK 4 1638#define RADEON_PLL_WAIT_CHK_SET_CLK_PWRMGT_CNTL24 5 1639 1640static uint16_t 1641RADEONValidateBIOSOffset(ScrnInfoPtr pScrn, uint16_t offset) 1642{ 1643 RADEONInfoPtr info = RADEONPTR (pScrn); 1644 uint8_t revision = RADEON_BIOS8(offset - 1); 1645 1646 if (revision > 0x10) { 1647 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1648 "Bad revision %d for BIOS table\n", revision); 1649 return 0; 1650 } 1651 1652 if (offset < 0x60) { 1653 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1654 "Bad offset 0x%x for BIOS Table\n", offset); 1655 return 0; 1656 } 1657 1658 return offset; 1659} 1660 1661Bool 1662RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn) 1663{ 1664 RADEONInfoPtr info = RADEONPTR (pScrn); 1665 uint8_t val; 1666 1667 if (!info->VBIOS) { 1668 return FALSE; 1669 } else { 1670 if (info->IsAtomBios) { 1671 return FALSE; 1672 } else { 1673 info->BiosTable.revision = RADEON_BIOS8(info->ROMHeaderStart + 4); 1674 info->BiosTable.rr1_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x0c); 1675 if (info->BiosTable.rr1_offset) { 1676 info->BiosTable.rr1_offset = 1677 RADEONValidateBIOSOffset(pScrn, info->BiosTable.rr1_offset); 1678 } 1679 if (info->BiosTable.revision > 0x09) 1680 return TRUE; 1681 info->BiosTable.rr2_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x4e); 1682 if (info->BiosTable.rr2_offset) { 1683 info->BiosTable.rr2_offset = 1684 RADEONValidateBIOSOffset(pScrn, info->BiosTable.rr2_offset); 1685 } 1686 info->BiosTable.dyn_clk_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x52); 1687 if (info->BiosTable.dyn_clk_offset) { 1688 info->BiosTable.dyn_clk_offset = 1689 RADEONValidateBIOSOffset(pScrn, info->BiosTable.dyn_clk_offset); 1690 } 1691 info->BiosTable.pll_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x46); 1692 if (info->BiosTable.pll_offset) { 1693 info->BiosTable.pll_offset = 1694 RADEONValidateBIOSOffset(pScrn, info->BiosTable.pll_offset); 1695 } 1696 info->BiosTable.mem_config_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x48); 1697 if (info->BiosTable.mem_config_offset) { 1698 info->BiosTable.mem_config_offset = 1699 RADEONValidateBIOSOffset(pScrn, info->BiosTable.mem_config_offset); 1700 } 1701 if (info->BiosTable.mem_config_offset) { 1702 info->BiosTable.mem_reset_offset = info->BiosTable.mem_config_offset; 1703 if (info->BiosTable.mem_reset_offset) { 1704 while (RADEON_BIOS8(info->BiosTable.mem_reset_offset)) 1705 info->BiosTable.mem_reset_offset++; 1706 info->BiosTable.mem_reset_offset++; 1707 info->BiosTable.mem_reset_offset += 2; 1708 } 1709 } 1710 if (info->BiosTable.mem_config_offset) { 1711 info->BiosTable.short_mem_offset = info->BiosTable.mem_config_offset; 1712 if ((info->BiosTable.short_mem_offset != 0) && 1713 (RADEON_BIOS8(info->BiosTable.short_mem_offset - 2) <= 64)) 1714 info->BiosTable.short_mem_offset += 1715 RADEON_BIOS8(info->BiosTable.short_mem_offset - 3); 1716 } 1717 if (info->BiosTable.rr2_offset) { 1718 info->BiosTable.rr3_offset = info->BiosTable.rr2_offset; 1719 if (info->BiosTable.rr3_offset) { 1720 while ((val = RADEON_BIOS8(info->BiosTable.rr3_offset + 1)) != 0) { 1721 if (val & 0x40) 1722 info->BiosTable.rr3_offset += 10; 1723 else if (val & 0x80) 1724 info->BiosTable.rr3_offset += 4; 1725 else 1726 info->BiosTable.rr3_offset += 6; 1727 } 1728 info->BiosTable.rr3_offset += 2; 1729 } 1730 } 1731 1732 if (info->BiosTable.rr3_offset) { 1733 info->BiosTable.rr4_offset = info->BiosTable.rr3_offset; 1734 if (info->BiosTable.rr4_offset) { 1735 while ((val = RADEON_BIOS8(info->BiosTable.rr4_offset + 1)) != 0) { 1736 if (val & 0x40) 1737 info->BiosTable.rr4_offset += 10; 1738 else if (val & 0x80) 1739 info->BiosTable.rr4_offset += 4; 1740 else 1741 info->BiosTable.rr4_offset += 6; 1742 } 1743 info->BiosTable.rr4_offset += 2; 1744 } 1745 } 1746 1747 if (info->BiosTable.rr3_offset + 1 == info->BiosTable.pll_offset) { 1748 info->BiosTable.rr3_offset = 0; 1749 info->BiosTable.rr4_offset = 0; 1750 } 1751 1752 return TRUE; 1753 1754 } 1755 } 1756} 1757 1758static void 1759RADEONRestoreBIOSRegBlock(ScrnInfoPtr pScrn, uint16_t table_offset) 1760{ 1761 RADEONInfoPtr info = RADEONPTR (pScrn); 1762 unsigned char *RADEONMMIO = info->MMIO; 1763 uint16_t offset = table_offset; 1764 uint16_t value, flag, index, count; 1765 uint32_t andmask, ormask, val, channel_complete_mask; 1766 uint8_t command; 1767 1768 if (offset == 0) 1769 return; 1770 1771 while ((value = RADEON_BIOS16(offset)) != 0) { 1772 flag = value & RADEON_TABLE_ENTRY_FLAG_MASK; 1773 index = value & RADEON_TABLE_ENTRY_INDEX_MASK; 1774 command = value & RADEON_TABLE_ENTRY_COMMAND_MASK; 1775 1776 offset += 2; 1777 1778 switch (flag) { 1779 case RADEON_TABLE_FLAG_WRITE_INDEXED: 1780 val = RADEON_BIOS32(offset); 1781 ErrorF("WRITE INDEXED: 0x%x 0x%x\n", 1782 index, (unsigned)val); 1783 OUTREG(RADEON_MM_INDEX, index); 1784 OUTREG(RADEON_MM_DATA, val); 1785 offset += 4; 1786 break; 1787 1788 case RADEON_TABLE_FLAG_WRITE_DIRECT: 1789 val = RADEON_BIOS32(offset); 1790 ErrorF("WRITE DIRECT: 0x%x 0x%x\n", index, (unsigned)val); 1791 OUTREG(index, val); 1792 offset += 4; 1793 break; 1794 1795 case RADEON_TABLE_FLAG_MASK_INDEXED: 1796 andmask = RADEON_BIOS32(offset); 1797 offset += 4; 1798 ormask = RADEON_BIOS32(offset); 1799 offset += 4; 1800 ErrorF("MASK INDEXED: 0x%x 0x%x 0x%x\n", 1801 index, (unsigned)andmask, (unsigned)ormask); 1802 OUTREG(RADEON_MM_INDEX, index); 1803 val = INREG(RADEON_MM_DATA); 1804 val = (val & andmask) | ormask; 1805 OUTREG(RADEON_MM_DATA, val); 1806 break; 1807 1808 case RADEON_TABLE_FLAG_MASK_DIRECT: 1809 andmask = RADEON_BIOS32(offset); 1810 offset += 4; 1811 ormask = RADEON_BIOS32(offset); 1812 offset += 4; 1813 ErrorF("MASK DIRECT: 0x%x 0x%x 0x%x\n", 1814 index, (unsigned)andmask, (unsigned)ormask); 1815 val = INREG(index); 1816 val = (val & andmask) | ormask; 1817 OUTREG(index, val); 1818 break; 1819 1820 case RADEON_TABLE_FLAG_DELAY: 1821 count = RADEON_BIOS16(offset); 1822 ErrorF("delay: %d\n", count); 1823 usleep(count); 1824 offset += 2; 1825 break; 1826 1827 case RADEON_TABLE_FLAG_SCOMMAND: 1828 ErrorF("SCOMMAND 0x%x\n", command); 1829 switch (command) { 1830 case RADEON_TABLE_SCOMMAND_WAIT_MC_BUSY_MASK: 1831 count = RADEON_BIOS16(offset); 1832 ErrorF("SCOMMAND_WAIT_MC_BUSY_MASK %d\n", count); 1833 while (count--) { 1834 if (!(INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL) & 1835 RADEON_MC_BUSY)) 1836 break; 1837 } 1838 break; 1839 1840 case RADEON_TABLE_SCOMMAND_WAIT_MEM_PWRUP_COMPLETE: 1841 count = RADEON_BIOS16(offset); 1842 ErrorF("SCOMMAND_WAIT_MEM_PWRUP_COMPLETE %d\n", count); 1843 /* may need to take into account how many memory channels 1844 * each card has 1845 */ 1846 if (IS_R300_VARIANT) 1847 channel_complete_mask = R300_MEM_PWRUP_COMPLETE; 1848 else 1849 channel_complete_mask = RADEON_MEM_PWRUP_COMPLETE; 1850 while (count--) { 1851 /* XXX: may need indexed access */ 1852 if ((INREG(RADEON_MEM_STR_CNTL) & 1853 channel_complete_mask) == 1854 channel_complete_mask) 1855 break; 1856 } 1857 break; 1858 1859 } 1860 offset += 2; 1861 break; 1862 } 1863 } 1864} 1865 1866static void 1867RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, uint16_t table_offset) 1868{ 1869 RADEONInfoPtr info = RADEONPTR (pScrn); 1870 unsigned char *RADEONMMIO = info->MMIO; 1871 uint16_t offset = table_offset; 1872 uint16_t count; 1873 uint32_t ormask, val, channel_complete_mask; 1874 uint8_t index; 1875 1876 if (offset == 0) 1877 return; 1878 1879 while ((index = RADEON_BIOS8(offset)) != 0xff) { 1880 offset++; 1881 if (index == 0x0f) { 1882 count = 20000; 1883 ErrorF("MEM_WAIT_MEM_PWRUP_COMPLETE %d\n", count); 1884 /* may need to take into account how many memory channels 1885 * each card has 1886 */ 1887 if (IS_R300_VARIANT) 1888 channel_complete_mask = R300_MEM_PWRUP_COMPLETE; 1889 else 1890 channel_complete_mask = RADEON_MEM_PWRUP_COMPLETE; 1891 while (count--) { 1892 /* XXX: may need indexed access */ 1893 if ((INREG(RADEON_MEM_STR_CNTL) & 1894 channel_complete_mask) == 1895 channel_complete_mask) 1896 break; 1897 } 1898 } else { 1899 ormask = RADEON_BIOS16(offset); 1900 offset += 2; 1901 1902 ErrorF("INDEX RADEON_MEM_SDRAM_MODE_REG %x %x\n", 1903 RADEON_SDRAM_MODE_MASK, (unsigned)ormask); 1904 1905 /* can this use direct access? */ 1906 OUTREG(RADEON_MM_INDEX, RADEON_MEM_SDRAM_MODE_REG); 1907 val = INREG(RADEON_MM_DATA); 1908 val = (val & RADEON_SDRAM_MODE_MASK) | ormask; 1909 OUTREG(RADEON_MM_DATA, val); 1910 1911 ormask = (uint32_t)index << 24; 1912 1913 ErrorF("INDEX RADEON_MEM_SDRAM_MODE_REG %x %x\n", 1914 RADEON_B3MEM_RESET_MASK, (unsigned)ormask); 1915 1916 /* can this use direct access? */ 1917 OUTREG(RADEON_MM_INDEX, RADEON_MEM_SDRAM_MODE_REG); 1918 val = INREG(RADEON_MM_DATA); 1919 val = (val & RADEON_B3MEM_RESET_MASK) | ormask; 1920 OUTREG(RADEON_MM_DATA, val); 1921 } 1922 } 1923} 1924 1925static void 1926RADEONRestoreBIOSPllBlock(ScrnInfoPtr pScrn, uint16_t table_offset) 1927{ 1928 RADEONInfoPtr info = RADEONPTR (pScrn); 1929 uint16_t offset = table_offset; 1930 uint8_t index, shift; 1931 uint32_t andmask, ormask, val, clk_pwrmgt_cntl; 1932 uint16_t count; 1933 1934 if (offset == 0) 1935 return; 1936 1937 while ((index = RADEON_BIOS8(offset)) != 0) { 1938 offset++; 1939 1940 switch (index & RADEON_PLL_FLAG_MASK) { 1941 case RADEON_PLL_FLAG_WAIT: 1942 switch (index & RADEON_PLL_INDEX_MASK) { 1943 case RADEON_PLL_WAIT_150MKS: 1944 ErrorF("delay: 150 us\n"); 1945 usleep(150); 1946 break; 1947 case RADEON_PLL_WAIT_5MS: 1948 ErrorF("delay: 5 ms\n"); 1949 usleep(5000); 1950 break; 1951 1952 case RADEON_PLL_WAIT_MC_BUSY_MASK: 1953 count = 1000; 1954 ErrorF("PLL_WAIT_MC_BUSY_MASK %d\n", count); 1955 while (count--) { 1956 if (!(INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL) & 1957 RADEON_MC_BUSY)) 1958 break; 1959 } 1960 break; 1961 1962 case RADEON_PLL_WAIT_DLL_READY_MASK: 1963 count = 1000; 1964 ErrorF("PLL_WAIT_DLL_READY_MASK %d\n", count); 1965 while (count--) { 1966 if (INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL) & 1967 RADEON_DLL_READY) 1968 break; 1969 } 1970 break; 1971 1972 case RADEON_PLL_WAIT_CHK_SET_CLK_PWRMGT_CNTL24: 1973 ErrorF("PLL_WAIT_CHK_SET_CLK_PWRMGT_CNTL24\n"); 1974 clk_pwrmgt_cntl = INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL); 1975 if (clk_pwrmgt_cntl & RADEON_CG_NO1_DEBUG_0) { 1976 val = INPLL(pScrn, RADEON_MCLK_CNTL); 1977 /* is this right? */ 1978 val = (val & 0xFFFF0000) | 0x1111; /* seems like we should clear these... */ 1979 OUTPLL(pScrn, RADEON_MCLK_CNTL, val); 1980 usleep(10000); 1981 OUTPLL(pScrn, RADEON_CLK_PWRMGT_CNTL, 1982 clk_pwrmgt_cntl & ~RADEON_CG_NO1_DEBUG_0); 1983 usleep(10000); 1984 } 1985 break; 1986 } 1987 break; 1988 1989 case RADEON_PLL_FLAG_MASK_BYTE: 1990 shift = RADEON_BIOS8(offset) * 8; 1991 offset++; 1992 1993 andmask = 1994 (((uint32_t)RADEON_BIOS8(offset)) << shift) | 1995 ~((uint32_t)0xff << shift); 1996 offset++; 1997 1998 ormask = ((uint32_t)RADEON_BIOS8(offset)) << shift; 1999 offset++; 2000 2001 ErrorF("PLL_MASK_BYTE 0x%x 0x%x 0x%x 0x%x\n", 2002 index, shift, (unsigned)andmask, (unsigned)ormask); 2003 val = INPLL(pScrn, index); 2004 val = (val & andmask) | ormask; 2005 OUTPLL(pScrn, index, val); 2006 break; 2007 2008 case RADEON_PLL_FLAG_WRITE: 2009 val = RADEON_BIOS32(offset); 2010 ErrorF("PLL_WRITE 0x%x 0x%x\n", index, (unsigned)val); 2011 OUTPLL(pScrn, index, val); 2012 offset += 4; 2013 break; 2014 } 2015 } 2016} 2017 2018Bool 2019RADEONPostCardFromBIOSTables(ScrnInfoPtr pScrn) 2020{ 2021 RADEONInfoPtr info = RADEONPTR (pScrn); 2022 2023 if (!info->VBIOS) { 2024 return FALSE; 2025 } else { 2026 if (info->IsAtomBios) { 2027 return FALSE; 2028 } else { 2029 if (info->BiosTable.rr1_offset) { 2030 ErrorF("rr1 restore, 0x%x\n", info->BiosTable.rr1_offset); 2031 RADEONRestoreBIOSRegBlock(pScrn, info->BiosTable.rr1_offset); 2032 } 2033 if (info->BiosTable.revision < 0x09) { 2034 if (info->BiosTable.pll_offset) { 2035 ErrorF("pll restore, 0x%x\n", info->BiosTable.pll_offset); 2036 RADEONRestoreBIOSPllBlock(pScrn, info->BiosTable.pll_offset); 2037 } 2038 if (info->BiosTable.rr2_offset) { 2039 ErrorF("rr2 restore, 0x%x\n", info->BiosTable.rr2_offset); 2040 RADEONRestoreBIOSRegBlock(pScrn, info->BiosTable.rr2_offset); 2041 } 2042 if (info->BiosTable.rr4_offset) { 2043 ErrorF("rr4 restore, 0x%x\n", info->BiosTable.rr4_offset); 2044 RADEONRestoreBIOSRegBlock(pScrn, info->BiosTable.rr4_offset); 2045 } 2046 if (info->BiosTable.mem_reset_offset) { 2047 ErrorF("mem reset restore, 0x%x\n", info->BiosTable.mem_reset_offset); 2048 RADEONRestoreBIOSMemBlock(pScrn, info->BiosTable.mem_reset_offset); 2049 } 2050 if (info->BiosTable.rr3_offset) { 2051 ErrorF("rr3 restore, 0x%x\n", info->BiosTable.rr3_offset); 2052 RADEONRestoreBIOSRegBlock(pScrn, info->BiosTable.rr3_offset); 2053 } 2054 if (info->BiosTable.dyn_clk_offset) { 2055 ErrorF("dyn_clk restore, 0x%x\n", info->BiosTable.dyn_clk_offset); 2056 RADEONRestoreBIOSPllBlock(pScrn, info->BiosTable.dyn_clk_offset); 2057 } 2058 } 2059 } 2060 } 2061 return TRUE; 2062} 2063