radeon_bios.c revision c503f109
1/* 2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario 3 * 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining 7 * a copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation on the rights to use, copy, modify, merge, 10 * publish, distribute, sublicense, and/or sell copies of the Software, 11 * and to permit persons to whom the Software is furnished to do so, 12 * subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial 16 * portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 21 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 22 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 * DEALINGS IN THE SOFTWARE. 26 */ 27 28#ifdef HAVE_CONFIG_H 29#include "config.h" 30#endif 31 32#include <string.h> 33 34#include "xf86.h" 35#include "xf86_OSproc.h" 36 37#include "xf86PciInfo.h" 38#include "radeon.h" 39#include "radeon_reg.h" 40#include "radeon_macros.h" 41#include "radeon_probe.h" 42#include "radeon_atombios.h" 43#include "vbe.h" 44 45typedef enum 46{ 47 DDC_NONE_DETECTED, 48 DDC_MONID, 49 DDC_DVI, 50 DDC_VGA, 51 DDC_CRT2, 52 DDC_LCD, 53 DDC_GPIO, 54} RADEONLegacyDDCType; 55 56typedef enum 57{ 58 CONNECTOR_NONE_LEGACY, 59 CONNECTOR_PROPRIETARY_LEGACY, 60 CONNECTOR_CRT_LEGACY, 61 CONNECTOR_DVI_I_LEGACY, 62 CONNECTOR_DVI_D_LEGACY, 63 CONNECTOR_CTV_LEGACY, 64 CONNECTOR_STV_LEGACY, 65 CONNECTOR_UNSUPPORTED_LEGACY 66} RADEONLegacyConnectorType; 67 68static Bool 69radeon_read_bios(ScrnInfoPtr pScrn) 70{ 71 RADEONInfoPtr info = RADEONPTR(pScrn); 72 73#ifdef XSERVER_LIBPCIACCESS 74 if (pci_device_read_rom(info->PciInfo, info->VBIOS)) { 75 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 76 "Failed to read PCI ROM!\n"); 77 return FALSE; 78 } 79#else 80 xf86ReadPciBIOS(0, info->PciTag, 0, info->VBIOS, RADEON_VBIOS_SIZE); 81 if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) { 82 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 83 "Video BIOS not detected in PCI space!\n"); 84 if (xf86IsEntityPrimary(info->pEnt->index)) { 85 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 86 "Attempting to read Video BIOS from " 87 "legacy ISA space!\n"); 88 info->BIOSAddr = 0x000c0000; 89 xf86ReadDomainMemory(info->PciTag, info->BIOSAddr, 90 RADEON_VBIOS_SIZE, info->VBIOS); 91 } 92 } 93#endif 94 if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) 95 return FALSE; 96 else 97 return TRUE; 98} 99 100static Bool 101radeon_read_disabled_bios(ScrnInfoPtr pScrn) 102{ 103 RADEONInfoPtr info = RADEONPTR(pScrn); 104 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 105 unsigned char *RADEONMMIO = info->MMIO; 106 Bool ret; 107 108 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Attempting to read un-POSTed bios\n"); 109 110 if (info->ChipFamily >= CHIP_FAMILY_R600) { 111 uint32_t viph_control = INREG(RADEON_VIPH_CONTROL); 112 uint32_t bus_cntl = INREG(RADEON_BUS_CNTL); 113 uint32_t d1vga_control = INREG(AVIVO_D1VGA_CONTROL); 114 uint32_t d2vga_control = INREG(AVIVO_D2VGA_CONTROL); 115 uint32_t vga_render_control = INREG(AVIVO_VGA_RENDER_CONTROL); 116 uint32_t rom_cntl = INREG(R600_ROM_CNTL); 117 uint32_t general_pwrmgt = INREG(R600_GENERAL_PWRMGT); 118 uint32_t low_vid_lower_gpio_cntl = INREG(R600_LOW_VID_LOWER_GPIO_CNTL); 119 uint32_t medium_vid_lower_gpio_cntl = INREG(R600_MEDIUM_VID_LOWER_GPIO_CNTL); 120 uint32_t high_vid_lower_gpio_cntl = INREG(R600_HIGH_VID_LOWER_GPIO_CNTL); 121 uint32_t ctxsw_vid_lower_gpio_cntl = INREG(R600_CTXSW_VID_LOWER_GPIO_CNTL); 122 uint32_t lower_gpio_enable = INREG(R600_LOWER_GPIO_ENABLE); 123 124 /* disable VIP */ 125 OUTREG(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 126 127 /* enable the rom */ 128 OUTREG(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 129 130 /* Disable VGA mode */ 131 OUTREG(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 132 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 133 OUTREG(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 134 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 135 OUTREG(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 136 137 OUTREG(R600_ROM_CNTL, ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | 138 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | 139 R600_SCK_OVERWRITE)); 140 141 OUTREG(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 142 143 OUTREG(R600_LOW_VID_LOWER_GPIO_CNTL, (low_vid_lower_gpio_cntl & ~0x400)); 144 145 OUTREG(R600_MEDIUM_VID_LOWER_GPIO_CNTL, (medium_vid_lower_gpio_cntl & ~0x400)); 146 147 OUTREG(R600_HIGH_VID_LOWER_GPIO_CNTL, (high_vid_lower_gpio_cntl & ~0x400)); 148 149 OUTREG(R600_CTXSW_VID_LOWER_GPIO_CNTL, (ctxsw_vid_lower_gpio_cntl & ~0x400)); 150 151 OUTREG(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); 152 153 ret = radeon_read_bios(pScrn); 154 155 /* restore regs */ 156 OUTREG(RADEON_VIPH_CONTROL, viph_control); 157 OUTREG(RADEON_BUS_CNTL, bus_cntl); 158 OUTREG(AVIVO_D1VGA_CONTROL, d1vga_control); 159 OUTREG(AVIVO_D2VGA_CONTROL, d2vga_control); 160 OUTREG(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 161 OUTREG(R600_ROM_CNTL, rom_cntl); 162 OUTREG(R600_GENERAL_PWRMGT, general_pwrmgt); 163 OUTREG(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); 164 OUTREG(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); 165 OUTREG(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); 166 OUTREG(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); 167 OUTREG(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 168 169 } else if (info->ChipFamily >= CHIP_FAMILY_RV515) { 170 uint32_t seprom_cntl1 = INREG(RADEON_SEPROM_CNTL1); 171 uint32_t viph_control = INREG(RADEON_VIPH_CONTROL); 172 uint32_t bus_cntl = INREG(RADEON_BUS_CNTL); 173 uint32_t d1vga_control = INREG(AVIVO_D1VGA_CONTROL); 174 uint32_t d2vga_control = INREG(AVIVO_D2VGA_CONTROL); 175 uint32_t vga_render_control = INREG(AVIVO_VGA_RENDER_CONTROL); 176 uint32_t gpiopad_a = INREG(RADEON_GPIOPAD_A); 177 uint32_t gpiopad_en = INREG(RADEON_GPIOPAD_EN); 178 uint32_t gpiopad_mask = INREG(RADEON_GPIOPAD_MASK); 179 180 OUTREG(RADEON_SEPROM_CNTL1, ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 181 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 182 183 OUTREG(RADEON_GPIOPAD_A, 0); 184 OUTREG(RADEON_GPIOPAD_EN, 0); 185 OUTREG(RADEON_GPIOPAD_MASK, 0); 186 187 /* disable VIP */ 188 OUTREG(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 189 190 /* enable the rom */ 191 OUTREG(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 192 193 /* Disable VGA mode */ 194 OUTREG(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 195 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 196 OUTREG(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 197 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 198 OUTREG(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 199 200 ret = radeon_read_bios(pScrn); 201 202 /* restore regs */ 203 OUTREG(RADEON_SEPROM_CNTL1, seprom_cntl1); 204 OUTREG(RADEON_VIPH_CONTROL, viph_control); 205 OUTREG(RADEON_BUS_CNTL, bus_cntl); 206 OUTREG(AVIVO_D1VGA_CONTROL, d1vga_control); 207 OUTREG(AVIVO_D2VGA_CONTROL, d2vga_control); 208 OUTREG(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 209 OUTREG(RADEON_GPIOPAD_A, gpiopad_a); 210 OUTREG(RADEON_GPIOPAD_EN, gpiopad_en); 211 OUTREG(RADEON_GPIOPAD_MASK, gpiopad_mask); 212 213 } else { 214 uint32_t seprom_cntl1 = INREG(RADEON_SEPROM_CNTL1); 215 uint32_t viph_control = INREG(RADEON_VIPH_CONTROL); 216 uint32_t bus_cntl = INREG(RADEON_BUS_CNTL); 217 uint32_t crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); 218 uint32_t crtc2_gen_cntl = 0; 219 uint32_t crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL); 220 uint32_t fp2_gen_cntl = 0; 221 222 if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) 223 fp2_gen_cntl = INREG(RADEON_FP2_GEN_CNTL); 224 225 if (pRADEONEnt->HasCRTC2) 226 crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); 227 228 OUTREG(RADEON_SEPROM_CNTL1, ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 229 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 230 231 /* disable VIP */ 232 OUTREG(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 233 234 /* enable the rom */ 235 OUTREG(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 236 237 /* Turn off mem requests and CRTC for both controllers */ 238 OUTREG(RADEON_CRTC_GEN_CNTL, ((crtc_gen_cntl & ~RADEON_CRTC_EN) | 239 (RADEON_CRTC_DISP_REQ_EN_B | 240 RADEON_CRTC_EXT_DISP_EN))); 241 if (pRADEONEnt->HasCRTC2) 242 OUTREG(RADEON_CRTC2_GEN_CNTL, ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | 243 RADEON_CRTC2_DISP_REQ_EN_B)); 244 245 /* Turn off CRTC */ 246 OUTREG(RADEON_CRTC_EXT_CNTL, ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | 247 (RADEON_CRTC_SYNC_TRISTAT | 248 RADEON_CRTC_DISPLAY_DIS))); 249 250 if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) 251 OUTREG(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); 252 253 ret = radeon_read_bios(pScrn); 254 255 /* restore regs */ 256 OUTREG(RADEON_SEPROM_CNTL1, seprom_cntl1); 257 OUTREG(RADEON_VIPH_CONTROL, viph_control); 258 OUTREG(RADEON_BUS_CNTL, bus_cntl); 259 OUTREG(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 260 if (pRADEONEnt->HasCRTC2) 261 OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 262 OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 263 if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) 264 OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 265 } 266 return ret; 267} 268 269Bool 270radeon_card_posted(ScrnInfoPtr pScrn) 271{ 272 RADEONInfoPtr info = RADEONPTR(pScrn); 273 unsigned char *RADEONMMIO = info->MMIO; 274 uint32_t reg; 275 276 /* first check CRTCs */ 277 if (IS_AVIVO_VARIANT) { 278 reg = INREG(AVIVO_D1CRTC_CONTROL) | INREG(AVIVO_D2CRTC_CONTROL); 279 if (reg & AVIVO_CRTC_EN) 280 return TRUE; 281 } else { 282 reg = INREG(RADEON_CRTC_GEN_CNTL) | INREG(RADEON_CRTC2_GEN_CNTL); 283 if (reg & RADEON_CRTC_EN) 284 return TRUE; 285 } 286 287 /* then check MEM_SIZE, in case something turned the crtcs off */ 288 if (info->ChipFamily >= CHIP_FAMILY_R600) 289 reg = INREG(R600_CONFIG_MEMSIZE); 290 else 291 reg = INREG(RADEON_CONFIG_MEMSIZE); 292 293 if (reg) 294 return TRUE; 295 296 return FALSE; 297} 298 299/* Read the Video BIOS block and the FP registers (if applicable). */ 300Bool 301RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) 302{ 303 RADEONInfoPtr info = RADEONPTR(pScrn); 304 int tmp; 305 unsigned short dptr; 306 307#ifdef XSERVER_LIBPCIACCESS 308 int size = info->PciInfo->rom_size > RADEON_VBIOS_SIZE ? info->PciInfo->rom_size : RADEON_VBIOS_SIZE; 309 info->VBIOS = xalloc(size); 310#else 311 info->VBIOS = xalloc(RADEON_VBIOS_SIZE); 312#endif 313 if (!info->VBIOS) { 314 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 315 "Cannot allocate space for hold Video BIOS!\n"); 316 return FALSE; 317 } else { 318 if (pInt10) { 319 info->BIOSAddr = pInt10->BIOSseg << 4; 320 (void)memcpy(info->VBIOS, xf86int10Addr(pInt10, info->BIOSAddr), 321 RADEON_VBIOS_SIZE); 322 } else if (!radeon_read_bios(pScrn)) 323 (void)radeon_read_disabled_bios(pScrn); 324 } 325 326 if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) { 327 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 328 "Unrecognized BIOS signature, BIOS data will not be used\n"); 329 xfree (info->VBIOS); 330 info->VBIOS = NULL; 331 return FALSE; 332 } 333 334 /* Verify it's an x86 BIOS not OF firmware, copied from radeonfb */ 335 dptr = RADEON_BIOS16(0x18); 336 /* If PCI data signature is wrong assume x86 video BIOS anyway */ 337 if (RADEON_BIOS32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) { 338 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 339 "ROM PCI data signature incorrect, ignoring\n"); 340 } 341 else if (info->VBIOS[dptr + 0x14] != 0x0) { 342 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 343 "Not an x86 BIOS ROM image, BIOS data will not be used\n"); 344 xfree (info->VBIOS); 345 info->VBIOS = NULL; 346 return FALSE; 347 } 348 349 if (info->VBIOS) info->ROMHeaderStart = RADEON_BIOS16(0x48); 350 351 if(!info->ROMHeaderStart) { 352 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 353 "Invalid ROM pointer, BIOS data will not be used\n"); 354 xfree (info->VBIOS); 355 info->VBIOS = NULL; 356 return FALSE; 357 } 358 359 tmp = info->ROMHeaderStart + 4; 360 if ((RADEON_BIOS8(tmp) == 'A' && 361 RADEON_BIOS8(tmp+1) == 'T' && 362 RADEON_BIOS8(tmp+2) == 'O' && 363 RADEON_BIOS8(tmp+3) == 'M') || 364 (RADEON_BIOS8(tmp) == 'M' && 365 RADEON_BIOS8(tmp+1) == 'O' && 366 RADEON_BIOS8(tmp+2) == 'T' && 367 RADEON_BIOS8(tmp+3) == 'A')) 368 info->IsAtomBios = TRUE; 369 else 370 info->IsAtomBios = FALSE; 371 372 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s BIOS detected\n", 373 info->IsAtomBios ? "ATOM":"Legacy"); 374 375 if (info->IsAtomBios) { 376 AtomBiosArgRec atomBiosArg; 377 378 if (RHDAtomBiosFunc(pScrn->scrnIndex, NULL, ATOMBIOS_INIT, &atomBiosArg) 379 == ATOM_SUCCESS) { 380 info->atomBIOS = atomBiosArg.atomhandle; 381 } 382 383 atomBiosArg.fb.start = info->FbFreeStart; 384 atomBiosArg.fb.size = info->FbFreeSize; 385 if (RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, ATOMBIOS_ALLOCATE_FB_SCRATCH, 386 &atomBiosArg) == ATOM_SUCCESS) { 387 388 info->FbFreeStart = atomBiosArg.fb.start; 389 info->FbFreeSize = atomBiosArg.fb.size; 390 } 391 392 RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, GET_DEFAULT_ENGINE_CLOCK, 393 &atomBiosArg); 394 RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, GET_DEFAULT_MEMORY_CLOCK, 395 &atomBiosArg); 396 RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, 397 GET_MAX_PIXEL_CLOCK_PLL_OUTPUT, &atomBiosArg); 398 RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, 399 GET_MIN_PIXEL_CLOCK_PLL_OUTPUT, &atomBiosArg); 400 RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, 401 GET_MAX_PIXEL_CLOCK_PLL_INPUT, &atomBiosArg); 402 RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, 403 GET_MIN_PIXEL_CLOCK_PLL_INPUT, &atomBiosArg); 404 RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, 405 GET_MAX_PIXEL_CLK, &atomBiosArg); 406 RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, 407 GET_REF_CLOCK, &atomBiosArg); 408 409 info->MasterDataStart = RADEON_BIOS16 (info->ROMHeaderStart + 32); 410 } 411 412 /* We are a bit too quick at using this "unposted" to re-post the 413 * card. This causes some problems with VT switch on some machines, 414 * so let's work around this for now by only POSTing if none of the 415 * CRTCs are enabled 416 */ 417 if ((!radeon_card_posted(pScrn)) && info->VBIOS) { 418 if (info->IsAtomBios) { 419 if (!rhdAtomASICInit(info->atomBIOS)) 420 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 421 "%s: AsicInit failed.\n",__func__); 422 } else { 423#if 0 424 /* FIX ME */ 425 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Attempting to POST via legacy BIOS tables\n"); 426 RADEONGetBIOSInitTableOffsets(pScrn); 427 RADEONPostCardFromBIOSTables(pScrn); 428#endif 429 } 430 } 431 432 return TRUE; 433} 434 435static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn) 436{ 437 RADEONInfoPtr info = RADEONPTR (pScrn); 438 439 if (!info->VBIOS) return FALSE; 440 441 if (RADEONGetATOMConnectorInfoFromBIOSObject(pScrn)) 442 return TRUE; 443 444 if (RADEONGetATOMConnectorInfoFromBIOSConnectorTable(pScrn)) 445 return TRUE; 446 447 return FALSE; 448} 449 450static void RADEONApplyLegacyQuirks(ScrnInfoPtr pScrn, int index) 451{ 452 RADEONInfoPtr info = RADEONPTR (pScrn); 453 454 /* XPRESS DDC quirks */ 455 if ((info->ChipFamily == CHIP_FAMILY_RS400 || 456 info->ChipFamily == CHIP_FAMILY_RS480) && 457 info->BiosConnector[index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) { 458 info->BiosConnector[index].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); 459 } else if ((info->ChipFamily == CHIP_FAMILY_RS400 || 460 info->ChipFamily == CHIP_FAMILY_RS480) && 461 info->BiosConnector[index].ddc_i2c.mask_clk_reg == RADEON_GPIO_MONID) { 462 info->BiosConnector[index].ddc_i2c.valid = TRUE; 463 info->BiosConnector[index].ddc_i2c.mask_clk_mask = (0x20 << 8); 464 info->BiosConnector[index].ddc_i2c.mask_data_mask = 0x80; 465 info->BiosConnector[index].ddc_i2c.a_clk_mask = (0x20 << 8); 466 info->BiosConnector[index].ddc_i2c.a_data_mask = 0x80; 467 info->BiosConnector[index].ddc_i2c.put_clk_mask = (0x20 << 8); 468 info->BiosConnector[index].ddc_i2c.put_data_mask = 0x80; 469 info->BiosConnector[index].ddc_i2c.get_clk_mask = (0x20 << 8); 470 info->BiosConnector[index].ddc_i2c.get_data_mask = 0x80; 471 info->BiosConnector[index].ddc_i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; 472 info->BiosConnector[index].ddc_i2c.mask_data_reg = RADEON_GPIOPAD_MASK; 473 info->BiosConnector[index].ddc_i2c.a_clk_reg = RADEON_GPIOPAD_A; 474 info->BiosConnector[index].ddc_i2c.a_data_reg = RADEON_GPIOPAD_A; 475 info->BiosConnector[index].ddc_i2c.put_clk_reg = RADEON_GPIOPAD_EN; 476 info->BiosConnector[index].ddc_i2c.put_data_reg = RADEON_GPIOPAD_EN; 477 info->BiosConnector[index].ddc_i2c.get_clk_reg = RADEON_LCD_GPIO_Y_REG; 478 info->BiosConnector[index].ddc_i2c.get_data_reg = RADEON_LCD_GPIO_Y_REG; 479 } 480 481 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, 482 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ 483 if (info->Chipset == PCI_CHIP_RN50_515E && 484 PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1014) { 485 if (info->BiosConnector[index].ConnectorType == CONNECTOR_VGA && 486 info->BiosConnector[index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) { 487 info->BiosConnector[index].valid = FALSE; 488 } 489 } 490 491 /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */ 492 if (info->Chipset == PCI_CHIP_RV100_QY && 493 PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1002 && 494 PCI_SUB_DEVICE_ID(info->PciInfo) == 0x013a) { 495 if (info->BiosConnector[index].ConnectorType == CONNECTOR_DVI_I) { 496 info->BiosConnector[index].ConnectorType = CONNECTOR_VGA; 497 } 498 } 499 500 /* X300 card with extra non-existent DVI port */ 501 if (info->Chipset == PCI_CHIP_RV370_5B60 && 502 PCI_SUB_VENDOR_ID(info->PciInfo) == 0x17af && 503 PCI_SUB_DEVICE_ID(info->PciInfo) == 0x201e && 504 index == 2) { 505 if (info->BiosConnector[index].ConnectorType == CONNECTOR_DVI_I) { 506 info->BiosConnector[index].valid = FALSE; 507 } 508 } 509 510 /* r200 card with primary dac routed to both VGA and DVI - disable load detection 511 * otherwise you end up detecing load if either port is attached 512 */ 513 if (info->Chipset == PCI_CHIP_R200_QL && 514 PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1569 && 515 PCI_SUB_DEVICE_ID(info->PciInfo) == 0x514c && 516 (info->BiosConnector[index].devices & ATOM_DEVICE_CRT1_SUPPORT)) { 517 info->BiosConnector[index].load_detection = FALSE; 518 } 519 520} 521 522static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) 523{ 524 RADEONInfoPtr info = RADEONPTR (pScrn); 525 int offset, i, entry, tmp, tmp0, tmp1; 526 RADEONLegacyDDCType DDCType; 527 RADEONLegacyConnectorType ConnectorType; 528 529 if (!info->VBIOS) return FALSE; 530 531 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x50); 532 if (offset) { 533 for (i = 0; i < 4; i++) { 534 entry = offset + 2 + i*2; 535 536 if (!RADEON_BIOS16(entry)) { 537 break; 538 } 539 info->BiosConnector[i].valid = TRUE; 540 tmp = RADEON_BIOS16(entry); 541 info->BiosConnector[i].ConnectorType = (tmp >> 12) & 0xf; 542 ConnectorType = (tmp >> 12) & 0xf; 543 switch (ConnectorType) { 544 case CONNECTOR_PROPRIETARY_LEGACY: 545 info->BiosConnector[i].ConnectorType = CONNECTOR_DVI_D; 546 if ((tmp >> 4) & 0x1) { 547 info->BiosConnector[i].devices |= ATOM_DEVICE_DFP2_SUPPORT; 548 if (!radeon_add_encoder(pScrn, 549 radeon_get_encoder_id_from_supported_device(pScrn, 550 ATOM_DEVICE_DFP2_SUPPORT, 551 0), 552 ATOM_DEVICE_DFP2_SUPPORT)) 553 return FALSE; 554 } else { 555 info->BiosConnector[i].devices |= ATOM_DEVICE_DFP1_SUPPORT; 556 if (!radeon_add_encoder(pScrn, 557 radeon_get_encoder_id_from_supported_device(pScrn, 558 ATOM_DEVICE_DFP1_SUPPORT, 559 0), 560 ATOM_DEVICE_DFP1_SUPPORT)) 561 return FALSE; 562 } 563 break; 564 case CONNECTOR_CRT_LEGACY: 565 info->BiosConnector[i].ConnectorType = CONNECTOR_VGA; 566 if (tmp & 0x1) { 567 info->BiosConnector[i].load_detection = FALSE; 568 info->BiosConnector[i].devices |= ATOM_DEVICE_CRT2_SUPPORT; 569 if (!radeon_add_encoder(pScrn, 570 radeon_get_encoder_id_from_supported_device(pScrn, 571 ATOM_DEVICE_CRT2_SUPPORT, 572 2), 573 ATOM_DEVICE_CRT2_SUPPORT)) 574 return FALSE; 575 } else { 576 info->BiosConnector[i].load_detection = TRUE; 577 info->BiosConnector[i].devices |= ATOM_DEVICE_CRT1_SUPPORT; 578 if (!radeon_add_encoder(pScrn, 579 radeon_get_encoder_id_from_supported_device(pScrn, 580 ATOM_DEVICE_CRT1_SUPPORT, 581 1), 582 ATOM_DEVICE_CRT1_SUPPORT)) 583 return FALSE; 584 } 585 break; 586 case CONNECTOR_DVI_I_LEGACY: 587 info->BiosConnector[i].ConnectorType = CONNECTOR_DVI_I; 588 if (tmp & 0x1) { 589 info->BiosConnector[i].load_detection = FALSE; 590 info->BiosConnector[i].devices |= ATOM_DEVICE_CRT2_SUPPORT; 591 if (!radeon_add_encoder(pScrn, 592 radeon_get_encoder_id_from_supported_device(pScrn, 593 ATOM_DEVICE_CRT2_SUPPORT, 594 2), 595 ATOM_DEVICE_CRT2_SUPPORT)) 596 return FALSE; 597 } else { 598 info->BiosConnector[i].load_detection = TRUE; 599 info->BiosConnector[i].devices |= ATOM_DEVICE_CRT1_SUPPORT; 600 if (!radeon_add_encoder(pScrn, 601 radeon_get_encoder_id_from_supported_device(pScrn, 602 ATOM_DEVICE_CRT1_SUPPORT, 603 1), 604 ATOM_DEVICE_CRT1_SUPPORT)) 605 return FALSE; 606 } 607 if ((tmp >> 4) & 0x1) { 608 info->BiosConnector[i].devices |= ATOM_DEVICE_DFP2_SUPPORT; 609 if (!radeon_add_encoder(pScrn, 610 radeon_get_encoder_id_from_supported_device(pScrn, 611 ATOM_DEVICE_DFP2_SUPPORT, 612 0), 613 ATOM_DEVICE_DFP2_SUPPORT)) 614 return FALSE; 615 } else { 616 info->BiosConnector[i].devices |= ATOM_DEVICE_DFP1_SUPPORT; 617 if (!radeon_add_encoder(pScrn, 618 radeon_get_encoder_id_from_supported_device(pScrn, 619 ATOM_DEVICE_DFP1_SUPPORT, 620 0), 621 ATOM_DEVICE_DFP1_SUPPORT)) 622 return FALSE; 623 } 624 break; 625 case CONNECTOR_DVI_D_LEGACY: 626 info->BiosConnector[i].ConnectorType = CONNECTOR_DVI_D; 627 if ((tmp >> 4) & 0x1) { 628 info->BiosConnector[i].devices |= ATOM_DEVICE_DFP2_SUPPORT; 629 if (!radeon_add_encoder(pScrn, 630 radeon_get_encoder_id_from_supported_device(pScrn, 631 ATOM_DEVICE_DFP2_SUPPORT, 632 0), 633 ATOM_DEVICE_DFP2_SUPPORT)) 634 return FALSE; 635 } else { 636 info->BiosConnector[i].devices |= ATOM_DEVICE_DFP1_SUPPORT; 637 if (!radeon_add_encoder(pScrn, 638 radeon_get_encoder_id_from_supported_device(pScrn, 639 ATOM_DEVICE_DFP1_SUPPORT, 640 0), 641 ATOM_DEVICE_DFP1_SUPPORT)) 642 return FALSE; 643 } 644 break; 645 case CONNECTOR_CTV_LEGACY: 646 info->BiosConnector[i].ConnectorType = CONNECTOR_CTV; 647 info->BiosConnector[i].load_detection = FALSE; 648 info->BiosConnector[i].devices = ATOM_DEVICE_TV1_SUPPORT; 649 if (!radeon_add_encoder(pScrn, 650 radeon_get_encoder_id_from_supported_device(pScrn, 651 ATOM_DEVICE_TV1_SUPPORT, 652 2), 653 ATOM_DEVICE_TV1_SUPPORT)) 654 return FALSE; 655 break; 656 case CONNECTOR_STV_LEGACY: 657 info->BiosConnector[i].ConnectorType = CONNECTOR_STV; 658 info->BiosConnector[i].load_detection = FALSE; 659 info->BiosConnector[i].devices = ATOM_DEVICE_TV1_SUPPORT; 660 if (!radeon_add_encoder(pScrn, 661 radeon_get_encoder_id_from_supported_device(pScrn, 662 ATOM_DEVICE_TV1_SUPPORT, 663 2), 664 ATOM_DEVICE_TV1_SUPPORT)) 665 return FALSE; 666 break; 667 default: 668 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown Connector Type: %d\n", ConnectorType); 669 info->BiosConnector[i].valid = FALSE; 670 break; 671 } 672 673 info->BiosConnector[i].ddc_i2c.valid = FALSE; 674 675 DDCType = (tmp >> 8) & 0xf; 676 switch (DDCType) { 677 case DDC_MONID: 678 info->BiosConnector[i].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); 679 break; 680 case DDC_DVI: 681 info->BiosConnector[i].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); 682 break; 683 case DDC_VGA: 684 info->BiosConnector[i].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); 685 break; 686 case DDC_CRT2: 687 info->BiosConnector[i].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); 688 break; 689 default: 690 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown DDC Type: %d\n", DDCType); 691 break; 692 } 693 694 RADEONApplyLegacyQuirks(pScrn, i); 695 696 } 697 } else { 698 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No Connector Info Table found!\n"); 699 700 /* old radeons and r128 didn't use connector tables you just check 701 * for LVDS, DVI, TV, etc. tables 702 */ 703 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x34); 704 if (offset) { 705 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 706 "Found DFP table, assuming DVI connector\n"); 707 info->BiosConnector[0].valid = TRUE; 708 info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I; 709 info->BiosConnector[0].load_detection = TRUE; 710 info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); 711 info->BiosConnector[0].devices = ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_DFP1_SUPPORT; 712 if (!radeon_add_encoder(pScrn, 713 radeon_get_encoder_id_from_supported_device(pScrn, 714 ATOM_DEVICE_DFP1_SUPPORT, 715 0), 716 ATOM_DEVICE_DFP1_SUPPORT)) 717 return FALSE; 718 if (!radeon_add_encoder(pScrn, 719 radeon_get_encoder_id_from_supported_device(pScrn, 720 ATOM_DEVICE_CRT1_SUPPORT, 721 1), 722 ATOM_DEVICE_CRT1_SUPPORT)) 723 return FALSE; 724 } else 725 return FALSE; 726 } 727 728 /* check LVDS table */ 729 /* IGP can be mobile or desktop so check the connectors */ 730 if (info->IsMobility || info->IsIGP) { 731 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x40); 732 if (offset) { 733 info->BiosConnector[4].valid = TRUE; 734 info->BiosConnector[4].ConnectorType = CONNECTOR_LVDS; 735 info->BiosConnector[4].ddc_i2c.valid = FALSE; 736 737 info->BiosConnector[4].devices = ATOM_DEVICE_LCD1_SUPPORT; 738 if (!radeon_add_encoder(pScrn, 739 radeon_get_encoder_id_from_supported_device(pScrn, 740 ATOM_DEVICE_LCD1_SUPPORT, 741 0), 742 ATOM_DEVICE_LCD1_SUPPORT)) 743 return FALSE; 744 745 tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x42); 746 if (tmp) { 747 tmp0 = RADEON_BIOS16(tmp + 0x15); 748 if (tmp0) { 749 tmp1 = RADEON_BIOS8(tmp0+2) & 0x07; 750 if (tmp1) { 751 DDCType = tmp1; 752 switch (DDCType) { 753 case DDC_NONE_DETECTED: 754 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "No DDC for LCD\n"); 755 break; 756 case DDC_MONID: 757 info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); 758 break; 759 case DDC_DVI: 760 info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); 761 break; 762 case DDC_VGA: 763 info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); 764 break; 765 case DDC_CRT2: 766 info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); 767 break; 768 case DDC_LCD: 769 info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_LCD_GPIO_MASK); 770 info->BiosConnector[4].ddc_i2c.mask_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 771 info->BiosConnector[4].ddc_i2c.mask_data_mask = RADEON_BIOS32(tmp0 + 0x07); 772 info->BiosConnector[4].ddc_i2c.a_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 773 info->BiosConnector[4].ddc_i2c.a_data_mask = RADEON_BIOS32(tmp0 + 0x07); 774 info->BiosConnector[4].ddc_i2c.put_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 775 info->BiosConnector[4].ddc_i2c.put_data_mask = RADEON_BIOS32(tmp0 + 0x07); 776 info->BiosConnector[4].ddc_i2c.get_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 777 info->BiosConnector[4].ddc_i2c.get_data_mask = RADEON_BIOS32(tmp0 + 0x07); 778 break; 779 case DDC_GPIO: 780 info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_MDGPIO_EN_REG); 781 info->BiosConnector[4].ddc_i2c.mask_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 782 info->BiosConnector[4].ddc_i2c.mask_data_mask = RADEON_BIOS32(tmp0 + 0x07); 783 info->BiosConnector[4].ddc_i2c.a_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 784 info->BiosConnector[4].ddc_i2c.a_data_mask = RADEON_BIOS32(tmp0 + 0x07); 785 info->BiosConnector[4].ddc_i2c.put_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 786 info->BiosConnector[4].ddc_i2c.put_data_mask = RADEON_BIOS32(tmp0 + 0x07); 787 info->BiosConnector[4].ddc_i2c.get_clk_mask = RADEON_BIOS32(tmp0 + 0x03); 788 info->BiosConnector[4].ddc_i2c.get_data_mask = RADEON_BIOS32(tmp0 + 0x07); 789 break; 790 default: 791 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown DDC Type: %d\n", DDCType); 792 break; 793 } 794 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "LCD DDC Info Table found!\n"); 795 } 796 } 797 } else 798 info->BiosConnector[4].ddc_i2c.valid = FALSE; 799 } 800 } 801 802 /* check TV table */ 803 if (info->InternalTVOut) { 804 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x32); 805 if (offset) { 806 if (RADEON_BIOS8(offset + 6) == 'T') { 807 info->BiosConnector[5].valid = TRUE; 808 /* assume s-video for now */ 809 info->BiosConnector[5].ConnectorType = CONNECTOR_STV; 810 info->BiosConnector[5].load_detection = FALSE; 811 info->BiosConnector[5].ddc_i2c.valid = FALSE; 812 info->BiosConnector[5].devices = ATOM_DEVICE_TV1_SUPPORT; 813 if (!radeon_add_encoder(pScrn, 814 radeon_get_encoder_id_from_supported_device(pScrn, 815 ATOM_DEVICE_TV1_SUPPORT, 816 2), 817 ATOM_DEVICE_TV1_SUPPORT)) 818 return FALSE; 819 } 820 } 821 } 822 823 return TRUE; 824} 825 826Bool RADEONGetConnectorInfoFromBIOS (ScrnInfoPtr pScrn) 827{ 828 RADEONInfoPtr info = RADEONPTR (pScrn); 829 830 if(!info->VBIOS) return FALSE; 831 832 if (info->IsAtomBios) 833 return RADEONGetATOMConnectorInfoFromBIOS(pScrn); 834 else 835 return RADEONGetLegacyConnectorInfoFromBIOS(pScrn); 836} 837 838Bool RADEONGetTVInfoFromBIOS (xf86OutputPtr output) { 839 ScrnInfoPtr pScrn = output->scrn; 840 RADEONInfoPtr info = RADEONPTR(pScrn); 841 RADEONOutputPrivatePtr radeon_output = output->driver_private; 842 radeon_tvout_ptr tvout = &radeon_output->tvout; 843 int offset, refclk, stds; 844 845 if (!info->VBIOS) return FALSE; 846 847 if (info->IsAtomBios) 848 return RADEONGetATOMTVInfo(output); 849 else { 850 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x32); 851 if (offset) { 852 if (RADEON_BIOS8(offset + 6) == 'T') { 853 switch (RADEON_BIOS8(offset + 7) & 0xf) { 854 case 1: 855 tvout->default_tvStd = TV_STD_NTSC; 856 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: NTSC\n"); 857 break; 858 case 2: 859 tvout->default_tvStd = TV_STD_PAL; 860 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: PAL\n"); 861 break; 862 case 3: 863 tvout->default_tvStd = TV_STD_PAL_M; 864 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: PAL-M\n"); 865 break; 866 case 4: 867 tvout->default_tvStd = TV_STD_PAL_60; 868 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: PAL-60\n"); 869 break; 870 case 5: 871 tvout->default_tvStd = TV_STD_NTSC_J; 872 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: NTSC-J\n"); 873 break; 874 case 6: 875 tvout->default_tvStd = TV_STD_SCART_PAL; 876 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: SCART-PAL\n"); 877 break; 878 default: 879 tvout->default_tvStd = TV_STD_NTSC; 880 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Unknown TV standard; defaulting to NTSC\n"); 881 break; 882 } 883 tvout->tvStd = tvout->default_tvStd; 884 885 refclk = (RADEON_BIOS8(offset + 9) >> 2) & 0x3; 886 if (refclk == 0) 887 tvout->TVRefClk = 29.498928713; /* MHz */ 888 else if (refclk == 1) 889 tvout->TVRefClk = 28.636360000; 890 else if (refclk == 2) 891 tvout->TVRefClk = 14.318180000; 892 else if (refclk == 3) 893 tvout->TVRefClk = 27.000000000; 894 895 tvout->SupportedTVStds = tvout->default_tvStd; 896 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TV standards supported by chip: "); 897 stds = RADEON_BIOS8(offset + 10) & 0x1f; 898 if (stds & TV_STD_NTSC) { 899 tvout->SupportedTVStds |= TV_STD_NTSC; 900 ErrorF("NTSC "); 901 } 902 if (stds & TV_STD_PAL) { 903 tvout->SupportedTVStds |= TV_STD_PAL; 904 ErrorF("PAL "); 905 } 906 if (stds & TV_STD_PAL_M) { 907 tvout->SupportedTVStds |= TV_STD_PAL_M; 908 ErrorF("PAL-M "); 909 } 910 if (stds & TV_STD_PAL_60) { 911 tvout->SupportedTVStds |= TV_STD_PAL_60; 912 ErrorF("PAL-60 "); 913 } 914 if (stds & TV_STD_NTSC_J) { 915 tvout->SupportedTVStds |= TV_STD_NTSC_J; 916 ErrorF("NTSC-J "); 917 } 918 if (stds & TV_STD_SCART_PAL) { 919 tvout->SupportedTVStds |= TV_STD_SCART_PAL; 920 ErrorF("SCART-PAL"); 921 } 922 ErrorF("\n"); 923 924 return TRUE; 925 } 926 } 927 } 928 return FALSE; 929} 930 931/* Read PLL parameters from BIOS block. Default to typical values if there 932 is no BIOS. */ 933Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn) 934{ 935 RADEONInfoPtr info = RADEONPTR (pScrn); 936 RADEONPLLPtr pll = &info->pll; 937 uint16_t pll_info_block; 938 939 if (!info->VBIOS) { 940 return FALSE; 941 } else { 942 if (info->IsAtomBios) { 943 pll_info_block = RADEON_BIOS16 (info->MasterDataStart + 12); 944 945 pll->reference_freq = RADEON_BIOS16 (pll_info_block + 82); 946 pll->reference_div = 0; /* Need to derive from existing setting 947 or use a new algorithm to calculate 948 from min_input and max_input 949 */ 950 pll->pll_out_min = RADEON_BIOS16 (pll_info_block + 78); 951 pll->pll_out_max = RADEON_BIOS32 (pll_info_block + 32); 952 953 if (pll->pll_out_min == 0) { 954 if (IS_AVIVO_VARIANT) 955 pll->pll_out_min = 64800; 956 else 957 pll->pll_out_min = 20000; 958 } 959 960 pll->pll_in_min = RADEON_BIOS16 (pll_info_block + 74); 961 pll->pll_in_max = RADEON_BIOS16 (pll_info_block + 76); 962 963 pll->xclk = RADEON_BIOS16 (pll_info_block + 72); 964 965 info->sclk = RADEON_BIOS32(pll_info_block + 8) / 100.0; 966 info->mclk = RADEON_BIOS32(pll_info_block + 12) / 100.0; 967 } else { 968 int rev; 969 970 pll_info_block = RADEON_BIOS16 (info->ROMHeaderStart + 0x30); 971 972 rev = RADEON_BIOS8(pll_info_block); 973 974 pll->reference_freq = RADEON_BIOS16 (pll_info_block + 0x0e); 975 pll->reference_div = RADEON_BIOS16 (pll_info_block + 0x10); 976 pll->pll_out_min = RADEON_BIOS32 (pll_info_block + 0x12); 977 pll->pll_out_max = RADEON_BIOS32 (pll_info_block + 0x16); 978 979 if (rev > 9) { 980 pll->pll_in_min = RADEON_BIOS32(pll_info_block + 0x36); 981 pll->pll_in_max = RADEON_BIOS32(pll_info_block + 0x3a); 982 } else { 983 pll->pll_in_min = 40; 984 pll->pll_in_max = 500; 985 } 986 987 pll->xclk = RADEON_BIOS16(pll_info_block + 0x08); 988 989 info->sclk = RADEON_BIOS16(pll_info_block + 10) / 100.0; 990 info->mclk = RADEON_BIOS16(pll_info_block + 8) / 100.0; 991 } 992 993 if (info->sclk == 0) info->sclk = 200; 994 if (info->mclk == 0) info->mclk = 200; 995 } 996 997 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "ref_freq: %d, min_out_pll: %u, " 998 "max_out_pll: %u, min_in_pll: %u, max_in_pll: %u, xclk: %d, " 999 "sclk: %f, mclk: %f\n", 1000 pll->reference_freq, (unsigned)pll->pll_out_min, 1001 (unsigned)pll->pll_out_max, (unsigned)pll->pll_in_min, 1002 (unsigned)pll->pll_in_max, pll->xclk, info->sclk, info->mclk); 1003 1004 return TRUE; 1005} 1006 1007Bool RADEONGetDAC2InfoFromBIOS (ScrnInfoPtr pScrn, radeon_tvdac_ptr tvdac) 1008{ 1009 RADEONInfoPtr info = RADEONPTR(pScrn); 1010 int offset, rev, bg, dac; 1011 1012 if (!info->VBIOS) return FALSE; 1013 1014 if (xf86ReturnOptValBool(info->Options, OPTION_DEFAULT_TVDAC_ADJ, FALSE)) 1015 return FALSE; 1016 1017 if (info->IsAtomBios) { 1018 /* not implemented yet */ 1019 return FALSE; 1020 } else { 1021 /* first check TV table */ 1022 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x32); 1023 if (offset) { 1024 rev = RADEON_BIOS8(offset + 0x3); 1025 if (rev > 4) { 1026 bg = RADEON_BIOS8(offset + 0xc) & 0xf; 1027 dac = RADEON_BIOS8(offset + 0xd) & 0xf; 1028 tvdac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1029 1030 bg = RADEON_BIOS8(offset + 0xe) & 0xf; 1031 dac = RADEON_BIOS8(offset + 0xf) & 0xf; 1032 tvdac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1033 1034 bg = RADEON_BIOS8(offset + 0x10) & 0xf; 1035 dac = RADEON_BIOS8(offset + 0x11) & 0xf; 1036 tvdac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1037 1038 return TRUE; 1039 } else if (rev > 1) { 1040 bg = RADEON_BIOS8(offset + 0xc) & 0xf; 1041 dac = (RADEON_BIOS8(offset + 0xc) >> 4) & 0xf; 1042 tvdac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1043 1044 bg = RADEON_BIOS8(offset + 0xd) & 0xf; 1045 dac = (RADEON_BIOS8(offset + 0xd) >> 4) & 0xf; 1046 tvdac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1047 1048 bg = RADEON_BIOS8(offset + 0xe) & 0xf; 1049 dac = (RADEON_BIOS8(offset + 0xe) >> 4) & 0xf; 1050 tvdac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1051 1052 return TRUE; 1053 } 1054 } 1055 /* then check CRT table */ 1056 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x60); 1057 if (offset) { 1058 rev = RADEON_BIOS8(offset) & 0x3; 1059 if (rev < 2) { 1060 bg = RADEON_BIOS8(offset + 0x3) & 0xf; 1061 dac = (RADEON_BIOS8(offset + 0x3) >> 4) & 0xf; 1062 tvdac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1063 tvdac->pal_tvdac_adj = tvdac->ps2_tvdac_adj; 1064 tvdac->ntsc_tvdac_adj = tvdac->ps2_tvdac_adj; 1065 1066 return TRUE; 1067 } else { 1068 bg = RADEON_BIOS8(offset + 0x4) & 0xf; 1069 dac = RADEON_BIOS8(offset + 0x5) & 0xf; 1070 tvdac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1071 tvdac->pal_tvdac_adj = tvdac->ps2_tvdac_adj; 1072 tvdac->ntsc_tvdac_adj = tvdac->ps2_tvdac_adj; 1073 1074 return TRUE; 1075 } 1076 } 1077 } 1078 1079 return FALSE; 1080} 1081 1082Bool 1083RADEONGetLVDSInfoFromBIOS(ScrnInfoPtr pScrn, radeon_lvds_ptr lvds) 1084{ 1085 RADEONInfoPtr info = RADEONPTR(pScrn); 1086 radeon_native_mode_ptr native_mode = &lvds->native_mode; 1087 unsigned long tmp, i; 1088 1089 if (!info->VBIOS) 1090 return FALSE; 1091 1092 if (!info->IsAtomBios) { 1093 tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x40); 1094 1095 if (!tmp) { 1096 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1097 "No Panel Info Table found in BIOS!\n"); 1098 return FALSE; 1099 } else { 1100 char stmp[30]; 1101 int tmp0; 1102 1103 for (i = 0; i < 24; i++) 1104 stmp[i] = RADEON_BIOS8(tmp+i+1); 1105 stmp[24] = 0; 1106 1107 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1108 "Panel ID string: %s\n", stmp); 1109 1110 native_mode->PanelXRes = RADEON_BIOS16(tmp+25); 1111 native_mode->PanelYRes = RADEON_BIOS16(tmp+27); 1112 xf86DrvMsg(0, X_INFO, "Panel Size from BIOS: %dx%d\n", 1113 native_mode->PanelXRes, native_mode->PanelYRes); 1114 1115 lvds->PanelPwrDly = RADEON_BIOS16(tmp+44); 1116 if (lvds->PanelPwrDly > 2000 || lvds->PanelPwrDly < 0) 1117 lvds->PanelPwrDly = 2000; 1118 1119 /* some panels only work well with certain divider combinations. 1120 */ 1121 info->RefDivider = RADEON_BIOS16(tmp+46); 1122 info->PostDivider = RADEON_BIOS8(tmp+48); 1123 info->FeedbackDivider = RADEON_BIOS16(tmp+49); 1124 if ((info->RefDivider != 0) && 1125 (info->FeedbackDivider > 3)) { 1126 info->UseBiosDividers = TRUE; 1127 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1128 "BIOS provided dividers will be used.\n"); 1129 } 1130 1131 /* We don't use a while loop here just in case we have a corrupted BIOS image. 1132 The max number of table entries is 23 at present, but may grow in future. 1133 To ensure it works with future revisions we loop it to 32. 1134 */ 1135 for (i = 0; i < 32; i++) { 1136 tmp0 = RADEON_BIOS16(tmp+64+i*2); 1137 if (tmp0 == 0) break; 1138 if ((RADEON_BIOS16(tmp0) == native_mode->PanelXRes) && 1139 (RADEON_BIOS16(tmp0+2) == native_mode->PanelYRes)) { 1140 native_mode->HBlank = (RADEON_BIOS16(tmp0+17) - 1141 RADEON_BIOS16(tmp0+19)) * 8; 1142 native_mode->HOverPlus = (RADEON_BIOS16(tmp0+21) - 1143 RADEON_BIOS16(tmp0+19) - 1) * 8; 1144 native_mode->HSyncWidth = RADEON_BIOS8(tmp0+23) * 8; 1145 native_mode->VBlank = (RADEON_BIOS16(tmp0+24) - 1146 RADEON_BIOS16(tmp0+26)); 1147 native_mode->VOverPlus = ((RADEON_BIOS16(tmp0+28) & 0x7ff) - 1148 RADEON_BIOS16(tmp0+26)); 1149 native_mode->VSyncWidth = ((RADEON_BIOS16(tmp0+28) & 0xf800) >> 11); 1150 native_mode->DotClock = RADEON_BIOS16(tmp0+9) * 10; 1151 native_mode->Flags = 0; 1152 } 1153 } 1154 } 1155 1156 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1157 "LVDS Info:\n" 1158 "XRes: %d, YRes: %d, DotClock: %d\n" 1159 "HBlank: %d, HOverPlus: %d, HSyncWidth: %d\n" 1160 "VBlank: %d, VOverPlus: %d, VSyncWidth: %d\n", 1161 native_mode->PanelXRes, native_mode->PanelYRes, native_mode->DotClock, 1162 native_mode->HBlank, native_mode->HOverPlus, native_mode->HSyncWidth, 1163 native_mode->VBlank, native_mode->VOverPlus, native_mode->VSyncWidth); 1164 1165 return TRUE; 1166 } 1167 return FALSE; 1168} 1169 1170xf86MonPtr RADEONGetHardCodedEDIDFromBIOS (xf86OutputPtr output) 1171{ 1172 ScrnInfoPtr pScrn = output->scrn; 1173 RADEONInfoPtr info = RADEONPTR(pScrn); 1174 unsigned long tmp; 1175 unsigned char edid[256]; 1176 xf86MonPtr mon = NULL; 1177 1178 if (!info->VBIOS) 1179 return mon; 1180 1181 if (!info->IsAtomBios) { 1182 tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x4c); 1183 if (tmp) { 1184 memcpy(edid, (unsigned char*)(info->VBIOS + tmp), 256); 1185 if (edid[1] == 0xff) 1186 mon = xf86InterpretEDID(output->scrn->scrnIndex, edid); 1187 } 1188 } 1189 1190 return mon; 1191} 1192 1193Bool RADEONGetTMDSInfoFromBIOS (ScrnInfoPtr pScrn, radeon_tmds_ptr tmds) 1194{ 1195 RADEONInfoPtr info = RADEONPTR(pScrn); 1196 uint32_t tmp, maxfreq; 1197 int i, n; 1198 1199 if (!info->VBIOS) return FALSE; 1200 1201 if (info->IsAtomBios) { 1202 if((tmp = RADEON_BIOS16 (info->MasterDataStart + 18))) { 1203 1204 maxfreq = RADEON_BIOS16(tmp+4); 1205 1206 for (i=0; i<4; i++) { 1207 tmds->tmds_pll[i].freq = RADEON_BIOS16(tmp+i*6+6); 1208 /* This assumes each field in TMDS_PLL has 6 bit as in R300/R420 */ 1209 tmds->tmds_pll[i].value = ((RADEON_BIOS8(tmp+i*6+8) & 0x3f) | 1210 ((RADEON_BIOS8(tmp+i*6+10) & 0x3f)<<6) | 1211 ((RADEON_BIOS8(tmp+i*6+9) & 0xf)<<12) | 1212 ((RADEON_BIOS8(tmp+i*6+11) & 0xf)<<16)); 1213 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1214 "TMDS PLL from BIOS: %u %x\n", 1215 (unsigned)tmds->tmds_pll[i].freq, 1216 (unsigned)tmds->tmds_pll[i].value); 1217 1218 if (maxfreq == tmds->tmds_pll[i].freq) { 1219 tmds->tmds_pll[i].freq = 0xffffffff; 1220 break; 1221 } 1222 } 1223 return TRUE; 1224 } 1225 } else { 1226 1227 tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x34); 1228 if (tmp) { 1229 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1230 "DFP table revision: %d\n", RADEON_BIOS8(tmp)); 1231 if (RADEON_BIOS8(tmp) == 3) { 1232 n = RADEON_BIOS8(tmp + 5) + 1; 1233 if (n > 4) n = 4; 1234 for (i=0; i<n; i++) { 1235 tmds->tmds_pll[i].value = RADEON_BIOS32(tmp+i*10+0x08); 1236 tmds->tmds_pll[i].freq = RADEON_BIOS16(tmp+i*10+0x10); 1237 } 1238 return TRUE; 1239 } else if (RADEON_BIOS8(tmp) == 4) { 1240 int stride = 0; 1241 n = RADEON_BIOS8(tmp + 5) + 1; 1242 if (n > 4) n = 4; 1243 for (i=0; i<n; i++) { 1244 tmds->tmds_pll[i].value = RADEON_BIOS32(tmp+stride+0x08); 1245 tmds->tmds_pll[i].freq = RADEON_BIOS16(tmp+stride+0x10); 1246 if (i == 0) stride += 10; 1247 else stride += 6; 1248 } 1249 return TRUE; 1250 } 1251 } 1252 } 1253 return FALSE; 1254} 1255 1256static RADEONI2CBusRec 1257RADEONLookupI2CBlock(ScrnInfoPtr pScrn, int id) 1258{ 1259 RADEONInfoPtr info = RADEONPTR (pScrn); 1260 int offset, blocks, i; 1261 RADEONI2CBusRec i2c; 1262 1263 memset(&i2c, 0, sizeof(RADEONI2CBusRec)); 1264 i2c.valid = FALSE; 1265 1266 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x70); 1267 if (offset) { 1268 blocks = RADEON_BIOS8(offset + 2); 1269 for (i = 0; i < blocks; i++) { 1270 int i2c_id = RADEON_BIOS8(offset + 3 + (i * 5) + 0); 1271 if (id == i2c_id) { 1272 int reg = RADEON_BIOS16(offset + 3 + (i * 5) + 1) * 4; 1273 int clock_shift = RADEON_BIOS8(offset + 3 + (i * 5) + 3); 1274 int data_shift = RADEON_BIOS8(offset + 3 + (i * 5) + 4); 1275 1276 i2c.mask_clk_mask = (1 << clock_shift); 1277 i2c.mask_data_mask = (1 << data_shift); 1278 i2c.a_clk_mask = (1 << clock_shift); 1279 i2c.a_data_mask = (1 << data_shift); 1280 i2c.put_clk_mask = (1 << clock_shift); 1281 i2c.put_data_mask = (1 << data_shift); 1282 i2c.get_clk_mask = (1 << clock_shift); 1283 i2c.get_data_mask = (1 << data_shift); 1284 i2c.mask_clk_reg = reg; 1285 i2c.mask_data_reg = reg; 1286 i2c.a_clk_reg = reg; 1287 i2c.a_data_reg = reg; 1288 i2c.put_clk_reg = reg; 1289 i2c.put_data_reg = reg; 1290 i2c.get_clk_reg = reg; 1291 i2c.get_data_reg = reg; 1292 i2c.valid = TRUE; 1293 break; 1294 } 1295 } 1296 } 1297 return i2c; 1298} 1299 1300Bool RADEONGetExtTMDSInfoFromBIOS (ScrnInfoPtr pScrn, radeon_dvo_ptr dvo) 1301{ 1302 RADEONInfoPtr info = RADEONPTR(pScrn); 1303 int offset, table_start, max_freq, gpio_reg, flags; 1304 1305 if (!info->VBIOS) 1306 return FALSE; 1307 1308 if (info->IsAtomBios) 1309 return FALSE; 1310 else if (info->IsIGP) { 1311 /* RS4xx TMDS stuff is in the mobile table */ 1312 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x42); 1313 if (offset) { 1314 int rev = RADEON_BIOS8(offset); 1315 if (rev >= 6) { 1316 offset = RADEON_BIOS16(offset + 0x17); 1317 if (offset) { 1318 offset = RADEON_BIOS16(offset + 2); 1319 rev = RADEON_BIOS8(offset); 1320 if (offset && (rev > 1)) { 1321 int blocks = RADEON_BIOS8(offset + 3); 1322 int index = offset + 4; 1323 dvo->dvo_i2c.valid = FALSE; 1324 while (blocks > 0) { 1325 int id = RADEON_BIOS16(index); 1326 index += 2; 1327 switch (id >> 13) { 1328 case 0: 1329 index += 6; 1330 break; 1331 case 2: 1332 index += 10; 1333 break; 1334 case 3: 1335 index += 2; 1336 break; 1337 case 4: 1338 index += 2; 1339 break; 1340 case 6: 1341 dvo->dvo_i2c_slave_addr = 1342 RADEON_BIOS16(index) & 0xff; 1343 index += 2; 1344 dvo->dvo_i2c = 1345 RADEONLookupI2CBlock(pScrn, RADEON_BIOS8(index)); 1346 return TRUE; 1347 default: 1348 break; 1349 } 1350 blocks--; 1351 } 1352 } 1353 } 1354 } 1355 } 1356 } else { 1357 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x58); 1358 if (offset) { 1359 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1360 "External TMDS Table revision: %d\n", 1361 RADEON_BIOS8(offset)); 1362 table_start = offset+4; 1363 max_freq = RADEON_BIOS16(table_start); 1364 dvo->dvo_i2c_slave_addr = RADEON_BIOS8(table_start+2); 1365 dvo->dvo_i2c.valid = FALSE; 1366 gpio_reg = RADEON_BIOS8(table_start+3); 1367 if (gpio_reg == 1) 1368 dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); 1369 else if (gpio_reg == 2) 1370 dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); 1371 else if (gpio_reg == 3) 1372 dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); 1373 else if (gpio_reg == 4) 1374 dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); 1375 else if (gpio_reg == 5) { 1376 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1377 "unsupported MM gpio_reg\n"); 1378 return FALSE; 1379 } else { 1380 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1381 "Unknown gpio reg: %d\n", gpio_reg); 1382 return FALSE; 1383 } 1384 flags = RADEON_BIOS8(table_start+5); 1385 dvo->dvo_duallink = flags & 0x01; 1386 if (dvo->dvo_duallink) { 1387 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1388 "Duallink TMDS detected\n"); 1389 } 1390 return TRUE; 1391 } 1392 } 1393 1394 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1395 "No External TMDS Table found\n"); 1396 1397 return FALSE; 1398} 1399 1400Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output) 1401{ 1402 ScrnInfoPtr pScrn = output->scrn; 1403 RADEONInfoPtr info = RADEONPTR(pScrn); 1404 unsigned char *RADEONMMIO = info->MMIO; 1405 radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); 1406 radeon_dvo_ptr dvo = NULL; 1407 int offset, index, id; 1408 uint32_t val, reg, and_mask, or_mask; 1409 1410 if (radeon_encoder == NULL) 1411 return FALSE; 1412 1413 dvo = (radeon_dvo_ptr)radeon_encoder->dev_priv; 1414 1415 if (dvo == NULL) 1416 return FALSE; 1417 1418 if (!info->VBIOS) 1419 return FALSE; 1420 1421 if (info->IsAtomBios) 1422 return FALSE; 1423 else if (info->IsIGP) { 1424 /* RS4xx TMDS stuff is in the mobile table */ 1425 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x42); 1426 if (offset) { 1427 int rev = RADEON_BIOS8(offset); 1428 if (rev >= 6) { 1429 offset = RADEON_BIOS16(offset + 0x17); 1430 if (offset) { 1431 offset = RADEON_BIOS16(offset + 2); 1432 rev = RADEON_BIOS8(offset); 1433 if (offset && (rev > 1)) { 1434 int blocks = RADEON_BIOS8(offset + 3); 1435 index = offset + 4; 1436 while (blocks > 0) { 1437 id = RADEON_BIOS16(index); 1438 index += 2; 1439 switch (id >> 13) { 1440 case 0: 1441 reg = (id & 0x1fff) * 4; 1442 val = RADEON_BIOS32(index); 1443 index += 4; 1444 ErrorF("MMIO: 0x%x 0x%x\n", 1445 (unsigned)reg, (unsigned)val); 1446 OUTREG(reg, val); 1447 break; 1448 case 2: 1449 reg = (id & 0x1fff) * 4; 1450 and_mask = RADEON_BIOS32(index); 1451 index += 4; 1452 or_mask = RADEON_BIOS32(index); 1453 index += 4; 1454 ErrorF("MMIO mask: 0x%x 0x%x 0x%x\n", 1455 (unsigned)reg, (unsigned)and_mask, (unsigned)or_mask); 1456 val = INREG(reg); 1457 val = (val & and_mask) | or_mask; 1458 OUTREG(reg, val); 1459 break; 1460 case 3: 1461 val = RADEON_BIOS16(index); 1462 index += 2; 1463 ErrorF("delay: %u\n", (unsigned)val); 1464 usleep(val); 1465 break; 1466 case 4: 1467 val = RADEON_BIOS16(index); 1468 index += 2; 1469 ErrorF("delay: %u\n", (unsigned)val * 1000); 1470 usleep(val * 1000); 1471 break; 1472 case 6: 1473 index++; 1474 reg = RADEON_BIOS8(index); 1475 index++; 1476 val = RADEON_BIOS8(index); 1477 index++; 1478 ErrorF("i2c write: 0x%x, 0x%x\n", (unsigned)reg, 1479 (unsigned)val); 1480 RADEONDVOWriteByte(dvo->DVOChip, reg, val); 1481 break; 1482 default: 1483 ErrorF("unknown id %d\n", id>>13); 1484 return FALSE; 1485 } 1486 blocks--; 1487 } 1488 return TRUE; 1489 } 1490 } 1491 } 1492 } 1493 } else { 1494 offset = RADEON_BIOS16(info->ROMHeaderStart + 0x58); 1495 if (offset) { 1496 index = offset+10; 1497 id = RADEON_BIOS16(index); 1498 while (id != 0xffff) { 1499 index += 2; 1500 switch(id >> 13) { 1501 case 0: 1502 reg = (id & 0x1fff) * 4; 1503 val = RADEON_BIOS32(index); 1504 index += 4; 1505 ErrorF("MMIO: 0x%x 0x%x\n", 1506 (unsigned)reg, (unsigned)val); 1507 OUTREG(reg, val); 1508 break; 1509 case 2: 1510 reg = (id & 0x1fff) * 4; 1511 and_mask = RADEON_BIOS32(index); 1512 index += 4; 1513 or_mask = RADEON_BIOS32(index); 1514 index += 4; 1515 val = INREG(reg); 1516 val = (val & and_mask) | or_mask; 1517 ErrorF("MMIO mask: 0x%x 0x%x 0x%x\n", 1518 (unsigned)reg, (unsigned)and_mask, (unsigned)or_mask); 1519 OUTREG(reg, val); 1520 break; 1521 case 4: 1522 val = RADEON_BIOS16(index); 1523 index += 2; 1524 ErrorF("delay: %u\n", (unsigned)val); 1525 usleep(val); 1526 break; 1527 case 5: 1528 reg = id & 0x1fff; 1529 and_mask = RADEON_BIOS32(index); 1530 index += 4; 1531 or_mask = RADEON_BIOS32(index); 1532 index += 4; 1533 ErrorF("PLL mask: 0x%x 0x%x 0x%x\n", 1534 (unsigned)reg, (unsigned)and_mask, (unsigned)or_mask); 1535 val = INPLL(pScrn, reg); 1536 val = (val & and_mask) | or_mask; 1537 OUTPLL(pScrn, reg, val); 1538 break; 1539 case 6: 1540 reg = id & 0x1fff; 1541 val = RADEON_BIOS8(index); 1542 index += 1; 1543 ErrorF("i2c write: 0x%x, 0x%x\n", (unsigned)reg, 1544 (unsigned)val); 1545 RADEONDVOWriteByte(dvo->DVOChip, reg, val); 1546 break; 1547 default: 1548 ErrorF("unknown id %d\n", id>>13); 1549 return FALSE; 1550 }; 1551 id = RADEON_BIOS16(index); 1552 } 1553 return TRUE; 1554 } 1555 } 1556 1557 return FALSE; 1558} 1559 1560/* support for init from bios tables 1561 * 1562 * Based heavily on the netbsd radeonfb driver 1563 * Written by Garrett D'Amore 1564 * Copyright (c) 2006 Itronix Inc. 1565 * 1566 */ 1567 1568/* bios table defines */ 1569 1570#define RADEON_TABLE_ENTRY_FLAG_MASK 0xe000 1571#define RADEON_TABLE_ENTRY_INDEX_MASK 0x1fff 1572#define RADEON_TABLE_ENTRY_COMMAND_MASK 0x00ff 1573 1574#define RADEON_TABLE_FLAG_WRITE_INDEXED 0x0000 1575#define RADEON_TABLE_FLAG_WRITE_DIRECT 0x2000 1576#define RADEON_TABLE_FLAG_MASK_INDEXED 0x4000 1577#define RADEON_TABLE_FLAG_MASK_DIRECT 0x6000 1578#define RADEON_TABLE_FLAG_DELAY 0x8000 1579#define RADEON_TABLE_FLAG_SCOMMAND 0xa000 1580 1581#define RADEON_TABLE_SCOMMAND_WAIT_MC_BUSY_MASK 0x03 1582#define RADEON_TABLE_SCOMMAND_WAIT_MEM_PWRUP_COMPLETE 0x08 1583 1584#define RADEON_PLL_FLAG_MASK 0xc0 1585#define RADEON_PLL_INDEX_MASK 0x3f 1586 1587#define RADEON_PLL_FLAG_WRITE 0x00 1588#define RADEON_PLL_FLAG_MASK_BYTE 0x40 1589#define RADEON_PLL_FLAG_WAIT 0x80 1590 1591#define RADEON_PLL_WAIT_150MKS 1 1592#define RADEON_PLL_WAIT_5MS 2 1593#define RADEON_PLL_WAIT_MC_BUSY_MASK 3 1594#define RADEON_PLL_WAIT_DLL_READY_MASK 4 1595#define RADEON_PLL_WAIT_CHK_SET_CLK_PWRMGT_CNTL24 5 1596 1597static uint16_t 1598RADEONValidateBIOSOffset(ScrnInfoPtr pScrn, uint16_t offset) 1599{ 1600 RADEONInfoPtr info = RADEONPTR (pScrn); 1601 uint8_t revision = RADEON_BIOS8(offset - 1); 1602 1603 if (revision > 0x10) { 1604 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1605 "Bad revision %d for BIOS table\n", revision); 1606 return 0; 1607 } 1608 1609 if (offset < 0x60) { 1610 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1611 "Bad offset 0x%x for BIOS Table\n", offset); 1612 return 0; 1613 } 1614 1615 return offset; 1616} 1617 1618Bool 1619RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn) 1620{ 1621 RADEONInfoPtr info = RADEONPTR (pScrn); 1622 uint8_t val; 1623 1624 if (!info->VBIOS) { 1625 return FALSE; 1626 } else { 1627 if (info->IsAtomBios) { 1628 return FALSE; 1629 } else { 1630 info->BiosTable.revision = RADEON_BIOS8(info->ROMHeaderStart + 4); 1631 info->BiosTable.rr1_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x0c); 1632 if (info->BiosTable.rr1_offset) { 1633 info->BiosTable.rr1_offset = 1634 RADEONValidateBIOSOffset(pScrn, info->BiosTable.rr1_offset); 1635 } 1636 if (info->BiosTable.revision > 0x09) 1637 return TRUE; 1638 info->BiosTable.rr2_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x4e); 1639 if (info->BiosTable.rr2_offset) { 1640 info->BiosTable.rr2_offset = 1641 RADEONValidateBIOSOffset(pScrn, info->BiosTable.rr2_offset); 1642 } 1643 info->BiosTable.dyn_clk_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x52); 1644 if (info->BiosTable.dyn_clk_offset) { 1645 info->BiosTable.dyn_clk_offset = 1646 RADEONValidateBIOSOffset(pScrn, info->BiosTable.dyn_clk_offset); 1647 } 1648 info->BiosTable.pll_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x46); 1649 if (info->BiosTable.pll_offset) { 1650 info->BiosTable.pll_offset = 1651 RADEONValidateBIOSOffset(pScrn, info->BiosTable.pll_offset); 1652 } 1653 info->BiosTable.mem_config_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x48); 1654 if (info->BiosTable.mem_config_offset) { 1655 info->BiosTable.mem_config_offset = 1656 RADEONValidateBIOSOffset(pScrn, info->BiosTable.mem_config_offset); 1657 } 1658 if (info->BiosTable.mem_config_offset) { 1659 info->BiosTable.mem_reset_offset = info->BiosTable.mem_config_offset; 1660 if (info->BiosTable.mem_reset_offset) { 1661 while (RADEON_BIOS8(info->BiosTable.mem_reset_offset)) 1662 info->BiosTable.mem_reset_offset++; 1663 info->BiosTable.mem_reset_offset++; 1664 info->BiosTable.mem_reset_offset += 2; 1665 } 1666 } 1667 if (info->BiosTable.mem_config_offset) { 1668 info->BiosTable.short_mem_offset = info->BiosTable.mem_config_offset; 1669 if ((info->BiosTable.short_mem_offset != 0) && 1670 (RADEON_BIOS8(info->BiosTable.short_mem_offset - 2) <= 64)) 1671 info->BiosTable.short_mem_offset += 1672 RADEON_BIOS8(info->BiosTable.short_mem_offset - 3); 1673 } 1674 if (info->BiosTable.rr2_offset) { 1675 info->BiosTable.rr3_offset = info->BiosTable.rr2_offset; 1676 if (info->BiosTable.rr3_offset) { 1677 while ((val = RADEON_BIOS8(info->BiosTable.rr3_offset + 1)) != 0) { 1678 if (val & 0x40) 1679 info->BiosTable.rr3_offset += 10; 1680 else if (val & 0x80) 1681 info->BiosTable.rr3_offset += 4; 1682 else 1683 info->BiosTable.rr3_offset += 6; 1684 } 1685 info->BiosTable.rr3_offset += 2; 1686 } 1687 } 1688 1689 if (info->BiosTable.rr3_offset) { 1690 info->BiosTable.rr4_offset = info->BiosTable.rr3_offset; 1691 if (info->BiosTable.rr4_offset) { 1692 while ((val = RADEON_BIOS8(info->BiosTable.rr4_offset + 1)) != 0) { 1693 if (val & 0x40) 1694 info->BiosTable.rr4_offset += 10; 1695 else if (val & 0x80) 1696 info->BiosTable.rr4_offset += 4; 1697 else 1698 info->BiosTable.rr4_offset += 6; 1699 } 1700 info->BiosTable.rr4_offset += 2; 1701 } 1702 } 1703 1704 if (info->BiosTable.rr3_offset + 1 == info->BiosTable.pll_offset) { 1705 info->BiosTable.rr3_offset = 0; 1706 info->BiosTable.rr4_offset = 0; 1707 } 1708 1709 return TRUE; 1710 1711 } 1712 } 1713} 1714 1715static void 1716RADEONRestoreBIOSRegBlock(ScrnInfoPtr pScrn, uint16_t table_offset) 1717{ 1718 RADEONInfoPtr info = RADEONPTR (pScrn); 1719 unsigned char *RADEONMMIO = info->MMIO; 1720 uint16_t offset = table_offset; 1721 uint16_t value, flag, index, count; 1722 uint32_t andmask, ormask, val, channel_complete_mask; 1723 uint8_t command; 1724 1725 if (offset == 0) 1726 return; 1727 1728 while ((value = RADEON_BIOS16(offset)) != 0) { 1729 flag = value & RADEON_TABLE_ENTRY_FLAG_MASK; 1730 index = value & RADEON_TABLE_ENTRY_INDEX_MASK; 1731 command = value & RADEON_TABLE_ENTRY_COMMAND_MASK; 1732 1733 offset += 2; 1734 1735 switch (flag) { 1736 case RADEON_TABLE_FLAG_WRITE_INDEXED: 1737 val = RADEON_BIOS32(offset); 1738 ErrorF("WRITE INDEXED: 0x%x 0x%x\n", 1739 index, (unsigned)val); 1740 OUTREG(RADEON_MM_INDEX, index); 1741 OUTREG(RADEON_MM_DATA, val); 1742 offset += 4; 1743 break; 1744 1745 case RADEON_TABLE_FLAG_WRITE_DIRECT: 1746 val = RADEON_BIOS32(offset); 1747 ErrorF("WRITE DIRECT: 0x%x 0x%x\n", index, (unsigned)val); 1748 OUTREG(index, val); 1749 offset += 4; 1750 break; 1751 1752 case RADEON_TABLE_FLAG_MASK_INDEXED: 1753 andmask = RADEON_BIOS32(offset); 1754 offset += 4; 1755 ormask = RADEON_BIOS32(offset); 1756 offset += 4; 1757 ErrorF("MASK INDEXED: 0x%x 0x%x 0x%x\n", 1758 index, (unsigned)andmask, (unsigned)ormask); 1759 OUTREG(RADEON_MM_INDEX, index); 1760 val = INREG(RADEON_MM_DATA); 1761 val = (val & andmask) | ormask; 1762 OUTREG(RADEON_MM_DATA, val); 1763 break; 1764 1765 case RADEON_TABLE_FLAG_MASK_DIRECT: 1766 andmask = RADEON_BIOS32(offset); 1767 offset += 4; 1768 ormask = RADEON_BIOS32(offset); 1769 offset += 4; 1770 ErrorF("MASK DIRECT: 0x%x 0x%x 0x%x\n", 1771 index, (unsigned)andmask, (unsigned)ormask); 1772 val = INREG(index); 1773 val = (val & andmask) | ormask; 1774 OUTREG(index, val); 1775 break; 1776 1777 case RADEON_TABLE_FLAG_DELAY: 1778 count = RADEON_BIOS16(offset); 1779 ErrorF("delay: %d\n", count); 1780 usleep(count); 1781 offset += 2; 1782 break; 1783 1784 case RADEON_TABLE_FLAG_SCOMMAND: 1785 ErrorF("SCOMMAND 0x%x\n", command); 1786 switch (command) { 1787 case RADEON_TABLE_SCOMMAND_WAIT_MC_BUSY_MASK: 1788 count = RADEON_BIOS16(offset); 1789 ErrorF("SCOMMAND_WAIT_MC_BUSY_MASK %d\n", count); 1790 while (count--) { 1791 if (!(INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL) & 1792 RADEON_MC_BUSY)) 1793 break; 1794 } 1795 break; 1796 1797 case RADEON_TABLE_SCOMMAND_WAIT_MEM_PWRUP_COMPLETE: 1798 count = RADEON_BIOS16(offset); 1799 ErrorF("SCOMMAND_WAIT_MEM_PWRUP_COMPLETE %d\n", count); 1800 /* may need to take into account how many memory channels 1801 * each card has 1802 */ 1803 if (IS_R300_VARIANT) 1804 channel_complete_mask = R300_MEM_PWRUP_COMPLETE; 1805 else 1806 channel_complete_mask = RADEON_MEM_PWRUP_COMPLETE; 1807 while (count--) { 1808 /* XXX: may need indexed access */ 1809 if ((INREG(RADEON_MEM_STR_CNTL) & 1810 channel_complete_mask) == 1811 channel_complete_mask) 1812 break; 1813 } 1814 break; 1815 1816 } 1817 offset += 2; 1818 break; 1819 } 1820 } 1821} 1822 1823static void 1824RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, uint16_t table_offset) 1825{ 1826 RADEONInfoPtr info = RADEONPTR (pScrn); 1827 unsigned char *RADEONMMIO = info->MMIO; 1828 uint16_t offset = table_offset; 1829 uint16_t count; 1830 uint32_t ormask, val, channel_complete_mask; 1831 uint8_t index; 1832 1833 if (offset == 0) 1834 return; 1835 1836 while ((index = RADEON_BIOS8(offset)) != 0xff) { 1837 offset++; 1838 if (index == 0x0f) { 1839 count = 20000; 1840 ErrorF("MEM_WAIT_MEM_PWRUP_COMPLETE %d\n", count); 1841 /* may need to take into account how many memory channels 1842 * each card has 1843 */ 1844 if (IS_R300_VARIANT) 1845 channel_complete_mask = R300_MEM_PWRUP_COMPLETE; 1846 else 1847 channel_complete_mask = RADEON_MEM_PWRUP_COMPLETE; 1848 while (count--) { 1849 /* XXX: may need indexed access */ 1850 if ((INREG(RADEON_MEM_STR_CNTL) & 1851 channel_complete_mask) == 1852 channel_complete_mask) 1853 break; 1854 } 1855 } else { 1856 ormask = RADEON_BIOS16(offset); 1857 offset += 2; 1858 1859 ErrorF("INDEX RADEON_MEM_SDRAM_MODE_REG %x %x\n", 1860 RADEON_SDRAM_MODE_MASK, (unsigned)ormask); 1861 1862 /* can this use direct access? */ 1863 OUTREG(RADEON_MM_INDEX, RADEON_MEM_SDRAM_MODE_REG); 1864 val = INREG(RADEON_MM_DATA); 1865 val = (val & RADEON_SDRAM_MODE_MASK) | ormask; 1866 OUTREG(RADEON_MM_DATA, val); 1867 1868 ormask = (uint32_t)index << 24; 1869 1870 ErrorF("INDEX RADEON_MEM_SDRAM_MODE_REG %x %x\n", 1871 RADEON_B3MEM_RESET_MASK, (unsigned)ormask); 1872 1873 /* can this use direct access? */ 1874 OUTREG(RADEON_MM_INDEX, RADEON_MEM_SDRAM_MODE_REG); 1875 val = INREG(RADEON_MM_DATA); 1876 val = (val & RADEON_B3MEM_RESET_MASK) | ormask; 1877 OUTREG(RADEON_MM_DATA, val); 1878 } 1879 } 1880} 1881 1882static void 1883RADEONRestoreBIOSPllBlock(ScrnInfoPtr pScrn, uint16_t table_offset) 1884{ 1885 RADEONInfoPtr info = RADEONPTR (pScrn); 1886 uint16_t offset = table_offset; 1887 uint8_t index, shift; 1888 uint32_t andmask, ormask, val, clk_pwrmgt_cntl; 1889 uint16_t count; 1890 1891 if (offset == 0) 1892 return; 1893 1894 while ((index = RADEON_BIOS8(offset)) != 0) { 1895 offset++; 1896 1897 switch (index & RADEON_PLL_FLAG_MASK) { 1898 case RADEON_PLL_FLAG_WAIT: 1899 switch (index & RADEON_PLL_INDEX_MASK) { 1900 case RADEON_PLL_WAIT_150MKS: 1901 ErrorF("delay: 150 us\n"); 1902 usleep(150); 1903 break; 1904 case RADEON_PLL_WAIT_5MS: 1905 ErrorF("delay: 5 ms\n"); 1906 usleep(5000); 1907 break; 1908 1909 case RADEON_PLL_WAIT_MC_BUSY_MASK: 1910 count = 1000; 1911 ErrorF("PLL_WAIT_MC_BUSY_MASK %d\n", count); 1912 while (count--) { 1913 if (!(INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL) & 1914 RADEON_MC_BUSY)) 1915 break; 1916 } 1917 break; 1918 1919 case RADEON_PLL_WAIT_DLL_READY_MASK: 1920 count = 1000; 1921 ErrorF("PLL_WAIT_DLL_READY_MASK %d\n", count); 1922 while (count--) { 1923 if (INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL) & 1924 RADEON_DLL_READY) 1925 break; 1926 } 1927 break; 1928 1929 case RADEON_PLL_WAIT_CHK_SET_CLK_PWRMGT_CNTL24: 1930 ErrorF("PLL_WAIT_CHK_SET_CLK_PWRMGT_CNTL24\n"); 1931 clk_pwrmgt_cntl = INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL); 1932 if (clk_pwrmgt_cntl & RADEON_CG_NO1_DEBUG_0) { 1933 val = INPLL(pScrn, RADEON_MCLK_CNTL); 1934 /* is this right? */ 1935 val = (val & 0xFFFF0000) | 0x1111; /* seems like we should clear these... */ 1936 OUTPLL(pScrn, RADEON_MCLK_CNTL, val); 1937 usleep(10000); 1938 OUTPLL(pScrn, RADEON_CLK_PWRMGT_CNTL, 1939 clk_pwrmgt_cntl & ~RADEON_CG_NO1_DEBUG_0); 1940 usleep(10000); 1941 } 1942 break; 1943 } 1944 break; 1945 1946 case RADEON_PLL_FLAG_MASK_BYTE: 1947 shift = RADEON_BIOS8(offset) * 8; 1948 offset++; 1949 1950 andmask = 1951 (((uint32_t)RADEON_BIOS8(offset)) << shift) | 1952 ~((uint32_t)0xff << shift); 1953 offset++; 1954 1955 ormask = ((uint32_t)RADEON_BIOS8(offset)) << shift; 1956 offset++; 1957 1958 ErrorF("PLL_MASK_BYTE 0x%x 0x%x 0x%x 0x%x\n", 1959 index, shift, (unsigned)andmask, (unsigned)ormask); 1960 val = INPLL(pScrn, index); 1961 val = (val & andmask) | ormask; 1962 OUTPLL(pScrn, index, val); 1963 break; 1964 1965 case RADEON_PLL_FLAG_WRITE: 1966 val = RADEON_BIOS32(offset); 1967 ErrorF("PLL_WRITE 0x%x 0x%x\n", index, (unsigned)val); 1968 OUTPLL(pScrn, index, val); 1969 offset += 4; 1970 break; 1971 } 1972 } 1973} 1974 1975Bool 1976RADEONPostCardFromBIOSTables(ScrnInfoPtr pScrn) 1977{ 1978 RADEONInfoPtr info = RADEONPTR (pScrn); 1979 1980 if (!info->VBIOS) { 1981 return FALSE; 1982 } else { 1983 if (info->IsAtomBios) { 1984 return FALSE; 1985 } else { 1986 if (info->BiosTable.rr1_offset) { 1987 ErrorF("rr1 restore, 0x%x\n", info->BiosTable.rr1_offset); 1988 RADEONRestoreBIOSRegBlock(pScrn, info->BiosTable.rr1_offset); 1989 } 1990 if (info->BiosTable.revision < 0x09) { 1991 if (info->BiosTable.pll_offset) { 1992 ErrorF("pll restore, 0x%x\n", info->BiosTable.pll_offset); 1993 RADEONRestoreBIOSPllBlock(pScrn, info->BiosTable.pll_offset); 1994 } 1995 if (info->BiosTable.rr2_offset) { 1996 ErrorF("rr2 restore, 0x%x\n", info->BiosTable.rr2_offset); 1997 RADEONRestoreBIOSRegBlock(pScrn, info->BiosTable.rr2_offset); 1998 } 1999 if (info->BiosTable.rr4_offset) { 2000 ErrorF("rr4 restore, 0x%x\n", info->BiosTable.rr4_offset); 2001 RADEONRestoreBIOSRegBlock(pScrn, info->BiosTable.rr4_offset); 2002 } 2003 if (info->BiosTable.mem_reset_offset) { 2004 ErrorF("mem reset restore, 0x%x\n", info->BiosTable.mem_reset_offset); 2005 RADEONRestoreBIOSMemBlock(pScrn, info->BiosTable.mem_reset_offset); 2006 } 2007 if (info->BiosTable.rr3_offset) { 2008 ErrorF("rr3 restore, 0x%x\n", info->BiosTable.rr3_offset); 2009 RADEONRestoreBIOSRegBlock(pScrn, info->BiosTable.rr3_offset); 2010 } 2011 if (info->BiosTable.dyn_clk_offset) { 2012 ErrorF("dyn_clk restore, 0x%x\n", info->BiosTable.dyn_clk_offset); 2013 RADEONRestoreBIOSPllBlock(pScrn, info->BiosTable.dyn_clk_offset); 2014 } 2015 } 2016 } 2017 } 2018 return TRUE; 2019} 2020