radeon_commonfuncs.c revision 2f39173d
1/* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining 8 * a copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation on the rights to use, copy, modify, merge, 11 * publish, distribute, sublicense, and/or sell copies of the Software, 12 * and to permit persons to whom the Software is furnished to do so, 13 * subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 */ 28 29#ifdef HAVE_CONFIG_H 30#include "config.h" 31#endif 32 33#include "ati_pciids_gen.h" 34 35#if defined(ACCEL_MMIO) && defined(ACCEL_CP) 36#error Cannot define both MMIO and CP acceleration! 37#endif 38 39#if !defined(UNIXCPP) || defined(ANSICPP) 40#define FUNC_NAME_CAT(prefix,suffix) prefix##suffix 41#else 42#define FUNC_NAME_CAT(prefix,suffix) prefix/**/suffix 43#endif 44 45#ifdef ACCEL_MMIO 46#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,MMIO) 47#else 48#ifdef ACCEL_CP 49#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,CP) 50#else 51#error No accel type defined! 52#endif 53#endif 54 55static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) 56{ 57 RADEONInfoPtr info = RADEONPTR(pScrn); 58 uint32_t gb_tile_config, su_reg_dest, vap_cntl; 59 int size; 60 ACCEL_PREAMBLE(); 61 62 info->accel_state->texW[0] = info->accel_state->texH[0] = 63 info->accel_state->texW[1] = info->accel_state->texH[1] = 1; 64 65 if (IS_R300_3D || IS_R500_3D) { 66 67 if (!info->cs) { 68 BEGIN_ACCEL(3); 69 OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); 70 OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); 71 OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); 72 FINISH_ACCEL(); 73 } 74 75 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 76 77 switch(info->accel_state->num_gb_pipes) { 78 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; 79 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; 80 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; 81 default: 82 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; 83 } 84 85 if (!info->cs) { 86 size = (info->ChipFamily >= CHIP_FAMILY_R420) ? 5 : 4; 87 BEGIN_ACCEL(size); 88 OUT_ACCEL_REG(R300_GB_TILE_CONFIG, gb_tile_config); 89 OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); 90 if (info->ChipFamily >= CHIP_FAMILY_R420) 91 OUT_ACCEL_REG(R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG); 92 OUT_ACCEL_REG(R300_GB_SELECT, 0); 93 OUT_ACCEL_REG(R300_GB_ENABLE, 0); 94 FINISH_ACCEL(); 95 } 96 97 if (IS_R500_3D) { 98 if (!info->cs) { 99 su_reg_dest = ((1 << info->accel_state->num_gb_pipes) - 1); 100 BEGIN_ACCEL(2); 101 OUT_ACCEL_REG(R500_SU_REG_DEST, su_reg_dest); 102 OUT_ACCEL_REG(R500_VAP_INDEX_OFFSET, 0); 103 FINISH_ACCEL(); 104 } 105 } 106 107 BEGIN_ACCEL(3); 108 OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); 109 OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); 110 OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); 111 FINISH_ACCEL(); 112 113 BEGIN_ACCEL(3); 114 OUT_ACCEL_REG(R300_GB_AA_CONFIG, 0); 115 OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); 116 OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); 117 FINISH_ACCEL(); 118 119 if (!info->cs) { 120 BEGIN_ACCEL(3); 121 OUT_ACCEL_REG(R300_GB_MSPOS0, ((6 << R300_MS_X0_SHIFT) | 122 (6 << R300_MS_Y0_SHIFT) | 123 (6 << R300_MS_X1_SHIFT) | 124 (6 << R300_MS_Y1_SHIFT) | 125 (6 << R300_MS_X2_SHIFT) | 126 (6 << R300_MS_Y2_SHIFT) | 127 (6 << R300_MSBD0_Y_SHIFT) | 128 (6 << R300_MSBD0_X_SHIFT))); 129 OUT_ACCEL_REG(R300_GB_MSPOS1, ((6 << R300_MS_X3_SHIFT) | 130 (6 << R300_MS_Y3_SHIFT) | 131 (6 << R300_MS_X4_SHIFT) | 132 (6 << R300_MS_Y4_SHIFT) | 133 (6 << R300_MS_X5_SHIFT) | 134 (6 << R300_MS_Y5_SHIFT) | 135 (6 << R300_MSBD1_SHIFT))); 136 OUT_ACCEL_REG(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); 137 FINISH_ACCEL(); 138 } 139 140 BEGIN_ACCEL(4); 141 OUT_ACCEL_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); 142 OUT_ACCEL_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST | 143 R300_COLOR_ROUND_NEAREST)); 144 OUT_ACCEL_REG(R300_GA_COLOR_CONTROL, (R300_RGB0_SHADING_GOURAUD | 145 R300_ALPHA0_SHADING_GOURAUD | 146 R300_RGB1_SHADING_GOURAUD | 147 R300_ALPHA1_SHADING_GOURAUD | 148 R300_RGB2_SHADING_GOURAUD | 149 R300_ALPHA2_SHADING_GOURAUD | 150 R300_RGB3_SHADING_GOURAUD | 151 R300_ALPHA3_SHADING_GOURAUD)); 152 OUT_ACCEL_REG(R300_GA_OFFSET, 0); 153 FINISH_ACCEL(); 154 155 BEGIN_ACCEL(5); 156 OUT_ACCEL_REG(R300_SU_TEX_WRAP, 0); 157 OUT_ACCEL_REG(R300_SU_POLY_OFFSET_ENABLE, 0); 158 OUT_ACCEL_REG(R300_SU_CULL_MODE, R300_FACE_NEG); 159 OUT_ACCEL_REG(R300_SU_DEPTH_SCALE, 0x4b7fffff); 160 OUT_ACCEL_REG(R300_SU_DEPTH_OFFSET, 0); 161 FINISH_ACCEL(); 162 163 /* setup the VAP */ 164 if (info->accel_state->has_tcl) 165 vap_cntl = ((5 << R300_PVS_NUM_SLOTS_SHIFT) | 166 (5 << R300_PVS_NUM_CNTLRS_SHIFT) | 167 (9 << R300_VF_MAX_VTX_NUM_SHIFT)); 168 else 169 vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) | 170 (5 << R300_PVS_NUM_CNTLRS_SHIFT) | 171 (5 << R300_VF_MAX_VTX_NUM_SHIFT)); 172 173 if ((info->ChipFamily == CHIP_FAMILY_R300) || 174 (info->ChipFamily == CHIP_FAMILY_R350)) 175 vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT); 176 else if (info->ChipFamily == CHIP_FAMILY_RV530) 177 vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT); 178 else if ((info->ChipFamily == CHIP_FAMILY_RV410) || 179 (info->ChipFamily == CHIP_FAMILY_R420)) 180 vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT); 181 else if ((info->ChipFamily == CHIP_FAMILY_R520) || 182 (info->ChipFamily == CHIP_FAMILY_R580) || 183 (info->ChipFamily == CHIP_FAMILY_RV560) || 184 (info->ChipFamily == CHIP_FAMILY_RV570)) 185 vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT); 186 else 187 vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT); 188 189 if (info->accel_state->has_tcl) 190 BEGIN_ACCEL(15); 191 else 192 BEGIN_ACCEL(9); 193 OUT_ACCEL_REG(R300_VAP_VTX_STATE_CNTL, 0); 194 OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); 195 196 if (info->accel_state->has_tcl) 197 OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0); 198 else 199 OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS); 200 OUT_ACCEL_REG(R300_VAP_CNTL, vap_cntl); 201 OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); 202 OUT_ACCEL_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT); 203 OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0); 204 205 OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 206 ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) | 207 (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) | 208 (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) | 209 (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) | 210 ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) 211 << R300_WRITE_ENA_0_SHIFT) | 212 (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) | 213 (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) | 214 (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) | 215 (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) | 216 ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) 217 << R300_WRITE_ENA_1_SHIFT))); 218 OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, 219 ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) | 220 (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) | 221 (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_2_SHIFT) | 222 (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_2_SHIFT) | 223 ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) 224 << R300_WRITE_ENA_2_SHIFT))); 225 226 if (info->accel_state->has_tcl) { 227 OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0); 228 OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000); 229 OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000); 230 OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000); 231 OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000); 232 OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE); 233 } 234 FINISH_ACCEL(); 235 236 /* pre-load the vertex shaders */ 237 if (info->accel_state->has_tcl) { 238 BEGIN_ACCEL(37); 239 /* exa composite shader program */ 240 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(0)); 241 /* PVS inst 0 - dst X,Y */ 242 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 243 (R300_PVS_DST_OPCODE(R300_VE_ADD) | 244 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 245 R300_PVS_DST_OFFSET(0) | 246 R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | 247 R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); 248 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 249 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 250 R300_PVS_SRC_OFFSET(0) | 251 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 252 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 253 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 254 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1))); 255 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 256 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 257 R300_PVS_SRC_OFFSET(0) | 258 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 259 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 260 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 261 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 262 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 263 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 264 R300_PVS_SRC_OFFSET(0) | 265 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 266 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 267 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 268 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 269 270 /* PVS inst 1 - src X */ 271 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 272 (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) | 273 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) | 274 R300_PVS_DST_OFFSET(0) | 275 R300_PVS_DST_WE_X)); 276 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 277 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 278 R300_PVS_SRC_OFFSET(6) | 279 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 280 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 281 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) | 282 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 283 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 284 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | 285 R300_PVS_SRC_OFFSET(0) | 286 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 287 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 288 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | 289 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 290 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 291 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 292 R300_PVS_SRC_OFFSET(6) | 293 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 294 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 295 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 296 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 297 298 /* PVS inst 2 - src Y */ 299 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 300 (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) | 301 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) | 302 R300_PVS_DST_OFFSET(0) | 303 R300_PVS_DST_WE_Y)); 304 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 305 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 306 R300_PVS_SRC_OFFSET(6) | 307 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 308 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 309 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) | 310 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 311 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 312 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | 313 R300_PVS_SRC_OFFSET(1) | 314 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 315 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 316 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | 317 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 318 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 319 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 320 R300_PVS_SRC_OFFSET(6) | 321 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 322 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 323 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 324 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 325 326 /* PVS inst 3 - src X / w */ 327 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 328 (R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) | 329 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 330 R300_PVS_DST_OFFSET(1) | 331 R300_PVS_DST_WE_X)); 332 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 333 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) | 334 R300_PVS_SRC_OFFSET(0) | 335 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 336 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 337 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 338 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 339 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 340 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | 341 R300_PVS_SRC_OFFSET(0) | 342 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_W) | 343 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 344 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 345 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 346 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 347 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 348 R300_PVS_SRC_OFFSET(6) | 349 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 350 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 351 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 352 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 353 354 /* PVS inst 4 - src y / h */ 355 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 356 (R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) | 357 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 358 R300_PVS_DST_OFFSET(1) | 359 R300_PVS_DST_WE_Y)); 360 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 361 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) | 362 R300_PVS_SRC_OFFSET(0) | 363 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 364 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 365 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 366 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 367 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 368 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | 369 R300_PVS_SRC_OFFSET(1) | 370 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 371 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_W) | 372 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 373 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 374 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 375 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 376 R300_PVS_SRC_OFFSET(6) | 377 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 378 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 379 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 380 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 381 382 /* PVS inst 5 - mask X */ 383 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 384 (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) | 385 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) | 386 R300_PVS_DST_OFFSET(0) | 387 R300_PVS_DST_WE_Z)); 388 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 389 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 390 R300_PVS_SRC_OFFSET(7) | 391 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 392 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 393 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) | 394 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 395 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 396 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | 397 R300_PVS_SRC_OFFSET(2) | 398 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 399 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 400 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | 401 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 402 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 403 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 404 R300_PVS_SRC_OFFSET(7) | 405 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 406 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 407 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 408 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 409 410 /* PVS inst 6 - mask Y */ 411 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 412 (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) | 413 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) | 414 R300_PVS_DST_OFFSET(0) | 415 R300_PVS_DST_WE_W)); 416 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 417 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 418 R300_PVS_SRC_OFFSET(7) | 419 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 420 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 421 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) | 422 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 423 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 424 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | 425 R300_PVS_SRC_OFFSET(3) | 426 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 427 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 428 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | 429 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 430 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 431 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 432 R300_PVS_SRC_OFFSET(7) | 433 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 434 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 435 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 436 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 437 438 /* PVS inst 7 - mask X / w */ 439 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 440 (R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) | 441 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 442 R300_PVS_DST_OFFSET(2) | 443 R300_PVS_DST_WE_X)); 444 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 445 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) | 446 R300_PVS_SRC_OFFSET(0) | 447 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_Z) | 448 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 449 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 450 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 451 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 452 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | 453 R300_PVS_SRC_OFFSET(2) | 454 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_W) | 455 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 456 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 457 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 458 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 459 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 460 R300_PVS_SRC_OFFSET(6) | 461 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 462 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 463 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 464 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 465 466 /* PVS inst 8 - mask y / h */ 467 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 468 (R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) | 469 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 470 R300_PVS_DST_OFFSET(2) | 471 R300_PVS_DST_WE_Y)); 472 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 473 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) | 474 R300_PVS_SRC_OFFSET(0) | 475 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 476 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_W) | 477 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 478 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 479 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 480 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | 481 R300_PVS_SRC_OFFSET(3) | 482 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 483 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_W) | 484 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 485 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 486 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 487 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 488 R300_PVS_SRC_OFFSET(6) | 489 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 490 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 491 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 492 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 493 FINISH_ACCEL(); 494 495 /* Xv shader program */ 496 BEGIN_ACCEL(9); 497 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(9)); 498 499 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 500 (R300_PVS_DST_OPCODE(R300_VE_ADD) | 501 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 502 R300_PVS_DST_OFFSET(0) | 503 R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | 504 R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); 505 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 506 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 507 R300_PVS_SRC_OFFSET(0) | 508 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 509 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 510 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 511 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1))); 512 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 513 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 514 R300_PVS_SRC_OFFSET(0) | 515 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 516 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 517 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 518 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 519 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 520 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 521 R300_PVS_SRC_OFFSET(0) | 522 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 523 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 524 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 525 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 526 527 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 528 (R300_PVS_DST_OPCODE(R300_VE_ADD) | 529 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 530 R300_PVS_DST_OFFSET(1) | 531 R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y)); 532 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 533 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 534 R300_PVS_SRC_OFFSET(6) | 535 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 536 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 537 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 538 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1))); 539 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 540 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 541 R300_PVS_SRC_OFFSET(6) | 542 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 543 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 544 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 545 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 546 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 547 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 548 R300_PVS_SRC_OFFSET(6) | 549 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 550 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 551 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 552 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 553 FINISH_ACCEL(); 554 555 /* Xv bicubic shader program */ 556 BEGIN_ACCEL(13); 557 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(11)); 558 /* PVS inst 0 */ 559 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 560 (R300_PVS_DST_OPCODE(R300_VE_ADD) | 561 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 562 R300_PVS_DST_OFFSET(0) | 563 R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | 564 R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); 565 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 566 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 567 R300_PVS_SRC_OFFSET(0) | 568 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 569 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 570 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 571 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1))); 572 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 573 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 574 R300_PVS_SRC_OFFSET(0) | 575 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 576 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 577 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 578 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 579 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 580 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 581 R300_PVS_SRC_OFFSET(0) | 582 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 583 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 584 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 585 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 586 587 /* PVS inst 1 */ 588 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 589 (R300_PVS_DST_OPCODE(R300_VE_ADD) | 590 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 591 R300_PVS_DST_OFFSET(1) | 592 R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | 593 R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); 594 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 595 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 596 R300_PVS_SRC_OFFSET(6) | 597 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 598 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 599 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 600 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1))); 601 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 602 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 603 R300_PVS_SRC_OFFSET(6) | 604 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 605 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 606 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 607 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 608 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 609 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 610 R300_PVS_SRC_OFFSET(6) | 611 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 612 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 613 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 614 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 615 616 /* PVS inst 2 */ 617 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 618 (R300_PVS_DST_OPCODE(R300_VE_ADD) | 619 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 620 R300_PVS_DST_OFFSET(2) | 621 R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | 622 R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); 623 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 624 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 625 R300_PVS_SRC_OFFSET(7) | 626 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 627 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 628 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 629 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1))); 630 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 631 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 632 R300_PVS_SRC_OFFSET(7) | 633 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 634 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 635 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 636 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 637 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 638 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 639 R300_PVS_SRC_OFFSET(7) | 640 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 641 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 642 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 643 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 644 FINISH_ACCEL(); 645 } 646 647 /* pre-load the RS instructions */ 648 BEGIN_ACCEL(4); 649 if (IS_R300_3D) { 650 /* rasterizer source table 651 * R300_RS_TEX_PTR is the offset into the input RS stream 652 * 0,1 are tex0 653 * 2,3 are tex1 654 */ 655 OUT_ACCEL_REG(R300_RS_IP_0, 656 (R300_RS_TEX_PTR(0) | 657 R300_RS_SEL_S(R300_RS_SEL_C0) | 658 R300_RS_SEL_T(R300_RS_SEL_C1) | 659 R300_RS_SEL_R(R300_RS_SEL_K0) | 660 R300_RS_SEL_Q(R300_RS_SEL_K1))); 661 OUT_ACCEL_REG(R300_RS_IP_1, 662 (R300_RS_TEX_PTR(2) | 663 R300_RS_SEL_S(R300_RS_SEL_C0) | 664 R300_RS_SEL_T(R300_RS_SEL_C1) | 665 R300_RS_SEL_R(R300_RS_SEL_K0) | 666 R300_RS_SEL_Q(R300_RS_SEL_K1))); 667 /* src tex */ 668 /* R300_INST_TEX_ID - select the RS source table entry 669 * R300_INST_TEX_ADDR - the FS temp register for the texture data 670 */ 671 OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) | 672 R300_RS_INST_TEX_CN_WRITE | 673 R300_INST_TEX_ADDR(0))); 674 /* mask tex */ 675 OUT_ACCEL_REG(R300_RS_INST_1, (R300_INST_TEX_ID(1) | 676 R300_RS_INST_TEX_CN_WRITE | 677 R300_INST_TEX_ADDR(1))); 678 679 } else { 680 /* rasterizer source table 681 * R300_RS_TEX_PTR is the offset into the input RS stream 682 * 0,1 are tex0 683 * 2,3 are tex1 684 */ 685 OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) | 686 (1 << R500_RS_IP_TEX_PTR_T_SHIFT) | 687 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | 688 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); 689 690 OUT_ACCEL_REG(R500_RS_IP_1, ((2 << R500_RS_IP_TEX_PTR_S_SHIFT) | 691 (3 << R500_RS_IP_TEX_PTR_T_SHIFT) | 692 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | 693 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); 694 /* src tex */ 695 /* R500_RS_INST_TEX_ID_SHIFT - select the RS source table entry 696 * R500_RS_INST_TEX_ADDR_SHIFT - the FS temp register for the texture data 697 */ 698 OUT_ACCEL_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) | 699 R500_RS_INST_TEX_CN_WRITE | 700 (0 << R500_RS_INST_TEX_ADDR_SHIFT))); 701 /* mask tex */ 702 OUT_ACCEL_REG(R500_RS_INST_1, ((1 << R500_RS_INST_TEX_ID_SHIFT) | 703 R500_RS_INST_TEX_CN_WRITE | 704 (1 << R500_RS_INST_TEX_ADDR_SHIFT))); 705 } 706 FINISH_ACCEL(); 707 708 if (IS_R300_3D) 709 BEGIN_ACCEL(4); 710 else { 711 BEGIN_ACCEL(6); 712 OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); 713 OUT_ACCEL_REG(R500_US_FC_CTRL, 0); 714 } 715 OUT_ACCEL_REG(R300_US_W_FMT, 0); 716 OUT_ACCEL_REG(R300_US_OUT_FMT_1, (R300_OUT_FMT_UNUSED | 717 R300_OUT_FMT_C0_SEL_BLUE | 718 R300_OUT_FMT_C1_SEL_GREEN | 719 R300_OUT_FMT_C2_SEL_RED | 720 R300_OUT_FMT_C3_SEL_ALPHA)); 721 OUT_ACCEL_REG(R300_US_OUT_FMT_2, (R300_OUT_FMT_UNUSED | 722 R300_OUT_FMT_C0_SEL_BLUE | 723 R300_OUT_FMT_C1_SEL_GREEN | 724 R300_OUT_FMT_C2_SEL_RED | 725 R300_OUT_FMT_C3_SEL_ALPHA)); 726 OUT_ACCEL_REG(R300_US_OUT_FMT_3, (R300_OUT_FMT_UNUSED | 727 R300_OUT_FMT_C0_SEL_BLUE | 728 R300_OUT_FMT_C1_SEL_GREEN | 729 R300_OUT_FMT_C2_SEL_RED | 730 R300_OUT_FMT_C3_SEL_ALPHA)); 731 FINISH_ACCEL(); 732 733 734 BEGIN_ACCEL(3); 735 OUT_ACCEL_REG(R300_FG_DEPTH_SRC, 0); 736 OUT_ACCEL_REG(R300_FG_FOG_BLEND, 0); 737 OUT_ACCEL_REG(R300_FG_ALPHA_FUNC, 0); 738 FINISH_ACCEL(); 739 740 BEGIN_ACCEL(13); 741 OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0); 742 OUT_ACCEL_REG(R300_RB3D_ZSTENCILCNTL, 0); 743 OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); 744 OUT_ACCEL_REG(R300_RB3D_BW_CNTL, 0); 745 OUT_ACCEL_REG(R300_RB3D_ZCNTL, 0); 746 OUT_ACCEL_REG(R300_RB3D_ZTOP, 0); 747 OUT_ACCEL_REG(R300_RB3D_ROPCNTL, 0); 748 749 OUT_ACCEL_REG(R300_RB3D_AARESOLVE_CTL, 0); 750 OUT_ACCEL_REG(R300_RB3D_COLOR_CHANNEL_MASK, (R300_BLUE_MASK_EN | 751 R300_GREEN_MASK_EN | 752 R300_RED_MASK_EN | 753 R300_ALPHA_MASK_EN)); 754 OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); 755 OUT_ACCEL_REG(R300_RB3D_CCTL, 0); 756 OUT_ACCEL_REG(R300_RB3D_DITHER_CTL, 0); 757 OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); 758 FINISH_ACCEL(); 759 760 BEGIN_ACCEL(5); 761 OUT_ACCEL_REG(R300_SC_EDGERULE, 0xA5294A5); 762 if (IS_R300_3D) { 763 /* clip has offset 1440 */ 764 OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1440 << R300_CLIP_X_SHIFT) | 765 (1440 << R300_CLIP_Y_SHIFT))); 766 OUT_ACCEL_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) | 767 (4080 << R300_CLIP_Y_SHIFT))); 768 } else { 769 OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) | 770 (0 << R300_CLIP_Y_SHIFT))); 771 OUT_ACCEL_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) | 772 (4080 << R300_CLIP_Y_SHIFT))); 773 } 774 OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA); 775 OUT_ACCEL_REG(R300_SC_SCREENDOOR, 0xffffff); 776 FINISH_ACCEL(); 777 } else if (IS_R200_3D) { 778 779 BEGIN_ACCEL(6); 780 if (info->ChipFamily == CHIP_FAMILY_RS300) { 781 OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS); 782 } else { 783 OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0); 784 } 785 OUT_ACCEL_REG(R200_PP_CNTL_X, 0); 786 OUT_ACCEL_REG(R200_PP_TXMULTI_CTL_0, 0); 787 OUT_ACCEL_REG(R200_SE_VTX_STATE_CNTL, 0); 788 OUT_ACCEL_REG(R200_SE_VTE_CNTL, 0); 789 OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE | 790 R200_VAP_VF_MAX_VTX_NUM); 791 FINISH_ACCEL(); 792 793 BEGIN_ACCEL(4); 794 OUT_ACCEL_REG(R200_RE_AUX_SCISSOR_CNTL, 0); 795 OUT_ACCEL_REG(R200_RE_CNTL, 0); 796 OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); 797 OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | 798 RADEON_BFACE_SOLID | 799 RADEON_FFACE_SOLID | 800 RADEON_VTX_PIX_CENTER_OGL | 801 RADEON_ROUND_MODE_ROUND | 802 RADEON_ROUND_PREC_4TH_PIX)); 803 FINISH_ACCEL(); 804 } else { 805 BEGIN_ACCEL(2); 806 if ((info->ChipFamily == CHIP_FAMILY_RADEON) || 807 (info->ChipFamily == CHIP_FAMILY_RV200)) 808 OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, 0); 809 else 810 OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS); 811 OUT_ACCEL_REG(RADEON_SE_COORD_FMT, 812 RADEON_VTX_XY_PRE_MULT_1_OVER_W0 | 813 RADEON_TEX1_W_ROUTING_USE_W0); 814 FINISH_ACCEL(); 815 816 BEGIN_ACCEL(2); 817 OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); 818 OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | 819 RADEON_BFACE_SOLID | 820 RADEON_FFACE_SOLID | 821 RADEON_VTX_PIX_CENTER_OGL | 822 RADEON_ROUND_MODE_ROUND | 823 RADEON_ROUND_PREC_4TH_PIX)); 824 FINISH_ACCEL(); 825 } 826 827} 828 829/* inserts a wait for vline in the command stream */ 830void FUNC_NAME(RADEONWaitForVLine)(ScrnInfoPtr pScrn, PixmapPtr pPix, 831 xf86CrtcPtr crtc, int start, int stop) 832{ 833 RADEONInfoPtr info = RADEONPTR(pScrn); 834 uint32_t offset; 835 ACCEL_PREAMBLE(); 836 837 if (!crtc) 838 return; 839 840 if (stop < start) 841 return; 842 843 if (!crtc->enabled) 844 return; 845 846 if (info->cs) { 847 if (pPix != pScrn->pScreen->GetScreenPixmap(pScrn->pScreen)) 848 return; 849 } else { 850#ifdef USE_EXA 851 if (info->useEXA) 852 offset = exaGetPixmapOffset(pPix); 853 else 854#endif 855 offset = pPix->devPrivate.ptr - info->FB; 856 857 /* if drawing to front buffer */ 858 if (offset != 0) 859 return; 860 } 861 862 start = max(start, 0); 863 stop = min(stop, crtc->mode.VDisplay); 864 865 if (start > crtc->mode.VDisplay) 866 return; 867 868#if defined(ACCEL_CP) && defined(XF86DRM_MODE) 869 if (info->cs) { 870 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 871 872 BEGIN_ACCEL(3); 873 if (IS_AVIVO_VARIANT) { 874 OUT_ACCEL_REG(AVIVO_D1MODE_VLINE_START_END, /* this is just a marker */ 875 ((start << AVIVO_D1MODE_VLINE_START_SHIFT) | 876 (stop << AVIVO_D1MODE_VLINE_END_SHIFT) | 877 AVIVO_D1MODE_VLINE_INV)); 878 } else { 879 OUT_ACCEL_REG(RADEON_CRTC_GUI_TRIG_VLINE, /* another placeholder */ 880 ((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) | 881 (stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) | 882 RADEON_CRTC_GUI_TRIG_VLINE_INV | 883 RADEON_CRTC_GUI_TRIG_VLINE_STALL)); 884 } 885 OUT_ACCEL_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE | 886 RADEON_ENG_DISPLAY_SELECT_CRTC0)); 887 888 OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_NOP, 0)); 889 OUT_RING(drmmode_crtc->mode_crtc->crtc_id); 890 FINISH_ACCEL(); 891 } else 892#endif 893 { 894 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 895 896 BEGIN_ACCEL(2); 897 if (IS_AVIVO_VARIANT) { 898 OUT_ACCEL_REG(AVIVO_D1MODE_VLINE_START_END + radeon_crtc->crtc_offset, 899 ((start << AVIVO_D1MODE_VLINE_START_SHIFT) | 900 (stop << AVIVO_D1MODE_VLINE_END_SHIFT) | 901 AVIVO_D1MODE_VLINE_INV)); 902 } else { 903 if (radeon_crtc->crtc_id == 0) 904 OUT_ACCEL_REG(RADEON_CRTC_GUI_TRIG_VLINE, 905 ((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) | 906 (stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) | 907 RADEON_CRTC_GUI_TRIG_VLINE_INV | 908 RADEON_CRTC_GUI_TRIG_VLINE_STALL)); 909 else 910 OUT_ACCEL_REG(RADEON_CRTC2_GUI_TRIG_VLINE, 911 ((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) | 912 (stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) | 913 RADEON_CRTC_GUI_TRIG_VLINE_INV | 914 RADEON_CRTC_GUI_TRIG_VLINE_STALL)); 915 } 916 917 if (radeon_crtc->crtc_id == 0) 918 OUT_ACCEL_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE | 919 RADEON_ENG_DISPLAY_SELECT_CRTC0)); 920 else 921 OUT_ACCEL_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE | 922 RADEON_ENG_DISPLAY_SELECT_CRTC1)); 923 FINISH_ACCEL(); 924 } 925} 926 927/* MMIO: 928 * 929 * Wait for the graphics engine to be completely idle: the FIFO has 930 * drained, the Pixel Cache is flushed, and the engine is idle. This is 931 * a standard "sync" function that will make the hardware "quiescent". 932 * 933 * CP: 934 * 935 * Wait until the CP is completely idle: the FIFO has drained and the CP 936 * is idle. 937 */ 938void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn) 939{ 940 RADEONInfoPtr info = RADEONPTR(pScrn); 941 unsigned char *RADEONMMIO = info->MMIO; 942 int i = 0; 943 944#ifdef ACCEL_CP 945 /* Make sure the CP is idle first */ 946 if (info->cp->CPStarted) { 947 int ret; 948 949 FLUSH_RING(); 950 951 for (;;) { 952 do { 953 ret = drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_IDLE); 954 if (ret && ret != -EBUSY) { 955 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 956 "%s: CP idle %d\n", __FUNCTION__, ret); 957 } 958 } while ((ret == -EBUSY) && (i++ < RADEON_TIMEOUT)); 959 960 if (ret == 0) return; 961 962 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 963 "Idle timed out, resetting engine...\n"); 964 if (info->ChipFamily < CHIP_FAMILY_R600) { 965 RADEONEngineReset(pScrn); 966 RADEONEngineRestore(pScrn); 967 } else 968 R600EngineReset(pScrn); 969 970 /* Always restart the engine when doing CP 2D acceleration */ 971 RADEONCP_RESET(pScrn, info); 972 RADEONCP_START(pScrn, info); 973 } 974 } 975#endif 976 977 if (info->ChipFamily >= CHIP_FAMILY_R600) { 978 if (!info->accelOn) 979 return; 980 981 /* Wait for the engine to go idle */ 982 if (info->ChipFamily >= CHIP_FAMILY_RV770) 983 R600WaitForFifoFunction(pScrn, 8); 984 else 985 R600WaitForFifoFunction(pScrn, 16); 986 987 for (;;) { 988 for (i = 0; i < RADEON_TIMEOUT; i++) { 989 if (!(INREG(R600_GRBM_STATUS) & R600_GUI_ACTIVE)) 990 return; 991 } 992 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 993 "Idle timed out: stat=0x%08x\n", 994 (unsigned int)INREG(R600_GRBM_STATUS)); 995 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 996 "Idle timed out, resetting engine...\n"); 997 R600EngineReset(pScrn); 998#ifdef XF86DRI 999 if (info->directRenderingEnabled) { 1000 RADEONCP_RESET(pScrn, info); 1001 RADEONCP_START(pScrn, info); 1002 } 1003#endif 1004 } 1005 } else { 1006 /* Wait for the engine to go idle */ 1007 RADEONWaitForFifoFunction(pScrn, 64); 1008 1009 for (;;) { 1010 for (i = 0; i < RADEON_TIMEOUT; i++) { 1011 if (!(INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)) { 1012 RADEONEngineFlush(pScrn); 1013 return; 1014 } 1015 } 1016 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 1017 "Idle timed out: %u entries, stat=0x%08x\n", 1018 (unsigned int)INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, 1019 (unsigned int)INREG(RADEON_RBBM_STATUS)); 1020 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1021 "Idle timed out, resetting engine...\n"); 1022 RADEONEngineReset(pScrn); 1023 RADEONEngineRestore(pScrn); 1024#ifdef XF86DRI 1025 if (info->directRenderingEnabled) { 1026 RADEONCP_RESET(pScrn, info); 1027 RADEONCP_START(pScrn, info); 1028 } 1029#endif 1030 } 1031 } 1032} 1033