radeon_commonfuncs.c revision ad43ddac
1/* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining 8 * a copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation on the rights to use, copy, modify, merge, 11 * publish, distribute, sublicense, and/or sell copies of the Software, 12 * and to permit persons to whom the Software is furnished to do so, 13 * subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 */ 28 29#ifdef HAVE_CONFIG_H 30#include "config.h" 31#endif 32 33#include "ati_pciids_gen.h" 34 35#if defined(ACCEL_MMIO) && defined(ACCEL_CP) 36#error Cannot define both MMIO and CP acceleration! 37#endif 38 39#if !defined(UNIXCPP) || defined(ANSICPP) 40#define FUNC_NAME_CAT(prefix,suffix) prefix##suffix 41#else 42#define FUNC_NAME_CAT(prefix,suffix) prefix/**/suffix 43#endif 44 45#ifdef ACCEL_MMIO 46#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,MMIO) 47#else 48#ifdef ACCEL_CP 49#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,CP) 50#else 51#error No accel type defined! 52#endif 53#endif 54 55static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) 56{ 57 RADEONInfoPtr info = RADEONPTR(pScrn); 58 uint32_t gb_tile_config, su_reg_dest, vap_cntl; 59 int size; 60 ACCEL_PREAMBLE(); 61 62 info->accel_state->texW[0] = info->accel_state->texH[0] = 63 info->accel_state->texW[1] = info->accel_state->texH[1] = 1; 64 65 if (IS_R300_3D || IS_R500_3D) { 66 67 if (!info->cs) { 68 BEGIN_ACCEL(3); 69 OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); 70 OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); 71 OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); 72 FINISH_ACCEL(); 73 } 74 75 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 76 77 switch(info->accel_state->num_gb_pipes) { 78 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; 79 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; 80 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; 81 default: 82 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; 83 } 84 85 if (!info->cs) { 86 size = (info->ChipFamily >= CHIP_FAMILY_R420) ? 5 : 4; 87 BEGIN_ACCEL(size); 88 OUT_ACCEL_REG(R300_GB_TILE_CONFIG, gb_tile_config); 89 OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); 90 if (info->ChipFamily >= CHIP_FAMILY_R420) 91 OUT_ACCEL_REG(R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG); 92 OUT_ACCEL_REG(R300_GB_SELECT, 0); 93 OUT_ACCEL_REG(R300_GB_ENABLE, 0); 94 FINISH_ACCEL(); 95 } 96 97 if (IS_R500_3D) { 98 if (!info->cs) { 99 su_reg_dest = ((1 << info->accel_state->num_gb_pipes) - 1); 100 BEGIN_ACCEL(2); 101 OUT_ACCEL_REG(R500_SU_REG_DEST, su_reg_dest); 102 OUT_ACCEL_REG(R500_VAP_INDEX_OFFSET, 0); 103 FINISH_ACCEL(); 104 } 105 } 106 107 BEGIN_ACCEL(3); 108 OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); 109 OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); 110 OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); 111 FINISH_ACCEL(); 112 113 BEGIN_ACCEL(3); 114 OUT_ACCEL_REG(R300_GB_AA_CONFIG, 0); 115 OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); 116 OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); 117 FINISH_ACCEL(); 118 119 if (!info->cs) { 120 BEGIN_ACCEL(3); 121 OUT_ACCEL_REG(R300_GB_MSPOS0, ((6 << R300_MS_X0_SHIFT) | 122 (6 << R300_MS_Y0_SHIFT) | 123 (6 << R300_MS_X1_SHIFT) | 124 (6 << R300_MS_Y1_SHIFT) | 125 (6 << R300_MS_X2_SHIFT) | 126 (6 << R300_MS_Y2_SHIFT) | 127 (6 << R300_MSBD0_Y_SHIFT) | 128 (6 << R300_MSBD0_X_SHIFT))); 129 OUT_ACCEL_REG(R300_GB_MSPOS1, ((6 << R300_MS_X3_SHIFT) | 130 (6 << R300_MS_Y3_SHIFT) | 131 (6 << R300_MS_X4_SHIFT) | 132 (6 << R300_MS_Y4_SHIFT) | 133 (6 << R300_MS_X5_SHIFT) | 134 (6 << R300_MS_Y5_SHIFT) | 135 (6 << R300_MSBD1_SHIFT))); 136 OUT_ACCEL_REG(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); 137 FINISH_ACCEL(); 138 } 139 140 BEGIN_ACCEL(4); 141 OUT_ACCEL_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); 142 OUT_ACCEL_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST | 143 R300_COLOR_ROUND_NEAREST)); 144 OUT_ACCEL_REG(R300_GA_COLOR_CONTROL, (R300_RGB0_SHADING_GOURAUD | 145 R300_ALPHA0_SHADING_GOURAUD | 146 R300_RGB1_SHADING_GOURAUD | 147 R300_ALPHA1_SHADING_GOURAUD | 148 R300_RGB2_SHADING_GOURAUD | 149 R300_ALPHA2_SHADING_GOURAUD | 150 R300_RGB3_SHADING_GOURAUD | 151 R300_ALPHA3_SHADING_GOURAUD)); 152 OUT_ACCEL_REG(R300_GA_OFFSET, 0); 153 FINISH_ACCEL(); 154 155 BEGIN_ACCEL(5); 156 OUT_ACCEL_REG(R300_SU_TEX_WRAP, 0); 157 OUT_ACCEL_REG(R300_SU_POLY_OFFSET_ENABLE, 0); 158 OUT_ACCEL_REG(R300_SU_CULL_MODE, R300_FACE_NEG); 159 OUT_ACCEL_REG(R300_SU_DEPTH_SCALE, 0x4b7fffff); 160 OUT_ACCEL_REG(R300_SU_DEPTH_OFFSET, 0); 161 FINISH_ACCEL(); 162 163 /* setup the VAP */ 164 if (info->accel_state->has_tcl) 165 vap_cntl = ((5 << R300_PVS_NUM_SLOTS_SHIFT) | 166 (5 << R300_PVS_NUM_CNTLRS_SHIFT) | 167 (9 << R300_VF_MAX_VTX_NUM_SHIFT)); 168 else 169 vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) | 170 (5 << R300_PVS_NUM_CNTLRS_SHIFT) | 171 (5 << R300_VF_MAX_VTX_NUM_SHIFT)); 172 173 if (info->ChipFamily == CHIP_FAMILY_RV515) 174 vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT); 175 else if ((info->ChipFamily == CHIP_FAMILY_RV530) || 176 (info->ChipFamily == CHIP_FAMILY_RV560) || 177 (info->ChipFamily == CHIP_FAMILY_RV570)) 178 vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT); 179 else if ((info->ChipFamily == CHIP_FAMILY_RV410) || 180 (info->ChipFamily == CHIP_FAMILY_R420)) 181 vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT); 182 else if ((info->ChipFamily == CHIP_FAMILY_R520) || 183 (info->ChipFamily == CHIP_FAMILY_R580)) 184 vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT); 185 else 186 vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT); 187 188 if (info->accel_state->has_tcl) 189 BEGIN_ACCEL(15); 190 else 191 BEGIN_ACCEL(9); 192 OUT_ACCEL_REG(R300_VAP_VTX_STATE_CNTL, 0); 193 OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); 194 195 if (info->accel_state->has_tcl) 196 OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0); 197 else 198 OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS); 199 OUT_ACCEL_REG(R300_VAP_CNTL, vap_cntl); 200 OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); 201 OUT_ACCEL_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT); 202 OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0); 203 204 OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 205 ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) | 206 (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) | 207 (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) | 208 (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) | 209 ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) 210 << R300_WRITE_ENA_0_SHIFT) | 211 (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) | 212 (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) | 213 (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) | 214 (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) | 215 ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) 216 << R300_WRITE_ENA_1_SHIFT))); 217 OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, 218 ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) | 219 (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) | 220 (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_2_SHIFT) | 221 (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_2_SHIFT) | 222 ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) 223 << R300_WRITE_ENA_2_SHIFT))); 224 225 if (info->accel_state->has_tcl) { 226 OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0); 227 OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000); 228 OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000); 229 OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000); 230 OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000); 231 OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE); 232 } 233 FINISH_ACCEL(); 234 235 /* pre-load the vertex shaders */ 236 if (info->accel_state->has_tcl) { 237 BEGIN_ACCEL(37); 238 /* exa composite shader program */ 239 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(0)); 240 /* PVS inst 0 - dst X,Y */ 241 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 242 (R300_PVS_DST_OPCODE(R300_VE_ADD) | 243 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 244 R300_PVS_DST_OFFSET(0) | 245 R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | 246 R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); 247 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 248 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 249 R300_PVS_SRC_OFFSET(0) | 250 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 251 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 252 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 253 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1))); 254 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 255 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 256 R300_PVS_SRC_OFFSET(0) | 257 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 258 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 259 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 260 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 261 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 262 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 263 R300_PVS_SRC_OFFSET(0) | 264 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 265 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 266 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 267 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 268 269 /* PVS inst 1 - src X */ 270 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 271 (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) | 272 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) | 273 R300_PVS_DST_OFFSET(0) | 274 R300_PVS_DST_WE_X)); 275 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 276 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 277 R300_PVS_SRC_OFFSET(6) | 278 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 279 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 280 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) | 281 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 282 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 283 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | 284 R300_PVS_SRC_OFFSET(0) | 285 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 286 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 287 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | 288 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 289 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 290 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 291 R300_PVS_SRC_OFFSET(6) | 292 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 293 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 294 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 295 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 296 297 /* PVS inst 2 - src Y */ 298 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 299 (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) | 300 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) | 301 R300_PVS_DST_OFFSET(0) | 302 R300_PVS_DST_WE_Y)); 303 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 304 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 305 R300_PVS_SRC_OFFSET(6) | 306 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 307 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 308 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) | 309 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 310 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 311 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | 312 R300_PVS_SRC_OFFSET(1) | 313 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 314 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 315 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | 316 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 317 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 318 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 319 R300_PVS_SRC_OFFSET(6) | 320 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 321 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 322 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 323 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 324 325 /* PVS inst 3 - src X / w */ 326 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 327 (R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) | 328 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 329 R300_PVS_DST_OFFSET(1) | 330 R300_PVS_DST_WE_X)); 331 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 332 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) | 333 R300_PVS_SRC_OFFSET(0) | 334 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 335 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 336 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 337 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 338 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 339 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | 340 R300_PVS_SRC_OFFSET(0) | 341 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_W) | 342 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 343 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 344 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 345 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 346 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 347 R300_PVS_SRC_OFFSET(6) | 348 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 349 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 350 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 351 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 352 353 /* PVS inst 4 - src y / h */ 354 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 355 (R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) | 356 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 357 R300_PVS_DST_OFFSET(1) | 358 R300_PVS_DST_WE_Y)); 359 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 360 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) | 361 R300_PVS_SRC_OFFSET(0) | 362 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 363 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 364 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 365 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 366 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 367 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | 368 R300_PVS_SRC_OFFSET(1) | 369 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 370 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_W) | 371 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 372 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 373 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 374 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 375 R300_PVS_SRC_OFFSET(6) | 376 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 377 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 378 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 379 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 380 381 /* PVS inst 5 - mask X */ 382 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 383 (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) | 384 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) | 385 R300_PVS_DST_OFFSET(0) | 386 R300_PVS_DST_WE_Z)); 387 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 388 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 389 R300_PVS_SRC_OFFSET(7) | 390 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 391 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 392 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) | 393 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 394 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 395 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | 396 R300_PVS_SRC_OFFSET(2) | 397 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 398 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 399 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | 400 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 401 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 402 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 403 R300_PVS_SRC_OFFSET(7) | 404 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 405 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 406 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 407 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 408 409 /* PVS inst 6 - mask Y */ 410 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 411 (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) | 412 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) | 413 R300_PVS_DST_OFFSET(0) | 414 R300_PVS_DST_WE_W)); 415 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 416 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 417 R300_PVS_SRC_OFFSET(7) | 418 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 419 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 420 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) | 421 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 422 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 423 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | 424 R300_PVS_SRC_OFFSET(3) | 425 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 426 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 427 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | 428 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 429 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 430 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 431 R300_PVS_SRC_OFFSET(7) | 432 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 433 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 434 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 435 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 436 437 /* PVS inst 7 - mask X / w */ 438 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 439 (R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) | 440 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 441 R300_PVS_DST_OFFSET(2) | 442 R300_PVS_DST_WE_X)); 443 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 444 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) | 445 R300_PVS_SRC_OFFSET(0) | 446 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_Z) | 447 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 448 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 449 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 450 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 451 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | 452 R300_PVS_SRC_OFFSET(2) | 453 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_W) | 454 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 455 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 456 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 457 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 458 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 459 R300_PVS_SRC_OFFSET(6) | 460 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 461 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 462 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 463 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 464 465 /* PVS inst 8 - mask y / h */ 466 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 467 (R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) | 468 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 469 R300_PVS_DST_OFFSET(2) | 470 R300_PVS_DST_WE_Y)); 471 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 472 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) | 473 R300_PVS_SRC_OFFSET(0) | 474 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 475 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_W) | 476 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 477 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 478 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 479 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | 480 R300_PVS_SRC_OFFSET(3) | 481 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 482 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_W) | 483 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 484 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 485 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 486 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 487 R300_PVS_SRC_OFFSET(6) | 488 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 489 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 490 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 491 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 492 FINISH_ACCEL(); 493 494 /* Xv shader program */ 495 BEGIN_ACCEL(9); 496 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(9)); 497 498 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 499 (R300_PVS_DST_OPCODE(R300_VE_ADD) | 500 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 501 R300_PVS_DST_OFFSET(0) | 502 R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | 503 R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); 504 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 505 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 506 R300_PVS_SRC_OFFSET(0) | 507 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 508 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 509 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 510 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1))); 511 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 512 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 513 R300_PVS_SRC_OFFSET(0) | 514 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 515 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 516 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 517 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 518 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 519 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 520 R300_PVS_SRC_OFFSET(0) | 521 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 522 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 523 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 524 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 525 526 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 527 (R300_PVS_DST_OPCODE(R300_VE_ADD) | 528 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 529 R300_PVS_DST_OFFSET(1) | 530 R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y)); 531 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 532 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 533 R300_PVS_SRC_OFFSET(6) | 534 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 535 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 536 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 537 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1))); 538 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 539 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 540 R300_PVS_SRC_OFFSET(6) | 541 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 542 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 543 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 544 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 545 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 546 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 547 R300_PVS_SRC_OFFSET(6) | 548 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 549 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 550 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 551 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 552 FINISH_ACCEL(); 553 554 /* Xv bicubic shader program */ 555 BEGIN_ACCEL(13); 556 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(11)); 557 /* PVS inst 0 */ 558 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 559 (R300_PVS_DST_OPCODE(R300_VE_ADD) | 560 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 561 R300_PVS_DST_OFFSET(0) | 562 R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | 563 R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); 564 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 565 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 566 R300_PVS_SRC_OFFSET(0) | 567 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 568 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 569 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 570 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1))); 571 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 572 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 573 R300_PVS_SRC_OFFSET(0) | 574 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 575 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 576 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 577 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 578 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 579 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 580 R300_PVS_SRC_OFFSET(0) | 581 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 582 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 583 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 584 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 585 586 /* PVS inst 1 */ 587 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 588 (R300_PVS_DST_OPCODE(R300_VE_ADD) | 589 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 590 R300_PVS_DST_OFFSET(1) | 591 R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | 592 R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); 593 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 594 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 595 R300_PVS_SRC_OFFSET(6) | 596 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 597 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 598 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 599 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1))); 600 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 601 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 602 R300_PVS_SRC_OFFSET(6) | 603 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 604 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 605 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 606 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 607 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 608 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 609 R300_PVS_SRC_OFFSET(6) | 610 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 611 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 612 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 613 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 614 615 /* PVS inst 2 */ 616 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 617 (R300_PVS_DST_OPCODE(R300_VE_ADD) | 618 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 619 R300_PVS_DST_OFFSET(2) | 620 R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | 621 R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); 622 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 623 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 624 R300_PVS_SRC_OFFSET(7) | 625 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 626 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 627 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 628 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1))); 629 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 630 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 631 R300_PVS_SRC_OFFSET(7) | 632 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 633 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 634 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 635 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 636 OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, 637 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 638 R300_PVS_SRC_OFFSET(7) | 639 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 640 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 641 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 642 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 643 FINISH_ACCEL(); 644 } 645 646 /* pre-load the RS instructions */ 647 BEGIN_ACCEL(4); 648 if (IS_R300_3D) { 649 /* rasterizer source table 650 * R300_RS_TEX_PTR is the offset into the input RS stream 651 * 0,1 are tex0 652 * 2,3 are tex1 653 */ 654 OUT_ACCEL_REG(R300_RS_IP_0, 655 (R300_RS_TEX_PTR(0) | 656 R300_RS_SEL_S(R300_RS_SEL_C0) | 657 R300_RS_SEL_T(R300_RS_SEL_C1) | 658 R300_RS_SEL_R(R300_RS_SEL_K0) | 659 R300_RS_SEL_Q(R300_RS_SEL_K1))); 660 OUT_ACCEL_REG(R300_RS_IP_1, 661 (R300_RS_TEX_PTR(2) | 662 R300_RS_SEL_S(R300_RS_SEL_C0) | 663 R300_RS_SEL_T(R300_RS_SEL_C1) | 664 R300_RS_SEL_R(R300_RS_SEL_K0) | 665 R300_RS_SEL_Q(R300_RS_SEL_K1))); 666 /* src tex */ 667 /* R300_INST_TEX_ID - select the RS source table entry 668 * R300_INST_TEX_ADDR - the FS temp register for the texture data 669 */ 670 OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) | 671 R300_RS_INST_TEX_CN_WRITE | 672 R300_INST_TEX_ADDR(0))); 673 /* mask tex */ 674 OUT_ACCEL_REG(R300_RS_INST_1, (R300_INST_TEX_ID(1) | 675 R300_RS_INST_TEX_CN_WRITE | 676 R300_INST_TEX_ADDR(1))); 677 678 } else { 679 /* rasterizer source table 680 * R300_RS_TEX_PTR is the offset into the input RS stream 681 * 0,1 are tex0 682 * 2,3 are tex1 683 */ 684 OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) | 685 (1 << R500_RS_IP_TEX_PTR_T_SHIFT) | 686 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | 687 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); 688 689 OUT_ACCEL_REG(R500_RS_IP_1, ((2 << R500_RS_IP_TEX_PTR_S_SHIFT) | 690 (3 << R500_RS_IP_TEX_PTR_T_SHIFT) | 691 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | 692 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); 693 /* src tex */ 694 /* R500_RS_INST_TEX_ID_SHIFT - select the RS source table entry 695 * R500_RS_INST_TEX_ADDR_SHIFT - the FS temp register for the texture data 696 */ 697 OUT_ACCEL_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) | 698 R500_RS_INST_TEX_CN_WRITE | 699 (0 << R500_RS_INST_TEX_ADDR_SHIFT))); 700 /* mask tex */ 701 OUT_ACCEL_REG(R500_RS_INST_1, ((1 << R500_RS_INST_TEX_ID_SHIFT) | 702 R500_RS_INST_TEX_CN_WRITE | 703 (1 << R500_RS_INST_TEX_ADDR_SHIFT))); 704 } 705 FINISH_ACCEL(); 706 707 if (IS_R300_3D) 708 BEGIN_ACCEL(4); 709 else { 710 BEGIN_ACCEL(6); 711 OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); 712 OUT_ACCEL_REG(R500_US_FC_CTRL, 0); 713 } 714 OUT_ACCEL_REG(R300_US_W_FMT, 0); 715 OUT_ACCEL_REG(R300_US_OUT_FMT_1, (R300_OUT_FMT_UNUSED | 716 R300_OUT_FMT_C0_SEL_BLUE | 717 R300_OUT_FMT_C1_SEL_GREEN | 718 R300_OUT_FMT_C2_SEL_RED | 719 R300_OUT_FMT_C3_SEL_ALPHA)); 720 OUT_ACCEL_REG(R300_US_OUT_FMT_2, (R300_OUT_FMT_UNUSED | 721 R300_OUT_FMT_C0_SEL_BLUE | 722 R300_OUT_FMT_C1_SEL_GREEN | 723 R300_OUT_FMT_C2_SEL_RED | 724 R300_OUT_FMT_C3_SEL_ALPHA)); 725 OUT_ACCEL_REG(R300_US_OUT_FMT_3, (R300_OUT_FMT_UNUSED | 726 R300_OUT_FMT_C0_SEL_BLUE | 727 R300_OUT_FMT_C1_SEL_GREEN | 728 R300_OUT_FMT_C2_SEL_RED | 729 R300_OUT_FMT_C3_SEL_ALPHA)); 730 FINISH_ACCEL(); 731 732 733 BEGIN_ACCEL(3); 734 OUT_ACCEL_REG(R300_FG_DEPTH_SRC, 0); 735 OUT_ACCEL_REG(R300_FG_FOG_BLEND, 0); 736 OUT_ACCEL_REG(R300_FG_ALPHA_FUNC, 0); 737 FINISH_ACCEL(); 738 739 BEGIN_ACCEL(13); 740 OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0); 741 OUT_ACCEL_REG(R300_RB3D_ZSTENCILCNTL, 0); 742 OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); 743 OUT_ACCEL_REG(R300_RB3D_BW_CNTL, 0); 744 OUT_ACCEL_REG(R300_RB3D_ZCNTL, 0); 745 OUT_ACCEL_REG(R300_RB3D_ZTOP, 0); 746 OUT_ACCEL_REG(R300_RB3D_ROPCNTL, 0); 747 748 OUT_ACCEL_REG(R300_RB3D_AARESOLVE_CTL, 0); 749 OUT_ACCEL_REG(R300_RB3D_COLOR_CHANNEL_MASK, (R300_BLUE_MASK_EN | 750 R300_GREEN_MASK_EN | 751 R300_RED_MASK_EN | 752 R300_ALPHA_MASK_EN)); 753 OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); 754 OUT_ACCEL_REG(R300_RB3D_CCTL, 0); 755 OUT_ACCEL_REG(R300_RB3D_DITHER_CTL, 0); 756 OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); 757 FINISH_ACCEL(); 758 759 BEGIN_ACCEL(5); 760 OUT_ACCEL_REG(R300_SC_EDGERULE, 0xA5294A5); 761 if (IS_R300_3D) { 762 /* clip has offset 1440 */ 763 OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1440 << R300_CLIP_X_SHIFT) | 764 (1440 << R300_CLIP_Y_SHIFT))); 765 OUT_ACCEL_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) | 766 (4080 << R300_CLIP_Y_SHIFT))); 767 } else { 768 OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) | 769 (0 << R300_CLIP_Y_SHIFT))); 770 OUT_ACCEL_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) | 771 (4080 << R300_CLIP_Y_SHIFT))); 772 } 773 OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA); 774 OUT_ACCEL_REG(R300_SC_SCREENDOOR, 0xffffff); 775 FINISH_ACCEL(); 776 } else if (IS_R200_3D) { 777 778 BEGIN_ACCEL(6); 779 if (info->ChipFamily == CHIP_FAMILY_RS300) { 780 OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS); 781 } else { 782 OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0); 783 } 784 OUT_ACCEL_REG(R200_PP_CNTL_X, 0); 785 OUT_ACCEL_REG(R200_PP_TXMULTI_CTL_0, 0); 786 OUT_ACCEL_REG(R200_SE_VTX_STATE_CNTL, 0); 787 OUT_ACCEL_REG(R200_SE_VTE_CNTL, 0); 788 OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE | 789 R200_VAP_VF_MAX_VTX_NUM); 790 FINISH_ACCEL(); 791 792 BEGIN_ACCEL(4); 793 OUT_ACCEL_REG(R200_RE_AUX_SCISSOR_CNTL, 0); 794 OUT_ACCEL_REG(R200_RE_CNTL, 0); 795 OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); 796 OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | 797 RADEON_BFACE_SOLID | 798 RADEON_FFACE_SOLID | 799 RADEON_VTX_PIX_CENTER_OGL | 800 RADEON_ROUND_MODE_ROUND | 801 RADEON_ROUND_PREC_4TH_PIX)); 802 FINISH_ACCEL(); 803 } else { 804 BEGIN_ACCEL(2); 805 if ((info->ChipFamily == CHIP_FAMILY_RADEON) || 806 (info->ChipFamily == CHIP_FAMILY_RV200)) 807 OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, 0); 808 else 809 OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS); 810 OUT_ACCEL_REG(RADEON_SE_COORD_FMT, 811 RADEON_VTX_XY_PRE_MULT_1_OVER_W0 | 812 RADEON_TEX1_W_ROUTING_USE_W0); 813 FINISH_ACCEL(); 814 815 BEGIN_ACCEL(2); 816 OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); 817 OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | 818 RADEON_BFACE_SOLID | 819 RADEON_FFACE_SOLID | 820 RADEON_VTX_PIX_CENTER_OGL | 821 RADEON_ROUND_MODE_ROUND | 822 RADEON_ROUND_PREC_4TH_PIX)); 823 FINISH_ACCEL(); 824 } 825 826} 827 828/* inserts a wait for vline in the command stream */ 829void FUNC_NAME(RADEONWaitForVLine)(ScrnInfoPtr pScrn, PixmapPtr pPix, 830 xf86CrtcPtr crtc, int start, int stop) 831{ 832 RADEONInfoPtr info = RADEONPTR(pScrn); 833 uint32_t offset; 834 ACCEL_PREAMBLE(); 835 836 if (!crtc) 837 return; 838 839 if (stop < start) 840 return; 841 842 if (!crtc->enabled) 843 return; 844 845 if (info->cs) { 846 if (pPix != pScrn->pScreen->GetScreenPixmap(pScrn->pScreen)) 847 return; 848 } else { 849#ifdef USE_EXA 850 if (info->useEXA) 851 offset = exaGetPixmapOffset(pPix); 852 else 853#endif 854 offset = pPix->devPrivate.ptr - info->FB; 855 856 /* if drawing to front buffer */ 857 if (offset != 0) 858 return; 859 } 860 861 start = max(start, 0); 862 stop = min(stop, crtc->mode.VDisplay); 863 864 if (start > crtc->mode.VDisplay) 865 return; 866 867#if defined(ACCEL_CP) && defined(XF86DRM_MODE) 868 if (info->cs) { 869 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 870 871 BEGIN_ACCEL(3); 872 if (IS_AVIVO_VARIANT) { 873 OUT_ACCEL_REG(AVIVO_D1MODE_VLINE_START_END, /* this is just a marker */ 874 ((start << AVIVO_D1MODE_VLINE_START_SHIFT) | 875 (stop << AVIVO_D1MODE_VLINE_END_SHIFT) | 876 AVIVO_D1MODE_VLINE_INV)); 877 } else { 878 OUT_ACCEL_REG(RADEON_CRTC_GUI_TRIG_VLINE, /* another placeholder */ 879 ((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) | 880 (stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) | 881 RADEON_CRTC_GUI_TRIG_VLINE_INV | 882 RADEON_CRTC_GUI_TRIG_VLINE_STALL)); 883 } 884 OUT_ACCEL_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE | 885 RADEON_ENG_DISPLAY_SELECT_CRTC0)); 886 887 OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_NOP, 0)); 888 OUT_RING(drmmode_crtc->mode_crtc->crtc_id); 889 FINISH_ACCEL(); 890 } else 891#endif 892 { 893 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 894 895 BEGIN_ACCEL(2); 896 if (IS_AVIVO_VARIANT) { 897 OUT_ACCEL_REG(AVIVO_D1MODE_VLINE_START_END + radeon_crtc->crtc_offset, 898 ((start << AVIVO_D1MODE_VLINE_START_SHIFT) | 899 (stop << AVIVO_D1MODE_VLINE_END_SHIFT) | 900 AVIVO_D1MODE_VLINE_INV)); 901 } else { 902 if (radeon_crtc->crtc_id == 0) 903 OUT_ACCEL_REG(RADEON_CRTC_GUI_TRIG_VLINE, 904 ((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) | 905 (stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) | 906 RADEON_CRTC_GUI_TRIG_VLINE_INV | 907 RADEON_CRTC_GUI_TRIG_VLINE_STALL)); 908 else 909 OUT_ACCEL_REG(RADEON_CRTC2_GUI_TRIG_VLINE, 910 ((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) | 911 (stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) | 912 RADEON_CRTC_GUI_TRIG_VLINE_INV | 913 RADEON_CRTC_GUI_TRIG_VLINE_STALL)); 914 } 915 916 if (radeon_crtc->crtc_id == 0) 917 OUT_ACCEL_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE | 918 RADEON_ENG_DISPLAY_SELECT_CRTC0)); 919 else 920 OUT_ACCEL_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE | 921 RADEON_ENG_DISPLAY_SELECT_CRTC1)); 922 FINISH_ACCEL(); 923 } 924} 925 926/* MMIO: 927 * 928 * Wait for the graphics engine to be completely idle: the FIFO has 929 * drained, the Pixel Cache is flushed, and the engine is idle. This is 930 * a standard "sync" function that will make the hardware "quiescent". 931 * 932 * CP: 933 * 934 * Wait until the CP is completely idle: the FIFO has drained and the CP 935 * is idle. 936 */ 937void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn) 938{ 939 RADEONInfoPtr info = RADEONPTR(pScrn); 940 unsigned char *RADEONMMIO = info->MMIO; 941 int i = 0; 942 943#ifdef ACCEL_CP 944 /* Make sure the CP is idle first */ 945 if (info->cp->CPStarted) { 946 int ret; 947 948 FLUSH_RING(); 949 950 for (;;) { 951 do { 952 ret = drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_IDLE); 953 if (ret && ret != -EBUSY) { 954 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 955 "%s: CP idle %d\n", __FUNCTION__, ret); 956 } 957 } while ((ret == -EBUSY) && (i++ < RADEON_TIMEOUT)); 958 959 if (ret == 0) return; 960 961 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 962 "Idle timed out, resetting engine...\n"); 963 if (info->ChipFamily < CHIP_FAMILY_R600) { 964 RADEONEngineReset(pScrn); 965 RADEONEngineRestore(pScrn); 966 } else 967 R600EngineReset(pScrn); 968 969 /* Always restart the engine when doing CP 2D acceleration */ 970 RADEONCP_RESET(pScrn, info); 971 RADEONCP_START(pScrn, info); 972 } 973 } 974#endif 975 976 if (info->ChipFamily >= CHIP_FAMILY_R600) { 977 if (!info->accelOn) 978 return; 979 980 /* Wait for the engine to go idle */ 981 if (info->ChipFamily >= CHIP_FAMILY_RV770) 982 R600WaitForFifoFunction(pScrn, 8); 983 else 984 R600WaitForFifoFunction(pScrn, 16); 985 986 for (;;) { 987 for (i = 0; i < RADEON_TIMEOUT; i++) { 988 if (!(INREG(R600_GRBM_STATUS) & R600_GUI_ACTIVE)) 989 return; 990 } 991 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 992 "Idle timed out: stat=0x%08x\n", 993 (unsigned int)INREG(R600_GRBM_STATUS)); 994 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 995 "Idle timed out, resetting engine...\n"); 996 R600EngineReset(pScrn); 997#ifdef XF86DRI 998 if (info->directRenderingEnabled) { 999 RADEONCP_RESET(pScrn, info); 1000 RADEONCP_START(pScrn, info); 1001 } 1002#endif 1003 } 1004 } else { 1005 /* Wait for the engine to go idle */ 1006 RADEONWaitForFifoFunction(pScrn, 64); 1007 1008 for (;;) { 1009 for (i = 0; i < RADEON_TIMEOUT; i++) { 1010 if (!(INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)) { 1011 RADEONEngineFlush(pScrn); 1012 return; 1013 } 1014 } 1015 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 1016 "Idle timed out: %u entries, stat=0x%08x\n", 1017 (unsigned int)INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, 1018 (unsigned int)INREG(RADEON_RBBM_STATUS)); 1019 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1020 "Idle timed out, resetting engine...\n"); 1021 RADEONEngineReset(pScrn); 1022 RADEONEngineRestore(pScrn); 1023#ifdef XF86DRI 1024 if (info->directRenderingEnabled) { 1025 RADEONCP_RESET(pScrn, info); 1026 RADEONCP_START(pScrn, info); 1027 } 1028#endif 1029 } 1030 } 1031} 1032