radeon_crtc.c revision 2f39173d
1/* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining 8 * a copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation on the rights to use, copy, modify, merge, 11 * publish, distribute, sublicense, and/or sell copies of the Software, 12 * and to permit persons to whom the Software is furnished to do so, 13 * subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 */ 28 29#ifdef HAVE_CONFIG_H 30#include "config.h" 31#endif 32 33#include <string.h> 34#include <stdio.h> 35 36/* X and server generic header files */ 37#include "xf86.h" 38#include "xf86_OSproc.h" 39#include "vgaHW.h" 40#include "xf86Modes.h" 41 42/* Driver data structures */ 43#include "radeon.h" 44#include "radeon_reg.h" 45#include "radeon_macros.h" 46#include "radeon_probe.h" 47#include "radeon_version.h" 48 49#ifdef XF86DRI 50#define _XF86DRI_SERVER_ 51#include "radeon_drm.h" 52#include "sarea.h" 53#endif 54 55extern void atombios_crtc_mode_set(xf86CrtcPtr crtc, 56 DisplayModePtr mode, 57 DisplayModePtr adjusted_mode, 58 int x, int y); 59extern void atombios_crtc_dpms(xf86CrtcPtr crtc, int mode); 60extern void 61RADEONInitDispBandwidthLegacy(ScrnInfoPtr pScrn, 62 DisplayModePtr mode1, int pixel_bytes1, 63 DisplayModePtr mode2, int pixel_bytes2); 64extern void 65RADEONInitDispBandwidthAVIVO(ScrnInfoPtr pScrn, 66 DisplayModePtr mode1, int pixel_bytes1, 67 DisplayModePtr mode2, int pixel_bytes2); 68 69void 70radeon_crtc_dpms(xf86CrtcPtr crtc, int mode) 71{ 72 RADEONInfoPtr info = RADEONPTR(crtc->scrn); 73 RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn); 74 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 75 xf86CrtcPtr crtc0 = pRADEONEnt->pCrtc[0]; 76 77 if ((mode == DPMSModeOn) && radeon_crtc->enabled) 78 return; 79 80 if (mode == DPMSModeOff) 81 radeon_crtc_modeset_ioctl(crtc, FALSE); 82 83 if (IS_AVIVO_VARIANT || info->r4xx_atom) { 84 atombios_crtc_dpms(crtc, mode); 85 } else { 86 87 /* need to restore crtc1 before crtc0 or we may get a blank screen 88 * in some cases 89 */ 90 if ((radeon_crtc->crtc_id == 1) && (mode == DPMSModeOn)) { 91 if (crtc0->enabled) 92 legacy_crtc_dpms(crtc0, DPMSModeOff); 93 } 94 95 legacy_crtc_dpms(crtc, mode); 96 97 if ((radeon_crtc->crtc_id == 1) && (mode == DPMSModeOn)) { 98 if (crtc0->enabled) 99 legacy_crtc_dpms(crtc0, mode); 100 } 101 } 102 103 if (mode != DPMSModeOff) { 104 radeon_crtc_modeset_ioctl(crtc, TRUE); 105 radeon_crtc_load_lut(crtc); 106 } 107 108 if (mode == DPMSModeOn) 109 radeon_crtc->enabled = TRUE; 110 else 111 radeon_crtc->enabled = FALSE; 112} 113 114static Bool 115radeon_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode, 116 DisplayModePtr adjusted_mode) 117{ 118 return TRUE; 119} 120 121static void 122radeon_crtc_mode_prepare(xf86CrtcPtr crtc) 123{ 124 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 125 126 if (radeon_crtc->enabled) 127 crtc->funcs->hide_cursor(crtc); 128} 129 130static uint32_t RADEONDiv(CARD64 n, uint32_t d) 131{ 132 return (n + (d / 2)) / d; 133} 134 135static void 136RADEONComputePLL_old(RADEONPLLPtr pll, 137 unsigned long freq, 138 uint32_t *chosen_dot_clock_freq, 139 uint32_t *chosen_feedback_div, 140 uint32_t *chosen_frac_feedback_div, 141 uint32_t *chosen_reference_div, 142 uint32_t *chosen_post_div, 143 int flags) 144{ 145 uint32_t min_ref_div = pll->min_ref_div; 146 uint32_t max_ref_div = pll->max_ref_div; 147 uint32_t min_post_div = pll->min_post_div; 148 uint32_t max_post_div = pll->max_post_div; 149 uint32_t min_fractional_feed_div = 0; 150 uint32_t max_fractional_feed_div = 0; 151 uint32_t best_vco = pll->best_vco; 152 uint32_t best_post_div = 1; 153 uint32_t best_ref_div = 1; 154 uint32_t best_feedback_div = 1; 155 uint32_t best_frac_feedback_div = 0; 156 uint32_t best_freq = -1; 157 uint32_t best_error = 0xffffffff; 158 uint32_t best_vco_diff = 1; 159 uint32_t post_div; 160 161 freq = freq * 1000; 162 163 ErrorF("freq: %lu\n", freq); 164 165 if (flags & RADEON_PLL_USE_REF_DIV) 166 min_ref_div = max_ref_div = pll->reference_div; 167 else { 168 while (min_ref_div < max_ref_div-1) { 169 uint32_t mid=(min_ref_div+max_ref_div)/2; 170 uint32_t pll_in = pll->reference_freq / mid; 171 if (pll_in < pll->pll_in_min) 172 max_ref_div = mid; 173 else if (pll_in > pll->pll_in_max) 174 min_ref_div = mid; 175 else break; 176 } 177 } 178 179 if (flags & RADEON_PLL_USE_POST_DIV) 180 min_post_div = max_post_div = pll->post_div; 181 182 if (flags & RADEON_PLL_USE_FRAC_FB_DIV) { 183 min_fractional_feed_div = pll->min_frac_feedback_div; 184 max_fractional_feed_div = pll->max_frac_feedback_div; 185 } 186 187 for (post_div = min_post_div; post_div <= max_post_div; ++post_div) { 188 uint32_t ref_div; 189 190 if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 191 continue; 192 193 /* legacy radeons only have a few post_divs */ 194 if (flags & RADEON_PLL_LEGACY) { 195 if ((post_div == 5) || 196 (post_div == 7) || 197 (post_div == 9) || 198 (post_div == 10) || 199 (post_div == 11)) 200 continue; 201 } 202 203 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { 204 uint32_t feedback_div, current_freq = 0, error, vco_diff; 205 uint32_t pll_in = pll->reference_freq / ref_div; 206 uint32_t min_feed_div = pll->min_feedback_div; 207 uint32_t max_feed_div = pll->max_feedback_div+1; 208 209 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) 210 continue; 211 212 while (min_feed_div < max_feed_div) { 213 uint32_t vco; 214 uint32_t min_frac_feed_div = min_fractional_feed_div; 215 uint32_t max_frac_feed_div = max_fractional_feed_div+1; 216 uint32_t frac_feedback_div; 217 CARD64 tmp; 218 219 feedback_div = (min_feed_div+max_feed_div)/2; 220 221 tmp = (CARD64)pll->reference_freq * feedback_div; 222 vco = RADEONDiv(tmp, ref_div); 223 224 if (vco < pll->pll_out_min) { 225 min_feed_div = feedback_div+1; 226 continue; 227 } else if(vco > pll->pll_out_max) { 228 max_feed_div = feedback_div; 229 continue; 230 } 231 232 while (min_frac_feed_div < max_frac_feed_div) { 233 frac_feedback_div = (min_frac_feed_div+max_frac_feed_div)/2; 234 tmp = (CARD64)pll->reference_freq * 10000 * feedback_div; 235 tmp += (CARD64)pll->reference_freq * 1000 * frac_feedback_div; 236 current_freq = RADEONDiv(tmp, ref_div * post_div); 237 238 if (flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 239 error = freq - current_freq; 240 error = error < 0 ? 0xffffffff : error; 241 } else 242 error = abs(current_freq - freq); 243 vco_diff = abs(vco - best_vco); 244 245 if ((best_vco == 0 && error < best_error) || 246 (best_vco != 0 && 247 (error < best_error - 100 || 248 (abs(error - best_error) < 100 && vco_diff < best_vco_diff )))) { 249 best_post_div = post_div; 250 best_ref_div = ref_div; 251 best_feedback_div = feedback_div; 252 best_frac_feedback_div = frac_feedback_div; 253 best_freq = current_freq; 254 best_error = error; 255 best_vco_diff = vco_diff; 256 } else if (current_freq == freq) { 257 if (best_freq == -1) { 258 best_post_div = post_div; 259 best_ref_div = ref_div; 260 best_feedback_div = feedback_div; 261 best_frac_feedback_div = frac_feedback_div; 262 best_freq = current_freq; 263 best_error = error; 264 best_vco_diff = vco_diff; 265 } else if (((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 266 ((flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 267 ((flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 268 ((flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 269 ((flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 270 ((flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 271 best_post_div = post_div; 272 best_ref_div = ref_div; 273 best_feedback_div = feedback_div; 274 best_frac_feedback_div = frac_feedback_div; 275 best_freq = current_freq; 276 best_error = error; 277 best_vco_diff = vco_diff; 278 } 279 } 280 if (current_freq < freq) 281 min_frac_feed_div = frac_feedback_div+1; 282 else 283 max_frac_feed_div = frac_feedback_div; 284 } 285 if (current_freq < freq) 286 min_feed_div = feedback_div+1; 287 else 288 max_feed_div = feedback_div; 289 } 290 } 291 } 292 293 ErrorF("best_freq: %u\n", (unsigned int)best_freq); 294 ErrorF("best_feedback_div: %u\n", (unsigned int)best_feedback_div); 295 ErrorF("best_frac_feedback_div: %u\n", (unsigned int)best_frac_feedback_div); 296 ErrorF("best_ref_div: %u\n", (unsigned int)best_ref_div); 297 ErrorF("best_post_div: %u\n", (unsigned int)best_post_div); 298 299 if (best_freq == -1) 300 FatalError("Couldn't find valid PLL dividers\n"); 301 *chosen_dot_clock_freq = best_freq / 10000; 302 *chosen_feedback_div = best_feedback_div; 303 *chosen_frac_feedback_div = best_frac_feedback_div; 304 *chosen_reference_div = best_ref_div; 305 *chosen_post_div = best_post_div; 306 307} 308 309static Bool 310calc_fb_div(RADEONPLLPtr pll, 311 unsigned long freq, 312 int flags, 313 int post_div, 314 int ref_div, 315 int *fb_div, 316 int *fb_div_frac) 317{ 318 float ffreq = freq / 10; 319 float vco_freq = ffreq * post_div; 320 float feedback_divider = vco_freq * ref_div / pll->reference_freq; 321 322 if (flags & RADEON_PLL_USE_FRAC_FB_DIV) { 323 feedback_divider = floor((feedback_divider * 10.0) + 0.5) * 0.1; 324 325 *fb_div = floor(feedback_divider); 326 *fb_div_frac = fmod(feedback_divider, 1.0) * 10.0; 327 328 } else { 329 *fb_div = floor(feedback_divider + 0.5); 330 *fb_div_frac = 0; 331 } 332 if ((*fb_div < pll->min_feedback_div) || (*fb_div > pll->max_feedback_div)) 333 return FALSE; 334 else 335 return TRUE; 336} 337 338static Bool 339calc_fb_ref_div(RADEONPLLPtr pll, 340 unsigned long freq, 341 int flags, 342 int post_div, 343 int *fb_div, 344 int *fb_div_frac, 345 int *ref_div) 346{ 347 float ffreq = freq / 10; 348 float max_error = ffreq * 0.0025; 349 float vco, error, pll_out; 350 351 for ((*ref_div) = pll->min_ref_div; (*ref_div) < pll->max_ref_div; ++(*ref_div)) { 352 if (calc_fb_div(pll, freq, flags, post_div, (*ref_div), fb_div, fb_div_frac)) { 353 vco = pll->reference_freq * ((*fb_div) + ((*fb_div_frac) * 0.1)) / (*ref_div); 354 355 if ((vco < pll->pll_out_min) || (vco > pll->pll_out_max)) 356 continue; 357 358 pll_out = vco / post_div; 359 360 error = pll_out - ffreq; 361 if ((fabs(error) <= max_error) && (error >= 0)) 362 return TRUE; 363 } 364 } 365 return FALSE; 366} 367 368static void 369RADEONComputePLL_new(RADEONPLLPtr pll, 370 unsigned long freq, 371 uint32_t *chosen_dot_clock_freq, 372 uint32_t *chosen_feedback_div, 373 uint32_t *chosen_frac_feedback_div, 374 uint32_t *chosen_reference_div, 375 uint32_t *chosen_post_div, 376 int flags) 377{ 378 float ffreq = freq / 10; 379 float vco_frequency; 380 int fb_div = 0, fb_div_frac = 0, post_div = 0, ref_div = 0; 381 uint32_t best_freq = 0; 382 383 if (flags & RADEON_PLL_USE_POST_DIV) { 384 post_div = pll->post_div; 385 if ((post_div < pll->min_post_div) || (post_div > pll->max_post_div)) 386 goto done; 387 vco_frequency = ffreq * post_div; 388 if ((vco_frequency < pll->pll_out_min) || (vco_frequency > pll->pll_out_max)) 389 goto done; 390 391 if (flags & RADEON_PLL_USE_REF_DIV) { 392 ref_div = pll->reference_div; 393 if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div)) 394 goto done; 395 if (!calc_fb_div(pll, freq, flags, post_div, ref_div, &fb_div, &fb_div_frac)) 396 goto done; 397 } 398 } else { 399 for (post_div = pll->max_post_div; post_div >= pll->min_post_div; --post_div) { 400 if (flags & RADEON_PLL_LEGACY) { 401 if ((post_div == 5) || 402 (post_div == 7) || 403 (post_div == 9) || 404 (post_div == 10) || 405 (post_div == 11)) 406 continue; 407 } 408 if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 409 continue; 410 411 vco_frequency = ffreq * post_div; 412 if ((vco_frequency < pll->pll_out_min) || (vco_frequency > pll->pll_out_max)) 413 continue; 414 if (flags & RADEON_PLL_USE_REF_DIV) { 415 ref_div = pll->reference_div; 416 if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div)) 417 goto done; 418 if (calc_fb_div(pll, freq, flags, post_div, ref_div, &fb_div, &fb_div_frac)) 419 break; 420 } else { 421 if (calc_fb_ref_div(pll, freq, flags, post_div, &fb_div, &fb_div_frac, &ref_div)) 422 break; 423 } 424 } 425 } 426 427 best_freq = pll->reference_freq * 10 * fb_div; 428 best_freq += pll->reference_freq * fb_div_frac; 429 best_freq = best_freq / (ref_div * post_div); 430 431 ErrorF("best_freq: %u\n", (unsigned int)best_freq); 432 ErrorF("best_feedback_div: %u\n", (unsigned int)fb_div); 433 ErrorF("best_frac_feedback_div: %u\n", (unsigned int)fb_div_frac); 434 ErrorF("best_ref_div: %u\n", (unsigned int)ref_div); 435 ErrorF("best_post_div: %u\n", (unsigned int)post_div); 436 437done: 438 if (best_freq == 0) 439 FatalError("Couldn't find valid PLL dividers\n"); 440 441 *chosen_dot_clock_freq = best_freq; 442 *chosen_feedback_div = fb_div; 443 *chosen_frac_feedback_div = fb_div_frac; 444 *chosen_reference_div = ref_div; 445 *chosen_post_div = post_div; 446 447} 448 449void 450RADEONComputePLL(xf86CrtcPtr crtc, 451 RADEONPLLPtr pll, 452 unsigned long freq, 453 uint32_t *chosen_dot_clock_freq, 454 uint32_t *chosen_feedback_div, 455 uint32_t *chosen_frac_feedback_div, 456 uint32_t *chosen_reference_div, 457 uint32_t *chosen_post_div, 458 int flags) 459{ 460 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 461 462 switch (radeon_crtc->pll_algo) { 463 case RADEON_PLL_OLD: 464 RADEONComputePLL_old(pll, freq, chosen_dot_clock_freq, 465 chosen_feedback_div, chosen_frac_feedback_div, 466 chosen_reference_div, chosen_post_div, flags); 467 break; 468 case RADEON_PLL_NEW: 469 /* disable frac fb dividers */ 470 flags &= ~RADEON_PLL_USE_FRAC_FB_DIV; 471 RADEONComputePLL_new(pll, freq, chosen_dot_clock_freq, 472 chosen_feedback_div, chosen_frac_feedback_div, 473 chosen_reference_div, chosen_post_div, flags); 474 break; 475 } 476} 477 478static void 479radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, 480 DisplayModePtr adjusted_mode, int x, int y) 481{ 482 ScrnInfoPtr pScrn = crtc->scrn; 483 RADEONInfoPtr info = RADEONPTR(pScrn); 484 485 if (IS_AVIVO_VARIANT || info->r4xx_atom) { 486 atombios_crtc_mode_set(crtc, mode, adjusted_mode, x, y); 487 } else { 488 legacy_crtc_mode_set(crtc, mode, adjusted_mode, x, y); 489 } 490} 491 492static void 493radeon_crtc_mode_commit(xf86CrtcPtr crtc) 494{ 495 if (crtc->scrn->pScreen != NULL) 496 xf86_reload_cursors(crtc->scrn->pScreen); 497} 498 499void 500radeon_crtc_load_lut(xf86CrtcPtr crtc) 501{ 502 ScrnInfoPtr pScrn = crtc->scrn; 503 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 504 RADEONInfoPtr info = RADEONPTR(pScrn); 505 unsigned char *RADEONMMIO = info->MMIO; 506 int i; 507 508 if (!crtc->enabled) 509 return; 510 511 if (IS_DCE4_VARIANT) { 512 OUTREG(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 513 514 OUTREG(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 515 OUTREG(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 516 OUTREG(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 517 518 OUTREG(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0x0000ffff); 519 OUTREG(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0x0000ffff); 520 OUTREG(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0x0000ffff); 521 522 OUTREG(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 523 OUTREG(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 524 525 for (i = 0; i < 256; i++) { 526 OUTREG(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, i); 527 OUTREG(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 528 (((radeon_crtc->lut_r[i]) << 20) | 529 ((radeon_crtc->lut_g[i]) << 10) | 530 (radeon_crtc->lut_b[i]))); 531 } 532 } else { 533 if (IS_AVIVO_VARIANT) { 534 OUTREG(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); 535 536 OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 537 OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 538 OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 539 540 OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0x0000ffff); 541 OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0x0000ffff); 542 OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0x0000ffff); 543 } 544 545 PAL_SELECT(radeon_crtc->crtc_id); 546 547 if (IS_AVIVO_VARIANT) { 548 OUTREG(AVIVO_DC_LUT_RW_MODE, 0); 549 OUTREG(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); 550 } 551 552 for (i = 0; i < 256; i++) { 553 OUTPAL(i, radeon_crtc->lut_r[i], radeon_crtc->lut_g[i], radeon_crtc->lut_b[i]); 554 } 555 556 if (IS_AVIVO_VARIANT) 557 OUTREG(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); 558 } 559 560} 561 562static void 563radeon_crtc_gamma_set(xf86CrtcPtr crtc, uint16_t *red, uint16_t *green, 564 uint16_t *blue, int size) 565{ 566 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 567 int i; 568 569 for (i = 0; i < 256; i++) { 570 radeon_crtc->lut_r[i] = red[i] >> 6; 571 radeon_crtc->lut_g[i] = green[i] >> 6; 572 radeon_crtc->lut_b[i] = blue[i] >> 6; 573 } 574 575 radeon_crtc_load_lut(crtc); 576} 577 578static Bool 579radeon_crtc_lock(xf86CrtcPtr crtc) 580{ 581 ScrnInfoPtr pScrn = crtc->scrn; 582 RADEONInfoPtr info = RADEONPTR(pScrn); 583 584#ifdef XF86DRI 585 if (info->cp->CPStarted && pScrn->pScreen) { 586 DRILock(pScrn->pScreen, 0); 587 if (info->accelOn) 588 RADEON_SYNC(info, pScrn); 589 return TRUE; 590 } 591#endif 592 if (info->accelOn) 593 RADEON_SYNC(info, pScrn); 594 595 return FALSE; 596 597} 598 599static void 600radeon_crtc_unlock(xf86CrtcPtr crtc) 601{ 602 ScrnInfoPtr pScrn = crtc->scrn; 603 RADEONInfoPtr info = RADEONPTR(pScrn); 604 605#ifdef XF86DRI 606 if (info->cp->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen); 607#endif 608 609 if (info->accelOn) 610 RADEON_SYNC(info, pScrn); 611} 612 613/** 614 * Allocates memory for a locked-in-framebuffer shadow of the given 615 * width and height for this CRTC's rotated shadow framebuffer. 616 */ 617 618static void * 619radeon_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height) 620{ 621 ScrnInfoPtr pScrn = crtc->scrn; 622 RADEONInfoPtr info = RADEONPTR(pScrn); 623 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 624 unsigned long rotate_pitch; 625 unsigned long rotate_offset; 626 int size; 627 int cpp = pScrn->bitsPerPixel / 8; 628 629 /* No rotation without accel */ 630 if (((info->ChipFamily >= CHIP_FAMILY_R600) && !info->directRenderingEnabled) || 631 xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { 632 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 633 "Acceleration required for rotation\n"); 634 return NULL; 635 } 636 637 rotate_pitch = pScrn->displayWidth * cpp; 638 size = rotate_pitch * height; 639 640 /* We could get close to what we want here by just creating a pixmap like 641 * normal, but we have to lock it down in framebuffer, and there is no 642 * setter for offscreen area locking in EXA currently. So, we just 643 * allocate offscreen memory and fake up a pixmap header for it. 644 */ 645 rotate_offset = radeon_legacy_allocate_memory(pScrn, &radeon_crtc->crtc_rotate_mem, 646 size, RADEON_GPU_PAGE_SIZE, RADEON_GEM_DOMAIN_VRAM); 647 if (rotate_offset == 0) 648 return NULL; 649 650 return info->FB + rotate_offset; 651} 652 653/** 654 * Creates a pixmap for this CRTC's rotated shadow framebuffer. 655 */ 656static PixmapPtr 657radeon_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height) 658{ 659 ScrnInfoPtr pScrn = crtc->scrn; 660 unsigned long rotate_pitch; 661 PixmapPtr rotate_pixmap; 662 int cpp = pScrn->bitsPerPixel / 8; 663 664 if (!data) 665 data = radeon_crtc_shadow_allocate(crtc, width, height); 666 667 rotate_pitch = pScrn->displayWidth * cpp; 668 669 rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen, 670 width, height, 671 pScrn->depth, 672 pScrn->bitsPerPixel, 673 rotate_pitch, 674 data); 675 676 if (rotate_pixmap == NULL) { 677 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 678 "Couldn't allocate shadow pixmap for rotated CRTC\n"); 679 } 680 681 return rotate_pixmap; 682} 683 684static void 685radeon_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data) 686{ 687 ScrnInfoPtr pScrn = crtc->scrn; 688 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 689 690 if (rotate_pixmap) 691 FreeScratchPixmapHeader(rotate_pixmap); 692 693 if (data) { 694 radeon_legacy_free_memory(pScrn, radeon_crtc->crtc_rotate_mem); 695 radeon_crtc->crtc_rotate_mem = NULL; 696 } 697 698} 699 700#if XF86_CRTC_VERSION >= 2 701#include "radeon_atombios.h" 702 703extern AtomBiosResult 704atombios_lock_crtc(atomBiosHandlePtr atomBIOS, int crtc, int lock); 705extern void 706RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save, 707 int x, int y); 708extern void 709RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save, 710 int x, int y); 711extern void 712RADEONRestoreCrtcBase(ScrnInfoPtr pScrn, 713 RADEONSavePtr restore); 714extern void 715RADEONRestoreCrtc2Base(ScrnInfoPtr pScrn, 716 RADEONSavePtr restore); 717 718static void 719radeon_crtc_set_origin(xf86CrtcPtr crtc, int x, int y) 720{ 721 ScrnInfoPtr pScrn = crtc->scrn; 722 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 723 RADEONInfoPtr info = RADEONPTR(pScrn); 724 unsigned char *RADEONMMIO = info->MMIO; 725 726 727 if (IS_DCE4_VARIANT) { 728 x &= ~3; 729 y &= ~1; 730 atombios_lock_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1); 731 OUTREG(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y); 732 atombios_lock_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0); 733 } else if (IS_AVIVO_VARIANT) { 734 x &= ~3; 735 y &= ~1; 736 atombios_lock_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1); 737 OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y); 738 atombios_lock_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0); 739 } else { 740 switch (radeon_crtc->crtc_id) { 741 case 0: 742 RADEONInitCrtcBase(crtc, info->ModeReg, x, y); 743 RADEONRestoreCrtcBase(pScrn, info->ModeReg); 744 break; 745 case 1: 746 RADEONInitCrtc2Base(crtc, info->ModeReg, x, y); 747 RADEONRestoreCrtc2Base(pScrn, info->ModeReg); 748 break; 749 default: 750 break; 751 } 752 } 753} 754#endif 755 756 757static xf86CrtcFuncsRec radeon_crtc_funcs = { 758 .dpms = radeon_crtc_dpms, 759 .save = NULL, /* XXX */ 760 .restore = NULL, /* XXX */ 761 .mode_fixup = radeon_crtc_mode_fixup, 762 .prepare = radeon_crtc_mode_prepare, 763 .mode_set = radeon_crtc_mode_set, 764 .commit = radeon_crtc_mode_commit, 765 .gamma_set = radeon_crtc_gamma_set, 766 .lock = radeon_crtc_lock, 767 .unlock = radeon_crtc_unlock, 768 .shadow_create = radeon_crtc_shadow_create, 769 .shadow_allocate = radeon_crtc_shadow_allocate, 770 .shadow_destroy = radeon_crtc_shadow_destroy, 771 .set_cursor_colors = radeon_crtc_set_cursor_colors, 772 .set_cursor_position = radeon_crtc_set_cursor_position, 773 .show_cursor = radeon_crtc_show_cursor, 774 .hide_cursor = radeon_crtc_hide_cursor, 775 .load_cursor_argb = radeon_crtc_load_cursor_argb, 776 .destroy = NULL, /* XXX */ 777#if XF86_CRTC_VERSION >= 2 778 .set_origin = radeon_crtc_set_origin, 779#endif 780}; 781 782void 783RADEONInitDispBandwidth(ScrnInfoPtr pScrn) 784{ 785 RADEONInfoPtr info = RADEONPTR(pScrn); 786 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 787 DisplayModePtr mode1 = NULL, mode2 = NULL; 788 int pixel_bytes1 = info->CurrentLayout.pixel_bytes; 789 int pixel_bytes2 = info->CurrentLayout.pixel_bytes; 790 791 /* XXX fix me */ 792 if (IS_DCE4_VARIANT) 793 return; 794 795 if (xf86_config->num_crtc == 2) { 796 if (xf86_config->crtc[1]->enabled && 797 xf86_config->crtc[0]->enabled) { 798 mode1 = &xf86_config->crtc[0]->mode; 799 mode2 = &xf86_config->crtc[1]->mode; 800 } else if (xf86_config->crtc[0]->enabled) { 801 mode1 = &xf86_config->crtc[0]->mode; 802 } else if (xf86_config->crtc[1]->enabled) { 803 mode2 = &xf86_config->crtc[1]->mode; 804 } else 805 return; 806 } else { 807 if (info->IsPrimary) 808 mode1 = &xf86_config->crtc[0]->mode; 809 else if (info->IsSecondary) 810 mode2 = &xf86_config->crtc[0]->mode; 811 else if (xf86_config->crtc[0]->enabled) 812 mode1 = &xf86_config->crtc[0]->mode; 813 else 814 return; 815 } 816 817 if (IS_AVIVO_VARIANT) 818 RADEONInitDispBandwidthAVIVO(pScrn, mode1, pixel_bytes1, mode2, pixel_bytes2); 819 else 820 RADEONInitDispBandwidthLegacy(pScrn, mode1, pixel_bytes1, mode2, pixel_bytes2); 821} 822 823Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask) 824{ 825 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 826 RADEONInfoPtr info = RADEONPTR(pScrn); 827 int i; 828 829 if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { 830 radeon_crtc_funcs.shadow_create = radeon_crtc_shadow_create; 831 radeon_crtc_funcs.shadow_allocate = radeon_crtc_shadow_allocate; 832 radeon_crtc_funcs.shadow_destroy = radeon_crtc_shadow_destroy; 833 } 834 835 if (mask & 1) { 836 if (pRADEONEnt->Controller[0]) 837 return TRUE; 838 839 pRADEONEnt->pCrtc[0] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs); 840 if (!pRADEONEnt->pCrtc[0]) 841 return FALSE; 842 843 pRADEONEnt->Controller[0] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1); 844 if (!pRADEONEnt->Controller[0]) 845 return FALSE; 846 847 pRADEONEnt->pCrtc[0]->driver_private = pRADEONEnt->Controller[0]; 848 pRADEONEnt->Controller[0]->crtc_id = 0; 849 pRADEONEnt->Controller[0]->crtc_offset = 0; 850 pRADEONEnt->Controller[0]->initialized = FALSE; 851 if (info->allowColorTiling) 852 pRADEONEnt->Controller[0]->can_tile = 1; 853 else 854 pRADEONEnt->Controller[0]->can_tile = 0; 855 pRADEONEnt->Controller[0]->pll_id = -1; 856 } 857 858 if (mask & 2) { 859 if (!pRADEONEnt->HasCRTC2) 860 return TRUE; 861 862 pRADEONEnt->pCrtc[1] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs); 863 if (!pRADEONEnt->pCrtc[1]) 864 return FALSE; 865 866 pRADEONEnt->Controller[1] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1); 867 if (!pRADEONEnt->Controller[1]) 868 { 869 free(pRADEONEnt->Controller[0]); 870 return FALSE; 871 } 872 873 pRADEONEnt->pCrtc[1]->driver_private = pRADEONEnt->Controller[1]; 874 pRADEONEnt->Controller[1]->crtc_id = 1; 875 if (IS_DCE4_VARIANT) 876 pRADEONEnt->Controller[1]->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; 877 else 878 pRADEONEnt->Controller[1]->crtc_offset = AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; 879 pRADEONEnt->Controller[1]->initialized = FALSE; 880 if (info->allowColorTiling) 881 pRADEONEnt->Controller[1]->can_tile = 1; 882 else 883 pRADEONEnt->Controller[1]->can_tile = 0; 884 pRADEONEnt->Controller[1]->pll_id = -1; 885 } 886 887 /* 6 crtcs on DCE4 chips */ 888 if (IS_DCE4_VARIANT && ((mask & 3) == 3)) { 889 for (i = 2; i < RADEON_MAX_CRTC; i++) { 890 pRADEONEnt->pCrtc[i] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs); 891 if (!pRADEONEnt->pCrtc[i]) 892 return FALSE; 893 894 pRADEONEnt->Controller[i] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1); 895 if (!pRADEONEnt->Controller[i]) 896 { 897 free(pRADEONEnt->Controller[i]); 898 return FALSE; 899 } 900 901 pRADEONEnt->pCrtc[i]->driver_private = pRADEONEnt->Controller[i]; 902 pRADEONEnt->Controller[i]->crtc_id = i; 903 switch (i) { 904 case 0: 905 pRADEONEnt->Controller[i]->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; 906 break; 907 case 1: 908 pRADEONEnt->Controller[i]->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; 909 break; 910 case 2: 911 pRADEONEnt->Controller[i]->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; 912 break; 913 case 3: 914 pRADEONEnt->Controller[i]->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; 915 break; 916 case 4: 917 pRADEONEnt->Controller[i]->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; 918 break; 919 case 5: 920 pRADEONEnt->Controller[i]->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; 921 break; 922 } 923 pRADEONEnt->Controller[i]->initialized = FALSE; 924 if (info->allowColorTiling) 925 pRADEONEnt->Controller[i]->can_tile = 1; 926 else 927 pRADEONEnt->Controller[i]->can_tile = 0; 928 pRADEONEnt->Controller[i]->pll_id = -1; 929 } 930 } 931 932 return TRUE; 933} 934 935/** 936 * In the current world order, there are lists of modes per output, which may 937 * or may not include the mode that was asked to be set by XFree86's mode 938 * selection. Find the closest one, in the following preference order: 939 * 940 * - Equality 941 * - Closer in size to the requested mode, but no larger 942 * - Closer in refresh rate to the requested mode. 943 */ 944DisplayModePtr 945RADEONCrtcFindClosestMode(xf86CrtcPtr crtc, DisplayModePtr pMode) 946{ 947 ScrnInfoPtr pScrn = crtc->scrn; 948 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 949 DisplayModePtr pBest = NULL, pScan = NULL; 950 int i; 951 952 /* Assume that there's only one output connected to the given CRTC. */ 953 for (i = 0; i < xf86_config->num_output; i++) 954 { 955 xf86OutputPtr output = xf86_config->output[i]; 956 if (output->crtc == crtc && output->probed_modes != NULL) 957 { 958 pScan = output->probed_modes; 959 break; 960 } 961 } 962 963 /* If the pipe doesn't have any detected modes, just let the system try to 964 * spam the desired mode in. 965 */ 966 if (pScan == NULL) { 967 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 968 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 969 "No crtc mode list for crtc %d," 970 "continuing with desired mode\n", radeon_crtc->crtc_id); 971 return pMode; 972 } 973 974 for (; pScan != NULL; pScan = pScan->next) { 975 assert(pScan->VRefresh != 0.0); 976 977 /* If there's an exact match, we're done. */ 978 if (xf86ModesEqual(pScan, pMode)) { 979 pBest = pMode; 980 break; 981 } 982 983 /* Reject if it's larger than the desired mode. */ 984 if (pScan->HDisplay > pMode->HDisplay || 985 pScan->VDisplay > pMode->VDisplay) 986 { 987 continue; 988 } 989 990 if (pBest == NULL) { 991 pBest = pScan; 992 continue; 993 } 994 995 /* Find if it's closer to the right size than the current best 996 * option. 997 */ 998 if ((pScan->HDisplay > pBest->HDisplay && 999 pScan->VDisplay >= pBest->VDisplay) || 1000 (pScan->HDisplay >= pBest->HDisplay && 1001 pScan->VDisplay > pBest->VDisplay)) 1002 { 1003 pBest = pScan; 1004 continue; 1005 } 1006 1007 /* Find if it's still closer to the right refresh than the current 1008 * best resolution. 1009 */ 1010 if (pScan->HDisplay == pBest->HDisplay && 1011 pScan->VDisplay == pBest->VDisplay && 1012 (fabs(pScan->VRefresh - pMode->VRefresh) < 1013 fabs(pBest->VRefresh - pMode->VRefresh))) { 1014 pBest = pScan; 1015 } 1016 } 1017 1018 if (pBest == NULL) { 1019 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1020 "No suitable mode found to program for the pipe.\n" 1021 " continuing with desired mode %dx%d@%.1f\n", 1022 pMode->HDisplay, pMode->VDisplay, pMode->VRefresh); 1023 } else if (!xf86ModesEqual(pBest, pMode)) { 1024 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 1025 int crtc = radeon_crtc->crtc_id; 1026 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1027 "Choosing pipe %d's mode %dx%d@%.1f instead of xf86 " 1028 "mode %dx%d@%.1f\n", crtc, 1029 pBest->HDisplay, pBest->VDisplay, pBest->VRefresh, 1030 pMode->HDisplay, pMode->VDisplay, pMode->VRefresh); 1031 pMode = pBest; 1032 } 1033 return pMode; 1034} 1035 1036void 1037RADEONBlank(ScrnInfoPtr pScrn) 1038{ 1039 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 1040 xf86OutputPtr output; 1041 xf86CrtcPtr crtc; 1042 int o, c; 1043 1044 for (c = 0; c < xf86_config->num_crtc; c++) { 1045 crtc = xf86_config->crtc[c]; 1046 for (o = 0; o < xf86_config->num_output; o++) { 1047 output = xf86_config->output[o]; 1048 if (output->crtc != crtc) 1049 continue; 1050 1051 output->funcs->dpms(output, DPMSModeOff); 1052 } 1053 crtc->funcs->dpms(crtc, DPMSModeOff); 1054 } 1055} 1056 1057void 1058RADEONUnblank(ScrnInfoPtr pScrn) 1059{ 1060 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 1061 xf86OutputPtr output; 1062 xf86CrtcPtr crtc; 1063 int o, c; 1064 1065 for (c = 0; c < xf86_config->num_crtc; c++) { 1066 crtc = xf86_config->crtc[c]; 1067 if(!crtc->enabled) 1068 continue; 1069 crtc->funcs->dpms(crtc, DPMSModeOn); 1070 for (o = 0; o < xf86_config->num_output; o++) { 1071 output = xf86_config->output[o]; 1072 if (output->crtc != crtc) 1073 continue; 1074 1075 output->funcs->dpms(output, DPMSModeOn); 1076 } 1077 } 1078} 1079 1080Bool 1081RADEONSetTiling(ScrnInfoPtr pScrn) 1082{ 1083 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 1084 RADEONInfoPtr info = RADEONPTR(pScrn); 1085 RADEONCrtcPrivatePtr radeon_crtc; 1086 xf86CrtcPtr crtc; 1087 int c; 1088 int can_tile = 1; 1089 Bool changed = FALSE; 1090 1091 for (c = 0; c < xf86_config->num_crtc; c++) { 1092 crtc = xf86_config->crtc[c]; 1093 radeon_crtc = crtc->driver_private; 1094 1095 if (crtc->enabled) { 1096 if (!radeon_crtc->can_tile) 1097 can_tile = 0; 1098 } 1099 } 1100 1101 if (info->tilingEnabled != can_tile) 1102 changed = TRUE; 1103 1104#ifdef XF86DRI 1105 if (info->directRenderingEnabled && (info->tilingEnabled != can_tile)) { 1106 drm_radeon_sarea_t *pSAREAPriv; 1107 if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (can_tile ? 1 : 0)) < 0) 1108 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1109 "[drm] failed changing tiling status\n"); 1110 /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */ 1111 pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]); 1112 info->tilingEnabled = pSAREAPriv->tiling_enabled ? TRUE : FALSE; 1113 } 1114#endif 1115 1116 return changed; 1117} 1118