radeon_crtc.c revision c4ae5be6
1/* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining 8 * a copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation on the rights to use, copy, modify, merge, 11 * publish, distribute, sublicense, and/or sell copies of the Software, 12 * and to permit persons to whom the Software is furnished to do so, 13 * subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 */ 28 29#ifdef HAVE_CONFIG_H 30#include "config.h" 31#endif 32 33#include <string.h> 34#include <stdio.h> 35#include <assert.h> 36#include <math.h> 37 38/* X and server generic header files */ 39#include "xf86.h" 40#include "xf86_OSproc.h" 41#include "vgaHW.h" 42#include "xf86Modes.h" 43 44/* Driver data structures */ 45#include "radeon.h" 46#include "radeon_reg.h" 47#include "radeon_macros.h" 48#include "radeon_probe.h" 49#include "radeon_version.h" 50 51#ifdef XF86DRI 52#define _XF86DRI_SERVER_ 53#include "radeon_drm.h" 54#include "sarea.h" 55#endif 56 57extern void atombios_crtc_mode_set(xf86CrtcPtr crtc, 58 DisplayModePtr mode, 59 DisplayModePtr adjusted_mode, 60 int x, int y); 61extern void atombios_crtc_dpms(xf86CrtcPtr crtc, int mode); 62extern void 63RADEONInitDispBandwidthLegacy(ScrnInfoPtr pScrn, 64 DisplayModePtr mode1, int pixel_bytes1, 65 DisplayModePtr mode2, int pixel_bytes2); 66extern void 67RADEONInitDispBandwidthAVIVO(ScrnInfoPtr pScrn, 68 DisplayModePtr mode1, int pixel_bytes1, 69 DisplayModePtr mode2, int pixel_bytes2); 70 71void 72radeon_crtc_dpms(xf86CrtcPtr crtc, int mode) 73{ 74 RADEONInfoPtr info = RADEONPTR(crtc->scrn); 75 RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn); 76 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 77 xf86CrtcPtr crtc0 = pRADEONEnt->pCrtc[0]; 78 79 if ((mode == DPMSModeOn) && radeon_crtc->enabled) 80 return; 81 82 if (mode == DPMSModeOff) 83 radeon_crtc_modeset_ioctl(crtc, FALSE); 84 85 if (IS_AVIVO_VARIANT || info->r4xx_atom) { 86 atombios_crtc_dpms(crtc, mode); 87 } else { 88 89 /* need to restore crtc1 before crtc0 or we may get a blank screen 90 * in some cases 91 */ 92 if ((radeon_crtc->crtc_id == 1) && (mode == DPMSModeOn)) { 93 if (crtc0->enabled) 94 legacy_crtc_dpms(crtc0, DPMSModeOff); 95 } 96 97 legacy_crtc_dpms(crtc, mode); 98 99 if ((radeon_crtc->crtc_id == 1) && (mode == DPMSModeOn)) { 100 if (crtc0->enabled) 101 legacy_crtc_dpms(crtc0, mode); 102 } 103 } 104 105 if (mode != DPMSModeOff) { 106 radeon_crtc_modeset_ioctl(crtc, TRUE); 107 radeon_crtc_load_lut(crtc); 108 } 109 110 if (mode == DPMSModeOn) 111 radeon_crtc->enabled = TRUE; 112 else 113 radeon_crtc->enabled = FALSE; 114} 115 116static Bool 117radeon_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode, 118 DisplayModePtr adjusted_mode) 119{ 120 return TRUE; 121} 122 123static void 124radeon_crtc_mode_prepare(xf86CrtcPtr crtc) 125{ 126 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 127 128 if (radeon_crtc->enabled) 129 crtc->funcs->hide_cursor(crtc); 130} 131 132static uint32_t RADEONDiv(CARD64 n, uint32_t d) 133{ 134 return (n + (d / 2)) / d; 135} 136 137static void 138RADEONComputePLL_old(RADEONPLLPtr pll, 139 unsigned long freq, 140 uint32_t *chosen_dot_clock_freq, 141 uint32_t *chosen_feedback_div, 142 uint32_t *chosen_frac_feedback_div, 143 uint32_t *chosen_reference_div, 144 uint32_t *chosen_post_div, 145 int flags) 146{ 147 uint32_t min_ref_div = pll->min_ref_div; 148 uint32_t max_ref_div = pll->max_ref_div; 149 uint32_t min_post_div = pll->min_post_div; 150 uint32_t max_post_div = pll->max_post_div; 151 uint32_t min_fractional_feed_div = 0; 152 uint32_t max_fractional_feed_div = 0; 153 uint32_t best_vco = pll->best_vco; 154 uint32_t best_post_div = 1; 155 uint32_t best_ref_div = 1; 156 uint32_t best_feedback_div = 1; 157 uint32_t best_frac_feedback_div = 0; 158 uint32_t best_freq = -1; 159 uint32_t best_error = 0xffffffff; 160 uint32_t best_vco_diff = 1; 161 uint32_t post_div; 162 163 freq = freq * 1000; 164 165 ErrorF("freq: %lu\n", freq); 166 167 if (flags & RADEON_PLL_USE_REF_DIV) 168 min_ref_div = max_ref_div = pll->reference_div; 169 else { 170 while (min_ref_div < max_ref_div-1) { 171 uint32_t mid=(min_ref_div+max_ref_div)/2; 172 uint32_t pll_in = pll->reference_freq / mid; 173 if (pll_in < pll->pll_in_min) 174 max_ref_div = mid; 175 else if (pll_in > pll->pll_in_max) 176 min_ref_div = mid; 177 else break; 178 } 179 } 180 181 if (flags & RADEON_PLL_USE_POST_DIV) 182 min_post_div = max_post_div = pll->post_div; 183 184 if (flags & RADEON_PLL_USE_FRAC_FB_DIV) { 185 min_fractional_feed_div = pll->min_frac_feedback_div; 186 max_fractional_feed_div = pll->max_frac_feedback_div; 187 } 188 189 for (post_div = min_post_div; post_div <= max_post_div; ++post_div) { 190 uint32_t ref_div; 191 192 if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 193 continue; 194 195 /* legacy radeons only have a few post_divs */ 196 if (flags & RADEON_PLL_LEGACY) { 197 if ((post_div == 5) || 198 (post_div == 7) || 199 (post_div == 9) || 200 (post_div == 10) || 201 (post_div == 11)) 202 continue; 203 } 204 205 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { 206 uint32_t feedback_div, current_freq = 0, error, vco_diff; 207 uint32_t pll_in = pll->reference_freq / ref_div; 208 uint32_t min_feed_div = pll->min_feedback_div; 209 uint32_t max_feed_div = pll->max_feedback_div+1; 210 211 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) 212 continue; 213 214 while (min_feed_div < max_feed_div) { 215 uint32_t vco; 216 uint32_t min_frac_feed_div = min_fractional_feed_div; 217 uint32_t max_frac_feed_div = max_fractional_feed_div+1; 218 uint32_t frac_feedback_div; 219 CARD64 tmp; 220 221 feedback_div = (min_feed_div+max_feed_div)/2; 222 223 tmp = (CARD64)pll->reference_freq * feedback_div; 224 vco = RADEONDiv(tmp, ref_div); 225 226 if (vco < pll->pll_out_min) { 227 min_feed_div = feedback_div+1; 228 continue; 229 } else if(vco > pll->pll_out_max) { 230 max_feed_div = feedback_div; 231 continue; 232 } 233 234 while (min_frac_feed_div < max_frac_feed_div) { 235 frac_feedback_div = (min_frac_feed_div+max_frac_feed_div)/2; 236 tmp = (CARD64)pll->reference_freq * 10000 * feedback_div; 237 tmp += (CARD64)pll->reference_freq * 1000 * frac_feedback_div; 238 current_freq = RADEONDiv(tmp, ref_div * post_div); 239 240 if (flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 241 error = freq - current_freq; 242 error = (int32_t)error < 0 ? 0xffffffff : error; 243 } else 244 error = abs(current_freq - freq); 245 vco_diff = abs(vco - best_vco); 246 247 if ((best_vco == 0 && error < best_error) || 248 (best_vco != 0 && 249 (error < best_error - 100 || 250 (abs(error - best_error) < 100 && vco_diff < best_vco_diff )))) { 251 best_post_div = post_div; 252 best_ref_div = ref_div; 253 best_feedback_div = feedback_div; 254 best_frac_feedback_div = frac_feedback_div; 255 best_freq = current_freq; 256 best_error = error; 257 best_vco_diff = vco_diff; 258 } else if (current_freq == freq) { 259 if (best_freq == -1) { 260 best_post_div = post_div; 261 best_ref_div = ref_div; 262 best_feedback_div = feedback_div; 263 best_frac_feedback_div = frac_feedback_div; 264 best_freq = current_freq; 265 best_error = error; 266 best_vco_diff = vco_diff; 267 } else if (((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 268 ((flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 269 ((flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 270 ((flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 271 ((flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 272 ((flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 273 best_post_div = post_div; 274 best_ref_div = ref_div; 275 best_feedback_div = feedback_div; 276 best_frac_feedback_div = frac_feedback_div; 277 best_freq = current_freq; 278 best_error = error; 279 best_vco_diff = vco_diff; 280 } 281 } 282 if (current_freq < freq) 283 min_frac_feed_div = frac_feedback_div+1; 284 else 285 max_frac_feed_div = frac_feedback_div; 286 } 287 if (current_freq < freq) 288 min_feed_div = feedback_div+1; 289 else 290 max_feed_div = feedback_div; 291 } 292 } 293 } 294 295 ErrorF("best_freq: %u\n", (unsigned int)best_freq); 296 ErrorF("best_feedback_div: %u\n", (unsigned int)best_feedback_div); 297 ErrorF("best_frac_feedback_div: %u\n", (unsigned int)best_frac_feedback_div); 298 ErrorF("best_ref_div: %u\n", (unsigned int)best_ref_div); 299 ErrorF("best_post_div: %u\n", (unsigned int)best_post_div); 300 301 if (best_freq == -1) 302 FatalError("Couldn't find valid PLL dividers\n"); 303 *chosen_dot_clock_freq = best_freq / 10000; 304 *chosen_feedback_div = best_feedback_div; 305 *chosen_frac_feedback_div = best_frac_feedback_div; 306 *chosen_reference_div = best_ref_div; 307 *chosen_post_div = best_post_div; 308 309} 310 311static Bool 312calc_fb_div(RADEONPLLPtr pll, 313 unsigned long freq, 314 int flags, 315 int post_div, 316 int ref_div, 317 int *fb_div, 318 int *fb_div_frac) 319{ 320 float ffreq = freq / 10; 321 float vco_freq = ffreq * post_div; 322 float feedback_divider = vco_freq * ref_div / pll->reference_freq; 323 324 if (flags & RADEON_PLL_USE_FRAC_FB_DIV) { 325 feedback_divider = floor((feedback_divider * 10.0) + 0.5) * 0.1; 326 327 *fb_div = floor(feedback_divider); 328 *fb_div_frac = fmod(feedback_divider, 1.0) * 10.0; 329 330 } else { 331 *fb_div = floor(feedback_divider + 0.5); 332 *fb_div_frac = 0; 333 } 334 if ((*fb_div < pll->min_feedback_div) || (*fb_div > pll->max_feedback_div)) 335 return FALSE; 336 else 337 return TRUE; 338} 339 340static Bool 341calc_fb_ref_div(RADEONPLLPtr pll, 342 unsigned long freq, 343 int flags, 344 int post_div, 345 int *fb_div, 346 int *fb_div_frac, 347 int *ref_div) 348{ 349 float ffreq = freq / 10; 350 float max_error = ffreq * 0.0025; 351 float vco, error, pll_out; 352 353 for ((*ref_div) = pll->min_ref_div; (*ref_div) < pll->max_ref_div; ++(*ref_div)) { 354 if (calc_fb_div(pll, freq, flags, post_div, (*ref_div), fb_div, fb_div_frac)) { 355 vco = pll->reference_freq * ((*fb_div) + ((*fb_div_frac) * 0.1)) / (*ref_div); 356 357 if ((vco < pll->pll_out_min) || (vco > pll->pll_out_max)) 358 continue; 359 360 pll_out = vco / post_div; 361 362 error = pll_out - ffreq; 363 if ((fabs(error) <= max_error) && (error >= 0)) 364 return TRUE; 365 } 366 } 367 return FALSE; 368} 369 370static void 371RADEONComputePLL_new(RADEONPLLPtr pll, 372 unsigned long freq, 373 uint32_t *chosen_dot_clock_freq, 374 uint32_t *chosen_feedback_div, 375 uint32_t *chosen_frac_feedback_div, 376 uint32_t *chosen_reference_div, 377 uint32_t *chosen_post_div, 378 int flags) 379{ 380 float ffreq = freq / 10; 381 float vco_frequency; 382 int fb_div = 0, fb_div_frac = 0, post_div = 0, ref_div = 0; 383 uint32_t best_freq = 0; 384 385 if (flags & RADEON_PLL_USE_POST_DIV) { 386 post_div = pll->post_div; 387 if ((post_div < pll->min_post_div) || (post_div > pll->max_post_div)) 388 goto done; 389 vco_frequency = ffreq * post_div; 390 if ((vco_frequency < pll->pll_out_min) || (vco_frequency > pll->pll_out_max)) 391 goto done; 392 393 if (flags & RADEON_PLL_USE_REF_DIV) { 394 ref_div = pll->reference_div; 395 if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div)) 396 goto done; 397 if (!calc_fb_div(pll, freq, flags, post_div, ref_div, &fb_div, &fb_div_frac)) 398 goto done; 399 } 400 } else { 401 for (post_div = pll->max_post_div; post_div >= pll->min_post_div; --post_div) { 402 if (flags & RADEON_PLL_LEGACY) { 403 if ((post_div == 5) || 404 (post_div == 7) || 405 (post_div == 9) || 406 (post_div == 10) || 407 (post_div == 11)) 408 continue; 409 } 410 if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 411 continue; 412 413 vco_frequency = ffreq * post_div; 414 if ((vco_frequency < pll->pll_out_min) || (vco_frequency > pll->pll_out_max)) 415 continue; 416 if (flags & RADEON_PLL_USE_REF_DIV) { 417 ref_div = pll->reference_div; 418 if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div)) 419 goto done; 420 if (calc_fb_div(pll, freq, flags, post_div, ref_div, &fb_div, &fb_div_frac)) 421 break; 422 } else { 423 if (calc_fb_ref_div(pll, freq, flags, post_div, &fb_div, &fb_div_frac, &ref_div)) 424 break; 425 } 426 } 427 } 428 429 best_freq = pll->reference_freq * 10 * fb_div; 430 best_freq += pll->reference_freq * fb_div_frac; 431 best_freq = best_freq / (ref_div * post_div); 432 433 ErrorF("best_freq: %u\n", (unsigned int)best_freq); 434 ErrorF("best_feedback_div: %u\n", (unsigned int)fb_div); 435 ErrorF("best_frac_feedback_div: %u\n", (unsigned int)fb_div_frac); 436 ErrorF("best_ref_div: %u\n", (unsigned int)ref_div); 437 ErrorF("best_post_div: %u\n", (unsigned int)post_div); 438 439done: 440 if (best_freq == 0) 441 FatalError("Couldn't find valid PLL dividers\n"); 442 443 *chosen_dot_clock_freq = best_freq; 444 *chosen_feedback_div = fb_div; 445 *chosen_frac_feedback_div = fb_div_frac; 446 *chosen_reference_div = ref_div; 447 *chosen_post_div = post_div; 448 449} 450 451void 452RADEONComputePLL(xf86CrtcPtr crtc, 453 RADEONPLLPtr pll, 454 unsigned long freq, 455 uint32_t *chosen_dot_clock_freq, 456 uint32_t *chosen_feedback_div, 457 uint32_t *chosen_frac_feedback_div, 458 uint32_t *chosen_reference_div, 459 uint32_t *chosen_post_div, 460 int flags) 461{ 462 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 463 464 switch (radeon_crtc->pll_algo) { 465 case RADEON_PLL_OLD: 466 RADEONComputePLL_old(pll, freq, chosen_dot_clock_freq, 467 chosen_feedback_div, chosen_frac_feedback_div, 468 chosen_reference_div, chosen_post_div, flags); 469 break; 470 case RADEON_PLL_NEW: 471 /* disable frac fb dividers */ 472 flags &= ~RADEON_PLL_USE_FRAC_FB_DIV; 473 RADEONComputePLL_new(pll, freq, chosen_dot_clock_freq, 474 chosen_feedback_div, chosen_frac_feedback_div, 475 chosen_reference_div, chosen_post_div, flags); 476 break; 477 } 478} 479 480static void 481radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, 482 DisplayModePtr adjusted_mode, int x, int y) 483{ 484 ScrnInfoPtr pScrn = crtc->scrn; 485 RADEONInfoPtr info = RADEONPTR(pScrn); 486 487 if (IS_AVIVO_VARIANT || info->r4xx_atom) { 488 atombios_crtc_mode_set(crtc, mode, adjusted_mode, x, y); 489 } else { 490 legacy_crtc_mode_set(crtc, mode, adjusted_mode, x, y); 491 } 492} 493 494static void 495radeon_crtc_mode_commit(xf86CrtcPtr crtc) 496{ 497 if (crtc->scrn->pScreen != NULL) 498 xf86_reload_cursors(crtc->scrn->pScreen); 499} 500 501void 502radeon_crtc_load_lut(xf86CrtcPtr crtc) 503{ 504 ScrnInfoPtr pScrn = crtc->scrn; 505 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 506 RADEONInfoPtr info = RADEONPTR(pScrn); 507 unsigned char *RADEONMMIO = info->MMIO; 508 int i; 509 510 if (!crtc->enabled) 511 return; 512 513 if (IS_DCE4_VARIANT) { 514 OUTREG(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 515 516 OUTREG(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 517 OUTREG(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 518 OUTREG(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 519 520 OUTREG(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0x0000ffff); 521 OUTREG(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0x0000ffff); 522 OUTREG(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0x0000ffff); 523 524 OUTREG(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 525 OUTREG(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 526 527 for (i = 0; i < 256; i++) { 528 OUTREG(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, i); 529 OUTREG(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 530 (((radeon_crtc->lut_r[i]) << 20) | 531 ((radeon_crtc->lut_g[i]) << 10) | 532 (radeon_crtc->lut_b[i]))); 533 } 534 } else { 535 if (IS_AVIVO_VARIANT) { 536 OUTREG(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); 537 538 OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 539 OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 540 OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 541 542 OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0x0000ffff); 543 OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0x0000ffff); 544 OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0x0000ffff); 545 } 546 547 PAL_SELECT(radeon_crtc->crtc_id); 548 549 if (IS_AVIVO_VARIANT) { 550 OUTREG(AVIVO_DC_LUT_RW_MODE, 0); 551 OUTREG(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); 552 } 553 554 for (i = 0; i < 256; i++) { 555 OUTPAL(i, radeon_crtc->lut_r[i], radeon_crtc->lut_g[i], radeon_crtc->lut_b[i]); 556 } 557 558 if (IS_AVIVO_VARIANT) 559 OUTREG(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); 560 } 561 562} 563 564static void 565radeon_crtc_gamma_set(xf86CrtcPtr crtc, uint16_t *red, uint16_t *green, 566 uint16_t *blue, int size) 567{ 568 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 569 int i; 570 571 for (i = 0; i < 256; i++) { 572 radeon_crtc->lut_r[i] = red[i] >> 6; 573 radeon_crtc->lut_g[i] = green[i] >> 6; 574 radeon_crtc->lut_b[i] = blue[i] >> 6; 575 } 576 577 radeon_crtc_load_lut(crtc); 578} 579 580static Bool 581radeon_crtc_lock(xf86CrtcPtr crtc) 582{ 583 ScrnInfoPtr pScrn = crtc->scrn; 584 RADEONInfoPtr info = RADEONPTR(pScrn); 585 586#ifdef XF86DRI 587 if (info->cp->CPStarted && pScrn->pScreen) { 588 DRILock(pScrn->pScreen, 0); 589 if (info->accelOn) 590 RADEON_SYNC(info, pScrn); 591 return TRUE; 592 } 593#endif 594 if (info->accelOn) 595 RADEON_SYNC(info, pScrn); 596 597 return FALSE; 598 599} 600 601static void 602radeon_crtc_unlock(xf86CrtcPtr crtc) 603{ 604 ScrnInfoPtr pScrn = crtc->scrn; 605 RADEONInfoPtr info = RADEONPTR(pScrn); 606 607#ifdef XF86DRI 608 if (info->cp->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen); 609#endif 610 611 if (info->accelOn) 612 RADEON_SYNC(info, pScrn); 613} 614 615/** 616 * Allocates memory for a locked-in-framebuffer shadow of the given 617 * width and height for this CRTC's rotated shadow framebuffer. 618 */ 619 620static void * 621radeon_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height) 622{ 623 ScrnInfoPtr pScrn = crtc->scrn; 624 RADEONInfoPtr info = RADEONPTR(pScrn); 625 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 626 unsigned long rotate_pitch; 627 unsigned long rotate_offset; 628 int size; 629 int cpp = pScrn->bitsPerPixel / 8; 630 631 /* No rotation without accel */ 632 if (((info->ChipFamily >= CHIP_FAMILY_R600) && !info->directRenderingEnabled) || 633 xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { 634 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 635 "Acceleration required for rotation\n"); 636 return NULL; 637 } 638 639 rotate_pitch = pScrn->displayWidth * cpp; 640 size = rotate_pitch * height; 641 642 /* We could get close to what we want here by just creating a pixmap like 643 * normal, but we have to lock it down in framebuffer, and there is no 644 * setter for offscreen area locking in EXA currently. So, we just 645 * allocate offscreen memory and fake up a pixmap header for it. 646 */ 647 rotate_offset = radeon_legacy_allocate_memory(pScrn, &radeon_crtc->crtc_rotate_mem, 648 size, RADEON_GPU_PAGE_SIZE, RADEON_GEM_DOMAIN_VRAM); 649 if (rotate_offset == 0) 650 return NULL; 651 652 return info->FB + rotate_offset; 653} 654 655/** 656 * Creates a pixmap for this CRTC's rotated shadow framebuffer. 657 */ 658static PixmapPtr 659radeon_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height) 660{ 661 ScrnInfoPtr pScrn = crtc->scrn; 662 unsigned long rotate_pitch; 663 PixmapPtr rotate_pixmap; 664 int cpp = pScrn->bitsPerPixel / 8; 665 666 if (!data) 667 data = radeon_crtc_shadow_allocate(crtc, width, height); 668 669 rotate_pitch = pScrn->displayWidth * cpp; 670 671 rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen, 672 width, height, 673 pScrn->depth, 674 pScrn->bitsPerPixel, 675 rotate_pitch, 676 data); 677 678 if (rotate_pixmap == NULL) { 679 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 680 "Couldn't allocate shadow pixmap for rotated CRTC\n"); 681 } 682 683 return rotate_pixmap; 684} 685 686static void 687radeon_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data) 688{ 689 ScrnInfoPtr pScrn = crtc->scrn; 690 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 691 692 if (rotate_pixmap) 693 FreeScratchPixmapHeader(rotate_pixmap); 694 695 if (data) { 696 radeon_legacy_free_memory(pScrn, radeon_crtc->crtc_rotate_mem); 697 radeon_crtc->crtc_rotate_mem = NULL; 698 } 699 700} 701 702#if XF86_CRTC_VERSION >= 2 703#include "radeon_atombios.h" 704 705extern AtomBiosResult 706atombios_lock_crtc(atomBiosHandlePtr atomBIOS, int crtc, int lock); 707extern void 708RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save, 709 int x, int y); 710extern void 711RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save, 712 int x, int y); 713extern void 714RADEONRestoreCrtcBase(ScrnInfoPtr pScrn, 715 RADEONSavePtr restore); 716extern void 717RADEONRestoreCrtc2Base(ScrnInfoPtr pScrn, 718 RADEONSavePtr restore); 719 720static void 721radeon_crtc_set_origin(xf86CrtcPtr crtc, int x, int y) 722{ 723 ScrnInfoPtr pScrn = crtc->scrn; 724 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 725 RADEONInfoPtr info = RADEONPTR(pScrn); 726 unsigned char *RADEONMMIO = info->MMIO; 727 728 729 if (IS_DCE4_VARIANT) { 730 x &= ~3; 731 y &= ~1; 732 atombios_lock_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1); 733 OUTREG(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y); 734 atombios_lock_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0); 735 } else if (IS_AVIVO_VARIANT) { 736 x &= ~3; 737 y &= ~1; 738 atombios_lock_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1); 739 OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y); 740 atombios_lock_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0); 741 } else { 742 switch (radeon_crtc->crtc_id) { 743 case 0: 744 RADEONInitCrtcBase(crtc, info->ModeReg, x, y); 745 RADEONRestoreCrtcBase(pScrn, info->ModeReg); 746 break; 747 case 1: 748 RADEONInitCrtc2Base(crtc, info->ModeReg, x, y); 749 RADEONRestoreCrtc2Base(pScrn, info->ModeReg); 750 break; 751 default: 752 break; 753 } 754 } 755} 756#endif 757 758 759static xf86CrtcFuncsRec radeon_crtc_funcs = { 760 .dpms = radeon_crtc_dpms, 761 .save = NULL, /* XXX */ 762 .restore = NULL, /* XXX */ 763 .mode_fixup = radeon_crtc_mode_fixup, 764 .prepare = radeon_crtc_mode_prepare, 765 .mode_set = radeon_crtc_mode_set, 766 .commit = radeon_crtc_mode_commit, 767 .gamma_set = radeon_crtc_gamma_set, 768 .lock = radeon_crtc_lock, 769 .unlock = radeon_crtc_unlock, 770 .shadow_create = radeon_crtc_shadow_create, 771 .shadow_allocate = radeon_crtc_shadow_allocate, 772 .shadow_destroy = radeon_crtc_shadow_destroy, 773 .set_cursor_colors = radeon_crtc_set_cursor_colors, 774 .set_cursor_position = radeon_crtc_set_cursor_position, 775 .show_cursor = radeon_crtc_show_cursor, 776 .hide_cursor = radeon_crtc_hide_cursor, 777 .load_cursor_argb = radeon_crtc_load_cursor_argb, 778 .destroy = NULL, /* XXX */ 779#if XF86_CRTC_VERSION >= 2 780 .set_origin = radeon_crtc_set_origin, 781#endif 782}; 783 784void 785RADEONInitDispBandwidth(ScrnInfoPtr pScrn) 786{ 787 RADEONInfoPtr info = RADEONPTR(pScrn); 788 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 789 DisplayModePtr mode1 = NULL, mode2 = NULL; 790 int pixel_bytes1 = info->CurrentLayout.pixel_bytes; 791 int pixel_bytes2 = info->CurrentLayout.pixel_bytes; 792 793 /* XXX fix me */ 794 if (IS_DCE4_VARIANT) 795 return; 796 797 if (xf86_config->num_crtc == 2) { 798 if (xf86_config->crtc[1]->enabled && 799 xf86_config->crtc[0]->enabled) { 800 mode1 = &xf86_config->crtc[0]->mode; 801 mode2 = &xf86_config->crtc[1]->mode; 802 } else if (xf86_config->crtc[0]->enabled) { 803 mode1 = &xf86_config->crtc[0]->mode; 804 } else if (xf86_config->crtc[1]->enabled) { 805 mode2 = &xf86_config->crtc[1]->mode; 806 } else 807 return; 808 } else { 809 if (info->IsPrimary) 810 mode1 = &xf86_config->crtc[0]->mode; 811 else if (info->IsSecondary) 812 mode2 = &xf86_config->crtc[0]->mode; 813 else if (xf86_config->crtc[0]->enabled) 814 mode1 = &xf86_config->crtc[0]->mode; 815 else 816 return; 817 } 818 819 if (IS_AVIVO_VARIANT) 820 RADEONInitDispBandwidthAVIVO(pScrn, mode1, pixel_bytes1, mode2, pixel_bytes2); 821 else 822 RADEONInitDispBandwidthLegacy(pScrn, mode1, pixel_bytes1, mode2, pixel_bytes2); 823} 824 825Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask) 826{ 827 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 828 RADEONInfoPtr info = RADEONPTR(pScrn); 829 int i; 830 831 if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { 832 radeon_crtc_funcs.shadow_create = radeon_crtc_shadow_create; 833 radeon_crtc_funcs.shadow_allocate = radeon_crtc_shadow_allocate; 834 radeon_crtc_funcs.shadow_destroy = radeon_crtc_shadow_destroy; 835 } 836 837 if (mask & 1) { 838 if (pRADEONEnt->Controller[0]) 839 return TRUE; 840 841 pRADEONEnt->pCrtc[0] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs); 842 if (!pRADEONEnt->pCrtc[0]) 843 return FALSE; 844 845 pRADEONEnt->Controller[0] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1); 846 if (!pRADEONEnt->Controller[0]) 847 return FALSE; 848 849 pRADEONEnt->pCrtc[0]->driver_private = pRADEONEnt->Controller[0]; 850 pRADEONEnt->Controller[0]->crtc_id = 0; 851 pRADEONEnt->Controller[0]->crtc_offset = 0; 852 pRADEONEnt->Controller[0]->initialized = FALSE; 853 if (info->allowColorTiling) 854 pRADEONEnt->Controller[0]->can_tile = 1; 855 else 856 pRADEONEnt->Controller[0]->can_tile = 0; 857 pRADEONEnt->Controller[0]->pll_id = -1; 858 } 859 860 if (mask & 2) { 861 if (!pRADEONEnt->HasCRTC2) 862 return TRUE; 863 864 pRADEONEnt->pCrtc[1] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs); 865 if (!pRADEONEnt->pCrtc[1]) 866 return FALSE; 867 868 pRADEONEnt->Controller[1] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1); 869 if (!pRADEONEnt->Controller[1]) 870 { 871 free(pRADEONEnt->Controller[0]); 872 return FALSE; 873 } 874 875 pRADEONEnt->pCrtc[1]->driver_private = pRADEONEnt->Controller[1]; 876 pRADEONEnt->Controller[1]->crtc_id = 1; 877 if (IS_DCE4_VARIANT) 878 pRADEONEnt->Controller[1]->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; 879 else 880 pRADEONEnt->Controller[1]->crtc_offset = AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; 881 pRADEONEnt->Controller[1]->initialized = FALSE; 882 if (info->allowColorTiling) 883 pRADEONEnt->Controller[1]->can_tile = 1; 884 else 885 pRADEONEnt->Controller[1]->can_tile = 0; 886 pRADEONEnt->Controller[1]->pll_id = -1; 887 } 888 889 /* 6 crtcs on DCE4 chips */ 890 if (IS_DCE4_VARIANT && ((mask & 3) == 3) && !IS_DCE41_VARIANT) { 891 for (i = 2; i < RADEON_MAX_CRTC; i++) { 892 pRADEONEnt->pCrtc[i] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs); 893 if (!pRADEONEnt->pCrtc[i]) 894 return FALSE; 895 896 pRADEONEnt->Controller[i] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1); 897 if (!pRADEONEnt->Controller[i]) 898 { 899 free(pRADEONEnt->Controller[i]); 900 return FALSE; 901 } 902 903 pRADEONEnt->pCrtc[i]->driver_private = pRADEONEnt->Controller[i]; 904 pRADEONEnt->Controller[i]->crtc_id = i; 905 switch (i) { 906 case 0: 907 pRADEONEnt->Controller[i]->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; 908 break; 909 case 1: 910 pRADEONEnt->Controller[i]->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; 911 break; 912 case 2: 913 pRADEONEnt->Controller[i]->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; 914 break; 915 case 3: 916 pRADEONEnt->Controller[i]->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; 917 break; 918 case 4: 919 pRADEONEnt->Controller[i]->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; 920 break; 921 case 5: 922 pRADEONEnt->Controller[i]->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; 923 break; 924 } 925 pRADEONEnt->Controller[i]->initialized = FALSE; 926 if (info->allowColorTiling) 927 pRADEONEnt->Controller[i]->can_tile = 1; 928 else 929 pRADEONEnt->Controller[i]->can_tile = 0; 930 pRADEONEnt->Controller[i]->pll_id = -1; 931 } 932 } 933 934 return TRUE; 935} 936 937/** 938 * In the current world order, there are lists of modes per output, which may 939 * or may not include the mode that was asked to be set by XFree86's mode 940 * selection. Find the closest one, in the following preference order: 941 * 942 * - Equality 943 * - Closer in size to the requested mode, but no larger 944 * - Closer in refresh rate to the requested mode. 945 */ 946DisplayModePtr 947RADEONCrtcFindClosestMode(xf86CrtcPtr crtc, DisplayModePtr pMode) 948{ 949 ScrnInfoPtr pScrn = crtc->scrn; 950 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 951 DisplayModePtr pBest = NULL, pScan = NULL; 952 int i; 953 954 /* Assume that there's only one output connected to the given CRTC. */ 955 for (i = 0; i < xf86_config->num_output; i++) 956 { 957 xf86OutputPtr output = xf86_config->output[i]; 958 if (output->crtc == crtc && output->probed_modes != NULL) 959 { 960 pScan = output->probed_modes; 961 break; 962 } 963 } 964 965 /* If the pipe doesn't have any detected modes, just let the system try to 966 * spam the desired mode in. 967 */ 968 if (pScan == NULL) { 969 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 970 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 971 "No crtc mode list for crtc %d," 972 "continuing with desired mode\n", radeon_crtc->crtc_id); 973 return pMode; 974 } 975 976 for (; pScan != NULL; pScan = pScan->next) { 977 assert(pScan->VRefresh != 0.0); 978 979 /* If there's an exact match, we're done. */ 980 if (xf86ModesEqual(pScan, pMode)) { 981 pBest = pMode; 982 break; 983 } 984 985 /* Reject if it's larger than the desired mode. */ 986 if (pScan->HDisplay > pMode->HDisplay || 987 pScan->VDisplay > pMode->VDisplay) 988 { 989 continue; 990 } 991 992 if (pBest == NULL) { 993 pBest = pScan; 994 continue; 995 } 996 997 /* Find if it's closer to the right size than the current best 998 * option. 999 */ 1000 if ((pScan->HDisplay > pBest->HDisplay && 1001 pScan->VDisplay >= pBest->VDisplay) || 1002 (pScan->HDisplay >= pBest->HDisplay && 1003 pScan->VDisplay > pBest->VDisplay)) 1004 { 1005 pBest = pScan; 1006 continue; 1007 } 1008 1009 /* Find if it's still closer to the right refresh than the current 1010 * best resolution. 1011 */ 1012 if (pScan->HDisplay == pBest->HDisplay && 1013 pScan->VDisplay == pBest->VDisplay && 1014 (fabs(pScan->VRefresh - pMode->VRefresh) < 1015 fabs(pBest->VRefresh - pMode->VRefresh))) { 1016 pBest = pScan; 1017 } 1018 } 1019 1020 if (pBest == NULL) { 1021 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1022 "No suitable mode found to program for the pipe.\n" 1023 " continuing with desired mode %dx%d@%.1f\n", 1024 pMode->HDisplay, pMode->VDisplay, pMode->VRefresh); 1025 } else if (!xf86ModesEqual(pBest, pMode)) { 1026 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 1027 int crtc = radeon_crtc->crtc_id; 1028 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1029 "Choosing pipe %d's mode %dx%d@%.1f instead of xf86 " 1030 "mode %dx%d@%.1f\n", crtc, 1031 pBest->HDisplay, pBest->VDisplay, pBest->VRefresh, 1032 pMode->HDisplay, pMode->VDisplay, pMode->VRefresh); 1033 pMode = pBest; 1034 } 1035 return pMode; 1036} 1037 1038void 1039RADEONBlank(ScrnInfoPtr pScrn) 1040{ 1041 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 1042 xf86OutputPtr output; 1043 xf86CrtcPtr crtc; 1044 int o, c; 1045 1046 for (c = 0; c < xf86_config->num_crtc; c++) { 1047 crtc = xf86_config->crtc[c]; 1048 for (o = 0; o < xf86_config->num_output; o++) { 1049 output = xf86_config->output[o]; 1050 if (output->crtc != crtc) 1051 continue; 1052 1053 output->funcs->dpms(output, DPMSModeOff); 1054 } 1055 crtc->funcs->dpms(crtc, DPMSModeOff); 1056 } 1057} 1058 1059void 1060RADEONUnblank(ScrnInfoPtr pScrn) 1061{ 1062 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 1063 xf86OutputPtr output; 1064 xf86CrtcPtr crtc; 1065 int o, c; 1066 1067 for (c = 0; c < xf86_config->num_crtc; c++) { 1068 crtc = xf86_config->crtc[c]; 1069 if(!crtc->enabled) 1070 continue; 1071 crtc->funcs->dpms(crtc, DPMSModeOn); 1072 for (o = 0; o < xf86_config->num_output; o++) { 1073 output = xf86_config->output[o]; 1074 if (output->crtc != crtc) 1075 continue; 1076 1077 output->funcs->dpms(output, DPMSModeOn); 1078 } 1079 } 1080} 1081 1082Bool 1083RADEONSetTiling(ScrnInfoPtr pScrn) 1084{ 1085 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 1086 RADEONInfoPtr info = RADEONPTR(pScrn); 1087 RADEONCrtcPrivatePtr radeon_crtc; 1088 xf86CrtcPtr crtc; 1089 int c; 1090 int can_tile = 1; 1091 Bool changed = FALSE; 1092 1093 for (c = 0; c < xf86_config->num_crtc; c++) { 1094 crtc = xf86_config->crtc[c]; 1095 radeon_crtc = crtc->driver_private; 1096 1097 if (crtc->enabled) { 1098 if (!radeon_crtc->can_tile) 1099 can_tile = 0; 1100 } 1101 } 1102 1103 if (info->tilingEnabled != can_tile) 1104 changed = TRUE; 1105 1106#ifdef XF86DRI 1107 if (info->directRenderingEnabled && (info->tilingEnabled != can_tile)) { 1108 drm_radeon_sarea_t *pSAREAPriv; 1109 if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (can_tile ? 1 : 0)) < 0) 1110 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1111 "[drm] failed changing tiling status\n"); 1112 /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */ 1113 pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]); 1114 info->tilingEnabled = pSAREAPriv->tiling_enabled ? TRUE : FALSE; 1115 } 1116#endif 1117 1118 return changed; 1119} 1120