radeon_cursor.c revision 486efd68 
1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 *                VA Linux Systems Inc., Fremont, California.
4 *
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation on the rights to use, copy, modify, merge,
11 * publish, distribute, sublicense, and/or sell copies of the Software,
12 * and to permit persons to whom the Software is furnished to do so,
13 * subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial
17 * portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
22 * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 */
28
29#ifdef HAVE_CONFIG_H
30#include "config.h"
31#endif
32
33#define RADEONCTRACE(x)
34/*#define RADEONCTRACE(x) RADEONTRACE(x) */
35
36/*
37 * Authors:
38 *   Kevin E. Martin <martin@xfree86.org>
39 *   Rickard E. Faith <faith@valinux.com>
40 *
41 * References:
42 *
43 * !!!! FIXME !!!!
44 *   RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
45 *   Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
46 *   1999.
47 *
48 *   RAGE 128 Software Development Manual (Technical Reference Manual P/N
49 *   SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
50 *
51 */
52
53				/* Driver data structures */
54#include "radeon.h"
55#include "radeon_version.h"
56#include "radeon_reg.h"
57#include "radeon_macros.h"
58
59				/* X and server generic header files */
60#include "xf86.h"
61
62#define CURSOR_WIDTH	64
63#define CURSOR_HEIGHT	64
64
65/*
66 * The cursor bits are always 32bpp.  On MSBFirst buses,
67 * configure byte swapping to swap 32 bit units when writing
68 * the cursor image.  Byte swapping must always be returned
69 * to its previous value before returning.
70 */
71#if X_BYTE_ORDER == X_BIG_ENDIAN
72
73#define CURSOR_SWAPPING_DECL_MMIO   unsigned char *RADEONMMIO = info->MMIO;
74#define CURSOR_SWAPPING_START() \
75  do { \
76  if (info->ChipFamily < CHIP_FAMILY_R600) \
77    OUTREG(RADEON_SURFACE_CNTL, \
78	   (info->ModeReg->surface_cntl | \
79	     RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP) & \
80	   ~(RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP)); \
81  } while (0)
82#define CURSOR_SWAPPING_END()	\
83  do { \
84  if (info->ChipFamily < CHIP_FAMILY_R600) \
85      OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl); \
86  } while (0)
87#else
88
89#define CURSOR_SWAPPING_DECL_MMIO
90#define CURSOR_SWAPPING_START()
91#define CURSOR_SWAPPING_END()
92
93#endif
94
95static void
96avivo_setup_cursor(xf86CrtcPtr crtc, Bool enable)
97{
98    ScrnInfoPtr pScrn = crtc->scrn;
99    RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
100    RADEONInfoPtr  info = RADEONPTR(crtc->scrn);
101    unsigned char     *RADEONMMIO = info->MMIO;
102
103    /* always use the same cursor mode even if the cursor is disabled,
104     * otherwise you may end up with cursor curruption bands
105     */
106    OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
107
108    if (enable) {
109	OUTREG(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
110	       info->fbLocation + radeon_crtc->cursor_offset + pScrn->fbOffset);
111	OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,
112	       AVIVO_D1CURSOR_EN | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
113    }
114}
115
116static void
117avivo_lock_cursor(xf86CrtcPtr crtc, Bool lock)
118{
119    RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
120    RADEONInfoPtr  info = RADEONPTR(crtc->scrn);
121    unsigned char     *RADEONMMIO = info->MMIO;
122    uint32_t tmp;
123
124    tmp = INREG(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);
125
126    if (lock)
127	tmp |= AVIVO_D1CURSOR_UPDATE_LOCK;
128    else
129	tmp &= ~AVIVO_D1CURSOR_UPDATE_LOCK;
130
131    OUTREG(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, tmp);
132}
133
134void
135radeon_crtc_show_cursor (xf86CrtcPtr crtc)
136{
137    ScrnInfoPtr pScrn = crtc->scrn;
138    RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
139    int crtc_id = radeon_crtc->crtc_id;
140    RADEONInfoPtr      info       = RADEONPTR(pScrn);
141    unsigned char     *RADEONMMIO = info->MMIO;
142
143    if (IS_AVIVO_VARIANT) {
144	avivo_lock_cursor(crtc, TRUE);
145	avivo_setup_cursor(crtc, TRUE);
146	avivo_lock_cursor(crtc, FALSE);
147    } else {
148        switch (crtc_id) {
149        case 0:
150            OUTREG(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
151	    break;
152        case 1:
153            OUTREG(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
154	    break;
155        default:
156            return;
157        }
158
159        OUTREGP(RADEON_MM_DATA, RADEON_CRTC_CUR_EN | 2 << 20,
160                ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
161    }
162}
163
164void
165radeon_crtc_hide_cursor (xf86CrtcPtr crtc)
166{
167    ScrnInfoPtr pScrn = crtc->scrn;
168    RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
169    int crtc_id = radeon_crtc->crtc_id;
170    RADEONInfoPtr      info       = RADEONPTR(pScrn);
171    unsigned char     *RADEONMMIO = info->MMIO;
172
173    if (IS_AVIVO_VARIANT) {
174	avivo_lock_cursor(crtc, TRUE);
175	avivo_setup_cursor(crtc, FALSE);
176	avivo_lock_cursor(crtc, FALSE);
177    } else {
178	switch(crtc_id) {
179    	case 0:
180            OUTREG(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
181            break;
182    	case 1:
183	    OUTREG(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
184	    break;
185        default:
186	    return;
187        }
188
189        OUTREGP(RADEON_MM_DATA, 0, ~RADEON_CRTC_CUR_EN);
190   }
191}
192
193void
194radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y)
195{
196    ScrnInfoPtr pScrn = crtc->scrn;
197    RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
198    RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
199    int crtc_id = radeon_crtc->crtc_id;
200    RADEONInfoPtr      info       = RADEONPTR(pScrn);
201    unsigned char     *RADEONMMIO = info->MMIO;
202    int xorigin = 0, yorigin = 0;
203    int stride = 256;
204    DisplayModePtr mode = &crtc->mode;
205
206    if (x < 0)                        xorigin = -x+1;
207    if (y < 0)                        yorigin = -y+1;
208    if (xorigin >= CURSOR_WIDTH)  xorigin = CURSOR_WIDTH - 1;
209    if (yorigin >= CURSOR_HEIGHT) yorigin = CURSOR_HEIGHT - 1;
210
211    if (IS_AVIVO_VARIANT) {
212	int w = CURSOR_WIDTH;
213
214	/* avivo cursor spans the full fb width */
215	if (crtc->rotatedData == NULL) {
216	    x += crtc->x;
217	    y += crtc->y;
218	}
219
220	if (pRADEONEnt->Controller[0]->enabled &&
221	    pRADEONEnt->Controller[1]->enabled) {
222	    int cursor_end, frame_end;
223
224	    cursor_end = x - xorigin + w;
225	    frame_end = crtc->x + mode->CrtcHDisplay;
226
227	    if (cursor_end >= frame_end) {
228		w = w - (cursor_end - frame_end);
229		if (!(frame_end & 0x7f))
230		    w--;
231	    } else {
232		if (!(cursor_end & 0x7f))
233		    w--;
234	    }
235	    if (w <= 0)
236		w = 1;
237	}
238
239	avivo_lock_cursor(crtc, TRUE);
240	OUTREG(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, ((xorigin ? 0 : x) << 16)
241	       | (yorigin ? 0 : y));
242	OUTREG(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
243	OUTREG(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, ((w - 1) << 16) | (CURSOR_HEIGHT - 1));
244	avivo_lock_cursor(crtc, FALSE);
245    } else {
246	if (mode->Flags & V_DBLSCAN)
247	    y *= 2;
248
249	if (crtc_id == 0) {
250	    OUTREG(RADEON_CUR_HORZ_VERT_OFF,  (RADEON_CUR_LOCK
251					       | (xorigin << 16)
252					       | yorigin));
253	    OUTREG(RADEON_CUR_HORZ_VERT_POSN, (RADEON_CUR_LOCK
254					       | ((xorigin ? 0 : x) << 16)
255					       | (yorigin ? 0 : y)));
256	    RADEONCTRACE(("cursor_offset: 0x%x, yorigin: %d, stride: %d, temp %08X\n",
257			  radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp));
258	    OUTREG(RADEON_CUR_OFFSET,
259		   radeon_crtc->cursor_offset + pScrn->fbOffset + yorigin * stride);
260	} else if (crtc_id == 1) {
261	    OUTREG(RADEON_CUR2_HORZ_VERT_OFF,  (RADEON_CUR2_LOCK
262						| (xorigin << 16)
263						| yorigin));
264	    OUTREG(RADEON_CUR2_HORZ_VERT_POSN, (RADEON_CUR2_LOCK
265						| ((xorigin ? 0 : x) << 16)
266						| (yorigin ? 0 : y)));
267	    RADEONCTRACE(("cursor_offset2: 0x%x, yorigin: %d, stride: %d, temp %08X\n",
268			  radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp));
269	    OUTREG(RADEON_CUR2_OFFSET,
270		   radeon_crtc->cursor_offset + pScrn->fbOffset + yorigin * stride);
271	}
272    }
273}
274
275void
276radeon_crtc_set_cursor_colors (xf86CrtcPtr crtc, int bg, int fg)
277{
278    ScrnInfoPtr pScrn = crtc->scrn;
279    RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
280    RADEONInfoPtr info = RADEONPTR(pScrn);
281    uint32_t *pixels = (uint32_t *)(pointer)(info->FB + radeon_crtc->cursor_offset);
282    int            pixel, i;
283    CURSOR_SWAPPING_DECL_MMIO
284
285    RADEONCTRACE(("RADEONSetCursorColors\n"));
286
287#ifdef ARGB_CURSOR
288    /* Don't recolour cursors set with SetCursorARGB. */
289    if (info->cursor_argb)
290       return;
291#endif
292
293    fg |= 0xff000000;
294    bg |= 0xff000000;
295
296    /* Don't recolour the image if we don't have to. */
297    if (fg == info->cursor_fg && bg == info->cursor_bg)
298       return;
299
300    CURSOR_SWAPPING_START();
301
302    /* Note: We assume that the pixels are either fully opaque or fully
303     * transparent, so we won't premultiply them, and we can just
304     * check for non-zero pixel values; those are either fg or bg
305     */
306    for (i = 0; i < CURSOR_WIDTH * CURSOR_HEIGHT; i++, pixels++)
307       if ((pixel = *pixels))
308           *pixels = (pixel == info->cursor_fg) ? fg : bg;
309
310    CURSOR_SWAPPING_END();
311    info->cursor_fg = fg;
312    info->cursor_bg = bg;
313}
314
315#ifdef ARGB_CURSOR
316
317void
318radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image)
319{
320    ScrnInfoPtr pScrn = crtc->scrn;
321    RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
322    RADEONInfoPtr  info = RADEONPTR(pScrn);
323    CURSOR_SWAPPING_DECL_MMIO
324    uint32_t *d = (uint32_t *)(pointer)(info->FB + radeon_crtc->cursor_offset);
325
326    RADEONCTRACE(("RADEONLoadCursorARGB\n"));
327
328    info->cursor_argb = TRUE;
329
330    CURSOR_SWAPPING_START();
331
332    memcpy (d, image, CURSOR_HEIGHT * CURSOR_WIDTH * 4);
333
334    CURSOR_SWAPPING_END ();
335}
336
337#endif
338
339
340/* Initialize hardware cursor support. */
341Bool RADEONCursorInit(ScreenPtr pScreen)
342{
343    ScrnInfoPtr        pScrn   = xf86Screens[pScreen->myNum];
344    RADEONInfoPtr      info    = RADEONPTR(pScrn);
345    unsigned char     *RADEONMMIO = info->MMIO;
346    xf86CrtcConfigPtr  xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
347    int                c;
348
349    for (c = 0; c < xf86_config->num_crtc; c++) {
350	xf86CrtcPtr crtc = xf86_config->crtc[c];
351	RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
352
353	if (!info->useEXA) {
354	    int size_bytes  = CURSOR_WIDTH * 4 * CURSOR_HEIGHT;
355	    int align = IS_AVIVO_VARIANT ? 4096 : 256;
356
357	    radeon_crtc->cursor_offset =
358		radeon_legacy_allocate_memory(pScrn, &radeon_crtc->cursor_mem, size_bytes, align);
359
360	    if (radeon_crtc->cursor_offset == 0)
361		return FALSE;
362
363	    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
364		       "Will use %d kb for hardware cursor %d at offset 0x%08x\n",
365		       (size_bytes * xf86_config->num_crtc) / 1024,
366		       c,
367		       (unsigned int)radeon_crtc->cursor_offset);
368	}
369	/* set the cursor mode the same on both crtcs to avoid corruption */
370	if (IS_AVIVO_VARIANT)
371	    OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,
372		   (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
373    }
374
375    return xf86_cursors_init (pScreen, CURSOR_WIDTH, CURSOR_HEIGHT,
376			      (HARDWARE_CURSOR_TRUECOLOR_AT_8BPP |
377			       HARDWARE_CURSOR_AND_SOURCE_WITH_MASK |
378			       HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_1 |
379			       HARDWARE_CURSOR_ARGB));
380}
381