radeon_cursor.c revision 51b40f85
1/* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining 8 * a copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation on the rights to use, copy, modify, merge, 11 * publish, distribute, sublicense, and/or sell copies of the Software, 12 * and to permit persons to whom the Software is furnished to do so, 13 * subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 */ 28 29#ifdef HAVE_CONFIG_H 30#include "config.h" 31#endif 32 33#define RADEONCTRACE(x) 34/*#define RADEONCTRACE(x) RADEONTRACE(x) */ 35 36/* 37 * Authors: 38 * Kevin E. Martin <martin@xfree86.org> 39 * Rickard E. Faith <faith@valinux.com> 40 * 41 * References: 42 * 43 * !!!! FIXME !!!! 44 * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical 45 * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April 46 * 1999. 47 * 48 * RAGE 128 Software Development Manual (Technical Reference Manual P/N 49 * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. 50 * 51 */ 52 53 /* Driver data structures */ 54#include "radeon.h" 55#include "radeon_version.h" 56#include "radeon_reg.h" 57#include "radeon_macros.h" 58 59 /* X and server generic header files */ 60#include "xf86.h" 61 62#define CURSOR_WIDTH 64 63#define CURSOR_HEIGHT 64 64 65/* 66 * The cursor bits are always 32bpp. On MSBFirst buses, 67 * configure byte swapping to swap 32 bit units when writing 68 * the cursor image. Byte swapping must always be returned 69 * to its previous value before returning. 70 */ 71#if X_BYTE_ORDER == X_BIG_ENDIAN 72 73#define CURSOR_SWAPPING_DECL_MMIO unsigned char *RADEONMMIO = info->MMIO; 74#define CURSOR_SWAPPING_START() \ 75 do { \ 76 if (info->ChipFamily < CHIP_FAMILY_R600) \ 77 OUTREG(RADEON_SURFACE_CNTL, \ 78 (info->ModeReg->surface_cntl | \ 79 RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP) & \ 80 ~(RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP)); \ 81 } while (0) 82#define CURSOR_SWAPPING_END() \ 83 do { \ 84 if (info->ChipFamily < CHIP_FAMILY_R600) \ 85 OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl); \ 86 } while (0) 87#else 88 89#define CURSOR_SWAPPING_DECL_MMIO 90#define CURSOR_SWAPPING_START() 91#define CURSOR_SWAPPING_END() 92 93#endif 94 95static void 96avivo_setup_cursor(xf86CrtcPtr crtc, Bool enable) 97{ 98 ScrnInfoPtr pScrn = crtc->scrn; 99 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 100 RADEONInfoPtr info = RADEONPTR(crtc->scrn); 101 unsigned char *RADEONMMIO = info->MMIO; 102 103 /* always use the same cursor mode even if the cursor is disabled, 104 * otherwise you may end up with cursor curruption bands 105 */ 106 OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); 107 108 if (enable) { 109 if (info->ChipFamily >= CHIP_FAMILY_RV770) { 110 if (radeon_crtc->crtc_id) 111 OUTREG(R700_D2CUR_SURFACE_ADDRESS_HIGH, 0); 112 else 113 OUTREG(R700_D1CUR_SURFACE_ADDRESS_HIGH, 0); 114 } 115 OUTREG(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 116 info->fbLocation + radeon_crtc->cursor_offset + pScrn->fbOffset); 117 OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, 118 AVIVO_D1CURSOR_EN | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); 119 } 120} 121 122static void 123avivo_lock_cursor(xf86CrtcPtr crtc, Bool lock) 124{ 125 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 126 RADEONInfoPtr info = RADEONPTR(crtc->scrn); 127 unsigned char *RADEONMMIO = info->MMIO; 128 uint32_t tmp; 129 130 tmp = INREG(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); 131 132 if (lock) 133 tmp |= AVIVO_D1CURSOR_UPDATE_LOCK; 134 else 135 tmp &= ~AVIVO_D1CURSOR_UPDATE_LOCK; 136 137 OUTREG(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, tmp); 138} 139 140static void 141evergreen_setup_cursor(xf86CrtcPtr crtc, Bool enable) 142{ 143 ScrnInfoPtr pScrn = crtc->scrn; 144 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 145 RADEONInfoPtr info = RADEONPTR(crtc->scrn); 146 unsigned char *RADEONMMIO = info->MMIO; 147 148 /* always use the same cursor mode even if the cursor is disabled, 149 * otherwise you may end up with cursor curruption bands 150 */ 151 OUTREG(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset, 152 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT)); 153 154 if (enable) { 155 OUTREG(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 0); 156 OUTREG(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 157 (info->fbLocation + radeon_crtc->cursor_offset + pScrn->fbOffset) 158 & EVERGREEN_CUR_SURFACE_ADDRESS_MASK); 159 OUTREG(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset, 160 EVERGREEN_CURSOR_EN | EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT)); 161 } 162} 163 164static void 165evergreen_lock_cursor(xf86CrtcPtr crtc, Bool lock) 166{ 167 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 168 RADEONInfoPtr info = RADEONPTR(crtc->scrn); 169 unsigned char *RADEONMMIO = info->MMIO; 170 uint32_t tmp; 171 172 tmp = INREG(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset); 173 174 if (lock) 175 tmp |= EVERGREEN_CURSOR_UPDATE_LOCK; 176 else 177 tmp &= ~EVERGREEN_CURSOR_UPDATE_LOCK; 178 179 OUTREG(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, tmp); 180} 181 182void 183radeon_crtc_show_cursor (xf86CrtcPtr crtc) 184{ 185 ScrnInfoPtr pScrn = crtc->scrn; 186 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 187 int crtc_id = radeon_crtc->crtc_id; 188 RADEONInfoPtr info = RADEONPTR(pScrn); 189 unsigned char *RADEONMMIO = info->MMIO; 190 191 if (IS_DCE4_VARIANT) { 192 evergreen_lock_cursor(crtc, TRUE); 193 evergreen_setup_cursor(crtc, TRUE); 194 evergreen_lock_cursor(crtc, FALSE); 195 } else if (IS_AVIVO_VARIANT) { 196 avivo_lock_cursor(crtc, TRUE); 197 avivo_setup_cursor(crtc, TRUE); 198 avivo_lock_cursor(crtc, FALSE); 199 } else { 200 switch (crtc_id) { 201 case 0: 202 OUTREG(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); 203 break; 204 case 1: 205 OUTREG(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL); 206 break; 207 default: 208 return; 209 } 210 211 OUTREGP(RADEON_MM_DATA, RADEON_CRTC_CUR_EN | 2 << 20, 212 ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK)); 213 } 214} 215 216void 217radeon_crtc_hide_cursor (xf86CrtcPtr crtc) 218{ 219 ScrnInfoPtr pScrn = crtc->scrn; 220 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 221 int crtc_id = radeon_crtc->crtc_id; 222 RADEONInfoPtr info = RADEONPTR(pScrn); 223 unsigned char *RADEONMMIO = info->MMIO; 224 225 if (IS_DCE4_VARIANT) { 226 evergreen_lock_cursor(crtc, TRUE); 227 evergreen_setup_cursor(crtc, FALSE); 228 evergreen_lock_cursor(crtc, TRUE); 229 } else if (IS_AVIVO_VARIANT) { 230 avivo_lock_cursor(crtc, TRUE); 231 avivo_setup_cursor(crtc, FALSE); 232 avivo_lock_cursor(crtc, FALSE); 233 } else { 234 switch(crtc_id) { 235 case 0: 236 OUTREG(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); 237 break; 238 case 1: 239 OUTREG(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL); 240 break; 241 default: 242 return; 243 } 244 245 OUTREGP(RADEON_MM_DATA, 0, ~RADEON_CRTC_CUR_EN); 246 } 247} 248 249void 250radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y) 251{ 252 ScrnInfoPtr pScrn = crtc->scrn; 253 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 254 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 255 int crtc_id = radeon_crtc->crtc_id; 256 RADEONInfoPtr info = RADEONPTR(pScrn); 257 unsigned char *RADEONMMIO = info->MMIO; 258 int xorigin = 0, yorigin = 0; 259 int stride = 256; 260 DisplayModePtr mode = &crtc->mode; 261 262 if (x < 0) xorigin = -x+1; 263 if (y < 0) yorigin = -y+1; 264 if (xorigin >= CURSOR_WIDTH) xorigin = CURSOR_WIDTH - 1; 265 if (yorigin >= CURSOR_HEIGHT) yorigin = CURSOR_HEIGHT - 1; 266 267 if (IS_DCE4_VARIANT) { 268 /* XXX - does evergreen need a similar hack as below? */ 269 evergreen_lock_cursor(crtc, TRUE); 270 OUTREG(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, ((xorigin ? 0 : x) << 16) 271 | (yorigin ? 0 : y)); 272 OUTREG(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); 273 OUTREG(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset, 274 ((CURSOR_WIDTH - 1) << 16) | (CURSOR_HEIGHT - 1)); 275 evergreen_lock_cursor(crtc, FALSE); 276 } else if (IS_AVIVO_VARIANT) { 277 int w = CURSOR_WIDTH; 278 279 /* avivo cursor spans the full fb width */ 280 if (crtc->rotatedData == NULL) { 281 x += crtc->x; 282 y += crtc->y; 283 } 284 285 if (pRADEONEnt->Controller[0]->enabled && 286 pRADEONEnt->Controller[1]->enabled) { 287 int cursor_end, frame_end; 288 289 cursor_end = x - xorigin + w; 290 frame_end = crtc->x + mode->CrtcHDisplay; 291 292 if (cursor_end >= frame_end) { 293 w = w - (cursor_end - frame_end); 294 if (!(frame_end & 0x7f)) 295 w--; 296 } else { 297 if (!(cursor_end & 0x7f)) 298 w--; 299 } 300 if (w <= 0) 301 w = 1; 302 } 303 304 avivo_lock_cursor(crtc, TRUE); 305 OUTREG(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, ((xorigin ? 0 : x) << 16) 306 | (yorigin ? 0 : y)); 307 OUTREG(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); 308 OUTREG(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, ((w - 1) << 16) | (CURSOR_HEIGHT - 1)); 309 avivo_lock_cursor(crtc, FALSE); 310 } else { 311 if (mode->Flags & V_DBLSCAN) 312 y *= 2; 313 314 if (crtc_id == 0) { 315 OUTREG(RADEON_CUR_HORZ_VERT_OFF, (RADEON_CUR_LOCK 316 | (xorigin << 16) 317 | yorigin)); 318 OUTREG(RADEON_CUR_HORZ_VERT_POSN, (RADEON_CUR_LOCK 319 | ((xorigin ? 0 : x) << 16) 320 | (yorigin ? 0 : y))); 321 RADEONCTRACE(("cursor_offset: 0x%x, yorigin: %d, stride: %d, temp %08X\n", 322 radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp)); 323 OUTREG(RADEON_CUR_OFFSET, 324 radeon_crtc->cursor_offset + pScrn->fbOffset + yorigin * stride); 325 } else if (crtc_id == 1) { 326 OUTREG(RADEON_CUR2_HORZ_VERT_OFF, (RADEON_CUR2_LOCK 327 | (xorigin << 16) 328 | yorigin)); 329 OUTREG(RADEON_CUR2_HORZ_VERT_POSN, (RADEON_CUR2_LOCK 330 | ((xorigin ? 0 : x) << 16) 331 | (yorigin ? 0 : y))); 332 RADEONCTRACE(("cursor_offset2: 0x%x, yorigin: %d, stride: %d, temp %08X\n", 333 radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp)); 334 OUTREG(RADEON_CUR2_OFFSET, 335 radeon_crtc->cursor_offset + pScrn->fbOffset + yorigin * stride); 336 } 337 } 338} 339 340void 341radeon_crtc_set_cursor_colors (xf86CrtcPtr crtc, int bg, int fg) 342{ 343 ScrnInfoPtr pScrn = crtc->scrn; 344 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 345 RADEONInfoPtr info = RADEONPTR(pScrn); 346 uint32_t *pixels = (uint32_t *)(pointer)(info->FB + pScrn->fbOffset + radeon_crtc->cursor_offset); 347 int pixel, i; 348 CURSOR_SWAPPING_DECL_MMIO 349 350 RADEONCTRACE(("RADEONSetCursorColors\n")); 351 352#ifdef ARGB_CURSOR 353 /* Don't recolour cursors set with SetCursorARGB. */ 354 if (info->cursor_argb) 355 return; 356#endif 357 358 fg |= 0xff000000; 359 bg |= 0xff000000; 360 361 /* Don't recolour the image if we don't have to. */ 362 if (fg == info->cursor_fg && bg == info->cursor_bg) 363 return; 364 365 CURSOR_SWAPPING_START(); 366 367 /* Note: We assume that the pixels are either fully opaque or fully 368 * transparent, so we won't premultiply them, and we can just 369 * check for non-zero pixel values; those are either fg or bg 370 */ 371 for (i = 0; i < CURSOR_WIDTH * CURSOR_HEIGHT; i++, pixels++) 372 if ((pixel = *pixels)) 373 *pixels = (pixel == info->cursor_fg) ? fg : bg; 374 375 CURSOR_SWAPPING_END(); 376 info->cursor_fg = fg; 377 info->cursor_bg = bg; 378} 379 380#ifdef ARGB_CURSOR 381 382void 383radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image) 384{ 385 ScrnInfoPtr pScrn = crtc->scrn; 386 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 387 RADEONInfoPtr info = RADEONPTR(pScrn); 388 CURSOR_SWAPPING_DECL_MMIO 389 uint32_t *d = (uint32_t *)(pointer)(info->FB + pScrn->fbOffset + radeon_crtc->cursor_offset); 390 391 RADEONCTRACE(("RADEONLoadCursorARGB\n")); 392 393 info->cursor_argb = TRUE; 394 395 CURSOR_SWAPPING_START(); 396 397 memcpy (d, image, CURSOR_HEIGHT * CURSOR_WIDTH * 4); 398 399 CURSOR_SWAPPING_END (); 400} 401 402#endif 403 404 405/* Initialize hardware cursor support. */ 406Bool RADEONCursorInit(ScreenPtr pScreen) 407{ 408 ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; 409 RADEONInfoPtr info = RADEONPTR(pScrn); 410 unsigned char *RADEONMMIO = info->MMIO; 411 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 412 int c; 413 414 for (c = 0; c < xf86_config->num_crtc; c++) { 415 xf86CrtcPtr crtc = xf86_config->crtc[c]; 416 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 417 418 if (!info->useEXA) { 419 int size_bytes = CURSOR_WIDTH * 4 * CURSOR_HEIGHT; 420 int align = IS_AVIVO_VARIANT ? 4096 : 256; 421 422 radeon_crtc->cursor_offset = 423 radeon_legacy_allocate_memory(pScrn, &radeon_crtc->cursor_mem, 424 size_bytes, align, RADEON_GEM_DOMAIN_VRAM); 425 426 if (radeon_crtc->cursor_offset == 0) 427 return FALSE; 428 429 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 430 "Will use %d kb for hardware cursor %d at offset 0x%08x\n", 431 (size_bytes * xf86_config->num_crtc) / 1024, 432 c, 433 (unsigned int)radeon_crtc->cursor_offset); 434 } 435 /* set the cursor mode the same on both crtcs to avoid corruption */ 436 /* XXX check if this is needed on evergreen */ 437 if (IS_AVIVO_VARIANT) 438 OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, 439 (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); 440 } 441 442 return xf86_cursors_init (pScreen, CURSOR_WIDTH, CURSOR_HEIGHT, 443 (HARDWARE_CURSOR_TRUECOLOR_AT_8BPP | 444 HARDWARE_CURSOR_AND_SOURCE_WITH_MASK | 445 HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_1 | 446 HARDWARE_CURSOR_ARGB)); 447} 448