radeon_dri.h revision 209ff23f 
1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario,
3 *                VA Linux Systems Inc., Fremont, California.
4 *
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation on the rights to use, copy, modify, merge,
11 * publish, distribute, sublicense, and/or sell copies of the Software,
12 * and to permit persons to whom the Software is furnished to do so,
13 * subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial
17 * portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
22 * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 */
28
29/*
30 * Authors:
31 *   Kevin E. Martin <martin@xfree86.org>
32 *   Rickard E. Faith <faith@valinux.com>
33 *
34 */
35
36#ifndef _RADEON_DRI_
37#define _RADEON_DRI_
38
39#include "xf86drm.h"
40
41/* DRI Driver defaults */
42#define RADEON_DEFAULT_CP_PIO_MODE    RADEON_CSQ_PRIPIO_INDPIO
43#define RADEON_DEFAULT_CP_BM_MODE     RADEON_CSQ_PRIBM_INDBM
44#define RADEON_DEFAULT_GART_SIZE      8 /* MB (must be 2^n and > 4MB) */
45#define RADEON_DEFAULT_RING_SIZE      1 /* MB (must be page aligned) */
46#define RADEON_DEFAULT_BUFFER_SIZE    2 /* MB (must be page aligned) */
47#define RADEON_DEFAULT_GART_TEX_SIZE  1 /* MB (must be page aligned) */
48
49#define RADEON_DEFAULT_CP_TIMEOUT     100000  /* usecs */
50
51#define RADEON_DEFAULT_PCI_APER_SIZE 32 /* in MB */
52
53#define RADEON_CARD_TYPE_RADEON       1
54
55#define RADEONCP_USE_RING_BUFFER(m)					\
56    (((m) == RADEON_CSQ_PRIBM_INDDIS) ||				\
57     ((m) == RADEON_CSQ_PRIBM_INDBM))
58
59typedef struct {
60    /* DRI screen private data */
61    int           deviceID;	/* PCI device ID */
62    int           width;	/* Width in pixels of display */
63    int           height;	/* Height in scanlines of display */
64    int           depth;	/* Depth of display (8, 15, 16, 24) */
65    int           bpp;		/* Bit depth of display (8, 16, 24, 32) */
66
67    int           IsPCI;	/* Current card is a PCI card */
68    int           AGPMode;
69
70    int           frontOffset;  /* Start of front buffer */
71    int           frontPitch;
72    int           backOffset;   /* Start of shared back buffer */
73    int           backPitch;
74    int           depthOffset;  /* Start of shared depth buffer */
75    int           depthPitch;
76    int           textureOffset;/* Start of texture data in frame buffer */
77    int           textureSize;
78    int           log2TexGran;
79
80    /* MMIO register data */
81    drm_handle_t     registerHandle;
82    drmSize       registerSize;
83
84    /* CP in-memory status information */
85    drm_handle_t     statusHandle;
86    drmSize       statusSize;
87
88    /* CP GART Texture data */
89    drm_handle_t     gartTexHandle;
90    drmSize       gartTexMapSize;
91    int           log2GARTTexGran;
92    int           gartTexOffset;
93    unsigned int  sarea_priv_offset;
94
95#ifdef PER_CONTEXT_SAREA
96    drmSize      perctx_sarea_size;
97#endif
98} RADEONDRIRec, *RADEONDRIPtr;
99
100#endif
101