radeon_driver.c revision 3336cae5
1/* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining 8 * a copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation on the rights to use, copy, modify, merge, 11 * publish, distribute, sublicense, and/or sell copies of the Software, 12 * and to permit persons to whom the Software is furnished to do so, 13 * subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 */ 28 29#ifdef HAVE_CONFIG_H 30#include "config.h" 31#endif 32 33/* 34 * Authors: 35 * Kevin E. Martin <martin@xfree86.org> 36 * Rickard E. Faith <faith@valinux.com> 37 * Alan Hourihane <alanh@fairlite.demon.co.uk> 38 * 39 * Credits: 40 * 41 * Thanks to Ani Joshi <ajoshi@shell.unixbox.com> for providing source 42 * code to his Radeon driver. Portions of this file are based on the 43 * initialization code for that driver. 44 * 45 * References: 46 * 47 * !!!! FIXME !!!! 48 * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical 49 * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April 50 * 1999. 51 * 52 * RAGE 128 Software Development Manual (Technical Reference Manual P/N 53 * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. 54 * 55 * This server does not yet support these XFree86 4.0 features: 56 * !!!! FIXME !!!! 57 * DDC1 & DDC2 58 * shadowfb 59 * overlay planes 60 * 61 * Modified by Marc Aurele La France (tsi@xfree86.org) for ATI driver merge. 62 * 63 * Mergedfb and pseudo xinerama support added by Alex Deucher (agd5f@yahoo.com) 64 * based on the sis driver by Thomas Winischhofer. 65 * 66 */ 67 68#include <string.h> 69#include <stdio.h> 70 71 /* Driver data structures */ 72#include "radeon.h" 73#include "radeon_reg.h" 74#include "radeon_macros.h" 75#include "radeon_probe.h" 76#include "radeon_version.h" 77#include "radeon_atombios.h" 78 79#ifdef XF86DRI 80#define _XF86DRI_SERVER_ 81#include "radeon_dri.h" 82#include "radeon_sarea.h" 83#include "sarea.h" 84#endif 85 86#include "fb.h" 87 88 /* colormap initialization */ 89#include "micmap.h" 90#include "dixstruct.h" 91 92 /* X and server generic header files */ 93#include "xf86.h" 94#include "xf86_OSproc.h" 95#include "xf86RAC.h" 96#include "xf86RandR12.h" 97#include "xf86Resources.h" 98#include "xf86cmap.h" 99#include "vbe.h" 100 101#include "shadow.h" 102 /* vgaHW definitions */ 103#ifdef WITH_VGAHW 104#include "vgaHW.h" 105#endif 106 107#define DPMS_SERVER 108#include <X11/extensions/dpms.h> 109 110#include "atipciids.h" 111#include "radeon_chipset_gen.h" 112 113 114#include "radeon_chipinfo_gen.h" 115 116 /* Forward definitions for driver functions */ 117static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen); 118static Bool RADEONSaveScreen(ScreenPtr pScreen, int mode); 119static void RADEONSave(ScrnInfoPtr pScrn); 120 121static void RADEONSetDynamicClock(ScrnInfoPtr pScrn, int mode); 122static void RADEONForceSomeClocks(ScrnInfoPtr pScrn); 123static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 124 125#ifdef XF86DRI 126static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 127#endif 128 129static const OptionInfoRec RADEONOptions[] = { 130 { OPTION_NOACCEL, "NoAccel", OPTV_BOOLEAN, {0}, FALSE }, 131 { OPTION_SW_CURSOR, "SWcursor", OPTV_BOOLEAN, {0}, FALSE }, 132 { OPTION_DAC_6BIT, "Dac6Bit", OPTV_BOOLEAN, {0}, FALSE }, 133 { OPTION_DAC_8BIT, "Dac8Bit", OPTV_BOOLEAN, {0}, TRUE }, 134#ifdef XF86DRI 135 { OPTION_BUS_TYPE, "BusType", OPTV_ANYSTR, {0}, FALSE }, 136 { OPTION_CP_PIO, "CPPIOMode", OPTV_BOOLEAN, {0}, FALSE }, 137 { OPTION_USEC_TIMEOUT, "CPusecTimeout", OPTV_INTEGER, {0}, FALSE }, 138 { OPTION_AGP_MODE, "AGPMode", OPTV_INTEGER, {0}, FALSE }, 139 { OPTION_AGP_FW, "AGPFastWrite", OPTV_BOOLEAN, {0}, FALSE }, 140 { OPTION_GART_SIZE_OLD, "AGPSize", OPTV_INTEGER, {0}, FALSE }, 141 { OPTION_GART_SIZE, "GARTSize", OPTV_INTEGER, {0}, FALSE }, 142 { OPTION_RING_SIZE, "RingSize", OPTV_INTEGER, {0}, FALSE }, 143 { OPTION_BUFFER_SIZE, "BufferSize", OPTV_INTEGER, {0}, FALSE }, 144 { OPTION_DEPTH_MOVE, "EnableDepthMoves", OPTV_BOOLEAN, {0}, FALSE }, 145 { OPTION_PAGE_FLIP, "EnablePageFlip", OPTV_BOOLEAN, {0}, FALSE }, 146 { OPTION_NO_BACKBUFFER, "NoBackBuffer", OPTV_BOOLEAN, {0}, FALSE }, 147 { OPTION_XV_DMA, "DMAForXv", OPTV_BOOLEAN, {0}, FALSE }, 148 { OPTION_FBTEX_PERCENT, "FBTexPercent", OPTV_INTEGER, {0}, FALSE }, 149 { OPTION_DEPTH_BITS, "DepthBits", OPTV_INTEGER, {0}, FALSE }, 150 { OPTION_PCIAPER_SIZE, "PCIAPERSize", OPTV_INTEGER, {0}, FALSE }, 151#ifdef USE_EXA 152 { OPTION_ACCEL_DFS, "AccelDFS", OPTV_BOOLEAN, {0}, FALSE }, 153#endif 154#endif 155 { OPTION_DDC_MODE, "DDCMode", OPTV_BOOLEAN, {0}, FALSE }, 156 { OPTION_IGNORE_EDID, "IgnoreEDID", OPTV_BOOLEAN, {0}, FALSE }, 157 { OPTION_DISP_PRIORITY, "DisplayPriority", OPTV_ANYSTR, {0}, FALSE }, 158 { OPTION_PANEL_SIZE, "PanelSize", OPTV_ANYSTR, {0}, FALSE }, 159 { OPTION_MIN_DOTCLOCK, "ForceMinDotClock", OPTV_FREQ, {0}, FALSE }, 160 { OPTION_COLOR_TILING, "ColorTiling", OPTV_BOOLEAN, {0}, FALSE }, 161#ifdef XvExtension 162 { OPTION_VIDEO_KEY, "VideoKey", OPTV_INTEGER, {0}, FALSE }, 163 { OPTION_RAGE_THEATRE_CRYSTAL, "RageTheatreCrystal", OPTV_INTEGER, {0}, FALSE }, 164 { OPTION_RAGE_THEATRE_TUNER_PORT, "RageTheatreTunerPort", OPTV_INTEGER, {0}, FALSE }, 165 { OPTION_RAGE_THEATRE_COMPOSITE_PORT, "RageTheatreCompositePort", OPTV_INTEGER, {0}, FALSE }, 166 { OPTION_RAGE_THEATRE_SVIDEO_PORT, "RageTheatreSVideoPort", OPTV_INTEGER, {0}, FALSE }, 167 { OPTION_TUNER_TYPE, "TunerType", OPTV_INTEGER, {0}, FALSE }, 168 { OPTION_RAGE_THEATRE_MICROC_PATH, "RageTheatreMicrocPath", OPTV_STRING, {0}, FALSE }, 169 { OPTION_RAGE_THEATRE_MICROC_TYPE, "RageTheatreMicrocType", OPTV_STRING, {0}, FALSE }, 170 { OPTION_SCALER_WIDTH, "ScalerWidth", OPTV_INTEGER, {0}, FALSE }, 171#endif 172#ifdef RENDER 173 { OPTION_RENDER_ACCEL, "RenderAccel", OPTV_BOOLEAN, {0}, FALSE }, 174 { OPTION_SUBPIXEL_ORDER, "SubPixelOrder", OPTV_ANYSTR, {0}, FALSE }, 175#endif 176 { OPTION_SHOWCACHE, "ShowCache", OPTV_BOOLEAN, {0}, FALSE }, 177 { OPTION_DYNAMIC_CLOCKS, "DynamicClocks", OPTV_BOOLEAN, {0}, FALSE }, 178 { OPTION_VGA_ACCESS, "VGAAccess", OPTV_BOOLEAN, {0}, TRUE }, 179 { OPTION_REVERSE_DDC, "ReverseDDC", OPTV_BOOLEAN, {0}, FALSE }, 180 { OPTION_LVDS_PROBE_PLL, "LVDSProbePLL", OPTV_BOOLEAN, {0}, FALSE }, 181 { OPTION_ACCELMETHOD, "AccelMethod", OPTV_STRING, {0}, FALSE }, 182 { OPTION_DRI, "DRI", OPTV_BOOLEAN, {0}, FALSE }, 183 { OPTION_CONNECTORTABLE, "ConnectorTable", OPTV_STRING, {0}, FALSE }, 184 { OPTION_DEFAULT_CONNECTOR_TABLE, "DefaultConnectorTable", OPTV_BOOLEAN, {0}, FALSE }, 185 { OPTION_DEFAULT_TMDS_PLL, "DefaultTMDSPLL", OPTV_BOOLEAN, {0}, FALSE }, 186#if defined(__powerpc__) 187 { OPTION_MAC_MODEL, "MacModel", OPTV_STRING, {0}, FALSE }, 188#endif 189 { OPTION_TVDAC_LOAD_DETECT, "TVDACLoadDetect", OPTV_BOOLEAN, {0}, FALSE }, 190 { OPTION_FORCE_TVOUT, "ForceTVOut", OPTV_BOOLEAN, {0}, FALSE }, 191 { OPTION_TVSTD, "TVStandard", OPTV_STRING, {0}, FALSE }, 192 { OPTION_IGNORE_LID_STATUS, "IgnoreLidStatus", OPTV_BOOLEAN, {0}, FALSE }, 193 { OPTION_DEFAULT_TVDAC_ADJ, "DefaultTVDACAdj", OPTV_BOOLEAN, {0}, FALSE }, 194 { OPTION_INT10, "Int10", OPTV_BOOLEAN, {0}, FALSE }, 195 { -1, NULL, OPTV_NONE, {0}, FALSE } 196}; 197 198const OptionInfoRec *RADEONOptionsWeak(void) { return RADEONOptions; } 199 200extern _X_EXPORT int gRADEONEntityIndex; 201 202static int getRADEONEntityIndex(void) 203{ 204 return gRADEONEntityIndex; 205} 206 207struct RADEONInt10Save { 208 uint32_t MEM_CNTL; 209 uint32_t MEMSIZE; 210 uint32_t MPP_TB_CONFIG; 211}; 212 213static Bool RADEONMapMMIO(ScrnInfoPtr pScrn); 214static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn); 215 216static void * 217radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode, 218 CARD32 *size, void *closure) 219{ 220 ScrnInfoPtr pScrn = xf86Screens[screen->myNum]; 221 RADEONInfoPtr info = RADEONPTR(pScrn); 222 int stride; 223 224 stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8; 225 *size = stride; 226 227 return ((uint8_t *)info->FB + row * stride + offset); 228} 229static Bool 230RADEONCreateScreenResources (ScreenPtr pScreen) 231{ 232 ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; 233 RADEONInfoPtr info = RADEONPTR(pScrn); 234 PixmapPtr pixmap; 235 236 pScreen->CreateScreenResources = info->CreateScreenResources; 237 if (!(*pScreen->CreateScreenResources)(pScreen)) 238 return FALSE; 239 pScreen->CreateScreenResources = RADEONCreateScreenResources; 240 241 if (info->r600_shadow_fb) { 242 pixmap = pScreen->GetScreenPixmap(pScreen); 243 244 if (!shadowAdd(pScreen, pixmap, shadowUpdatePackedWeak(), 245 radeonShadowWindow, 0, NULL)) 246 return FALSE; 247 } 248 return TRUE; 249} 250 251RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn) 252{ 253 DevUnion *pPriv; 254 RADEONInfoPtr info = RADEONPTR(pScrn); 255 pPriv = xf86GetEntityPrivate(info->pEnt->index, 256 getRADEONEntityIndex()); 257 return pPriv->ptr; 258} 259 260static void 261RADEONPreInt10Save(ScrnInfoPtr pScrn, void **pPtr) 262{ 263 RADEONInfoPtr info = RADEONPTR(pScrn); 264 unsigned char *RADEONMMIO = info->MMIO; 265 uint32_t CardTmp; 266 static struct RADEONInt10Save SaveStruct = { 0, 0, 0 }; 267 268 if (!IS_AVIVO_VARIANT) { 269 /* Save the values and zap MEM_CNTL */ 270 SaveStruct.MEM_CNTL = INREG(RADEON_MEM_CNTL); 271 SaveStruct.MEMSIZE = INREG(RADEON_CONFIG_MEMSIZE); 272 SaveStruct.MPP_TB_CONFIG = INREG(RADEON_MPP_TB_CONFIG); 273 274 /* 275 * Zap MEM_CNTL and set MPP_TB_CONFIG<31:24> to 4 276 */ 277 OUTREG(RADEON_MEM_CNTL, 0); 278 CardTmp = SaveStruct.MPP_TB_CONFIG & 0x00ffffffu; 279 CardTmp |= 0x04 << 24; 280 OUTREG(RADEON_MPP_TB_CONFIG, CardTmp); 281 } 282 283 *pPtr = (void *)&SaveStruct; 284} 285 286static void 287RADEONPostInt10Check(ScrnInfoPtr pScrn, void *ptr) 288{ 289 RADEONInfoPtr info = RADEONPTR(pScrn); 290 unsigned char *RADEONMMIO = info->MMIO; 291 struct RADEONInt10Save *pSave = ptr; 292 uint32_t CardTmp; 293 294 /* If we don't have a valid (non-zero) saved MEM_CNTL, get out now */ 295 if (!pSave || !pSave->MEM_CNTL) 296 return; 297 298 if (IS_AVIVO_VARIANT) 299 return; 300 301 /* 302 * If either MEM_CNTL is currently zero or inconistent (configured for 303 * two channels with the two channels configured differently), restore 304 * the saved registers. 305 */ 306 CardTmp = INREG(RADEON_MEM_CNTL); 307 if (!CardTmp || 308 ((CardTmp & 1) && 309 (((CardTmp >> 8) & 0xff) != ((CardTmp >> 24) & 0xff)))) { 310 /* Restore the saved registers */ 311 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 312 "Restoring MEM_CNTL (%08lx), setting to %08lx\n", 313 (unsigned long)CardTmp, (unsigned long)pSave->MEM_CNTL); 314 OUTREG(RADEON_MEM_CNTL, pSave->MEM_CNTL); 315 316 CardTmp = INREG(RADEON_CONFIG_MEMSIZE); 317 if (CardTmp != pSave->MEMSIZE) { 318 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 319 "Restoring CONFIG_MEMSIZE (%08lx), setting to %08lx\n", 320 (unsigned long)CardTmp, (unsigned long)pSave->MEMSIZE); 321 OUTREG(RADEON_CONFIG_MEMSIZE, pSave->MEMSIZE); 322 } 323 } 324 325 CardTmp = INREG(RADEON_MPP_TB_CONFIG); 326 if ((CardTmp & 0xff000000u) != (pSave->MPP_TB_CONFIG & 0xff000000u)) { 327 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 328 "Restoring MPP_TB_CONFIG<31:24> (%02lx), setting to %02lx\n", 329 (unsigned long)CardTmp >> 24, 330 (unsigned long)pSave->MPP_TB_CONFIG >> 24); 331 CardTmp &= 0x00ffffffu; 332 CardTmp |= (pSave->MPP_TB_CONFIG & 0xff000000u); 333 OUTREG(RADEON_MPP_TB_CONFIG, CardTmp); 334 } 335} 336 337/* Allocate our private RADEONInfoRec */ 338static Bool RADEONGetRec(ScrnInfoPtr pScrn) 339{ 340 if (pScrn->driverPrivate) return TRUE; 341 342 pScrn->driverPrivate = xnfcalloc(sizeof(RADEONInfoRec), 1); 343 return TRUE; 344} 345 346/* Free our private RADEONInfoRec */ 347static void RADEONFreeRec(ScrnInfoPtr pScrn) 348{ 349 if (!pScrn || !pScrn->driverPrivate) return; 350 xfree(pScrn->driverPrivate); 351 pScrn->driverPrivate = NULL; 352} 353 354/* Memory map the MMIO region. Used during pre-init and by RADEONMapMem, 355 * below 356 */ 357static Bool RADEONMapMMIO(ScrnInfoPtr pScrn) 358{ 359 RADEONInfoPtr info = RADEONPTR(pScrn); 360 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 361 362 if (pRADEONEnt->MMIO) { 363 info->MMIO = pRADEONEnt->MMIO; 364 return TRUE; 365 } 366 367#ifndef XSERVER_LIBPCIACCESS 368 369 info->MMIO = xf86MapPciMem(pScrn->scrnIndex, 370 VIDMEM_MMIO | VIDMEM_READSIDEEFFECT, 371 info->PciTag, 372 info->MMIOAddr, 373 info->MMIOSize); 374 375 if (!info->MMIO) return FALSE; 376#else 377 378 void** result = (void**)&info->MMIO; 379 int err = pci_device_map_range(info->PciInfo, 380 info->MMIOAddr, 381 info->MMIOSize, 382 PCI_DEV_MAP_FLAG_WRITABLE, 383 result); 384 385 if (err) { 386 xf86DrvMsg (pScrn->scrnIndex, X_ERROR, 387 "Unable to map MMIO aperture. %s (%d)\n", 388 strerror (err), err); 389 return FALSE; 390 } 391 392#endif 393 394 pRADEONEnt->MMIO = info->MMIO; 395 return TRUE; 396} 397 398/* Unmap the MMIO region. Used during pre-init and by RADEONUnmapMem, 399 * below 400 */ 401static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn) 402{ 403 RADEONInfoPtr info = RADEONPTR(pScrn); 404 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 405 406 if (info->IsPrimary || info->IsSecondary) { 407 /* never unmap on zaphod */ 408 info->MMIO = NULL; 409 return TRUE; 410 } 411 412#ifndef XSERVER_LIBPCIACCESS 413 xf86UnMapVidMem(pScrn->scrnIndex, info->MMIO, info->MMIOSize); 414#else 415 pci_device_unmap_range(info->PciInfo, info->MMIO, info->MMIOSize); 416#endif 417 418 pRADEONEnt->MMIO = NULL; 419 info->MMIO = NULL; 420 return TRUE; 421} 422 423/* Memory map the frame buffer. Used by RADEONMapMem, below. */ 424static Bool RADEONMapFB(ScrnInfoPtr pScrn) 425{ 426#ifdef XSERVER_LIBPCIACCESS 427 int err; 428#endif 429 RADEONInfoPtr info = RADEONPTR(pScrn); 430 431 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 432 "Map: 0x%08lx, 0x%08lx\n", info->LinearAddr, info->FbMapSize); 433 434#ifndef XSERVER_LIBPCIACCESS 435 436 info->FB = xf86MapPciMem(pScrn->scrnIndex, 437 VIDMEM_FRAMEBUFFER, 438 info->PciTag, 439 info->LinearAddr, 440 info->FbMapSize); 441 442 if (!info->FB) return FALSE; 443 444#else 445 446 err = pci_device_map_range(info->PciInfo, 447 info->LinearAddr, 448 info->FbMapSize, 449 PCI_DEV_MAP_FLAG_WRITABLE | 450 PCI_DEV_MAP_FLAG_WRITE_COMBINE, 451 &info->FB); 452 453 if (err) { 454 xf86DrvMsg (pScrn->scrnIndex, X_ERROR, 455 "Unable to map FB aperture. %s (%d)\n", 456 strerror (err), err); 457 return FALSE; 458 } 459 460#endif 461 462 return TRUE; 463} 464 465/* Unmap the frame buffer. Used by RADEONUnmapMem, below. */ 466static Bool RADEONUnmapFB(ScrnInfoPtr pScrn) 467{ 468 RADEONInfoPtr info = RADEONPTR(pScrn); 469 470#ifndef XSERVER_LIBPCIACCESS 471 xf86UnMapVidMem(pScrn->scrnIndex, info->FB, info->FbMapSize); 472#else 473 pci_device_unmap_range(info->PciInfo, info->FB, info->FbMapSize); 474#endif 475 476 info->FB = NULL; 477 return TRUE; 478} 479 480/* Memory map the MMIO region and the frame buffer */ 481static Bool RADEONMapMem(ScrnInfoPtr pScrn) 482{ 483 if (!RADEONMapMMIO(pScrn)) return FALSE; 484 if (!RADEONMapFB(pScrn)) { 485 RADEONUnmapMMIO(pScrn); 486 return FALSE; 487 } 488 return TRUE; 489} 490 491/* Unmap the MMIO region and the frame buffer */ 492static Bool RADEONUnmapMem(ScrnInfoPtr pScrn) 493{ 494 if (!RADEONUnmapMMIO(pScrn) || !RADEONUnmapFB(pScrn)) return FALSE; 495 return TRUE; 496} 497 498void RADEONPllErrataAfterIndex(RADEONInfoPtr info) 499{ 500 unsigned char *RADEONMMIO = info->MMIO; 501 502 if (!(info->ChipErrata & CHIP_ERRATA_PLL_DUMMYREADS)) 503 return; 504 505 /* This workaround is necessary on rv200 and RS200 or PLL 506 * reads may return garbage (among others...) 507 */ 508 (void)INREG(RADEON_CLOCK_CNTL_DATA); 509 (void)INREG(RADEON_CRTC_GEN_CNTL); 510} 511 512void RADEONPllErrataAfterData(RADEONInfoPtr info) 513{ 514 unsigned char *RADEONMMIO = info->MMIO; 515 516 /* This workarounds is necessary on RV100, RS100 and RS200 chips 517 * or the chip could hang on a subsequent access 518 */ 519 if (info->ChipErrata & CHIP_ERRATA_PLL_DELAY) { 520 /* we can't deal with posted writes here ... */ 521 usleep(5000); 522 } 523 524 /* This function is required to workaround a hardware bug in some (all?) 525 * revisions of the R300. This workaround should be called after every 526 * CLOCK_CNTL_INDEX register access. If not, register reads afterward 527 * may not be correct. 528 */ 529 if (info->ChipErrata & CHIP_ERRATA_R300_CG) { 530 uint32_t save, tmp; 531 532 save = INREG(RADEON_CLOCK_CNTL_INDEX); 533 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 534 OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp); 535 tmp = INREG(RADEON_CLOCK_CNTL_DATA); 536 OUTREG(RADEON_CLOCK_CNTL_INDEX, save); 537 } 538} 539 540/* Read PLL register */ 541unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr) 542{ 543 RADEONInfoPtr info = RADEONPTR(pScrn); 544 unsigned char *RADEONMMIO = info->MMIO; 545 uint32_t data; 546 547 OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f); 548 RADEONPllErrataAfterIndex(info); 549 data = INREG(RADEON_CLOCK_CNTL_DATA); 550 RADEONPllErrataAfterData(info); 551 552 return data; 553} 554 555/* Write PLL information */ 556void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, uint32_t data) 557{ 558 RADEONInfoPtr info = RADEONPTR(pScrn); 559 unsigned char *RADEONMMIO = info->MMIO; 560 561 OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) | 562 RADEON_PLL_WR_EN)); 563 RADEONPllErrataAfterIndex(info); 564 OUTREG(RADEON_CLOCK_CNTL_DATA, data); 565 RADEONPllErrataAfterData(info); 566} 567 568/* Read MC register */ 569unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr) 570{ 571 RADEONInfoPtr info = RADEONPTR(pScrn); 572 unsigned char *RADEONMMIO = info->MMIO; 573 uint32_t data; 574 575 if ((info->ChipFamily == CHIP_FAMILY_RS690) || 576 (info->ChipFamily == CHIP_FAMILY_RS740)) { 577 OUTREG(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); 578 data = INREG(RS690_MC_DATA); 579 } else if (info->ChipFamily == CHIP_FAMILY_RS600) { 580 OUTREG(RS600_MC_INDEX, (addr & RS600_MC_INDEX_MASK)); 581 data = INREG(RS600_MC_DATA); 582 } else if (IS_AVIVO_VARIANT) { 583 OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000); 584 (void)INREG(AVIVO_MC_INDEX); 585 data = INREG(AVIVO_MC_DATA); 586 587 OUTREG(AVIVO_MC_INDEX, 0); 588 (void)INREG(AVIVO_MC_INDEX); 589 } else { 590 OUTREG(R300_MC_IND_INDEX, addr & 0x3f); 591 (void)INREG(R300_MC_IND_INDEX); 592 data = INREG(R300_MC_IND_DATA); 593 594 OUTREG(R300_MC_IND_INDEX, 0); 595 (void)INREG(R300_MC_IND_INDEX); 596 } 597 598 return data; 599} 600 601/* Write MC information */ 602void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, uint32_t data) 603{ 604 RADEONInfoPtr info = RADEONPTR(pScrn); 605 unsigned char *RADEONMMIO = info->MMIO; 606 607 if ((info->ChipFamily == CHIP_FAMILY_RS690) || 608 (info->ChipFamily == CHIP_FAMILY_RS740)) { 609 OUTREG(RS690_MC_INDEX, ((addr & RS690_MC_INDEX_MASK) | 610 RS690_MC_INDEX_WR_EN)); 611 OUTREG(RS690_MC_DATA, data); 612 OUTREG(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); 613 } else if (info->ChipFamily == CHIP_FAMILY_RS600) { 614 OUTREG(RS600_MC_INDEX, ((addr & RS600_MC_INDEX_MASK) | 615 RS600_MC_INDEX_WR_EN)); 616 OUTREG(RS600_MC_DATA, data); 617 OUTREG(RS600_MC_INDEX, RS600_MC_INDEX_WR_ACK); 618 } else if (IS_AVIVO_VARIANT) { 619 OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0xff0000); 620 (void)INREG(AVIVO_MC_INDEX); 621 OUTREG(AVIVO_MC_DATA, data); 622 OUTREG(AVIVO_MC_INDEX, 0); 623 (void)INREG(AVIVO_MC_INDEX); 624 } else { 625 OUTREG(R300_MC_IND_INDEX, (((addr) & 0x3f) | 626 R300_MC_IND_WR_EN)); 627 (void)INREG(R300_MC_IND_INDEX); 628 OUTREG(R300_MC_IND_DATA, data); 629 OUTREG(R300_MC_IND_INDEX, 0); 630 (void)INREG(R300_MC_IND_INDEX); 631 } 632} 633 634static Bool avivo_get_mc_idle(ScrnInfoPtr pScrn) 635{ 636 RADEONInfoPtr info = RADEONPTR(pScrn); 637 638 if (info->ChipFamily >= CHIP_FAMILY_R600) { 639 /* no idea where this is on r600 yet */ 640 return TRUE; 641 } else if (info->ChipFamily == CHIP_FAMILY_RV515) { 642 if (INMC(pScrn, RV515_MC_STATUS) & RV515_MC_STATUS_IDLE) 643 return TRUE; 644 else 645 return FALSE; 646 } else if (info->ChipFamily == CHIP_FAMILY_RS600) { 647 if (INMC(pScrn, RS600_MC_STATUS) & RS600_MC_STATUS_IDLE) 648 return TRUE; 649 else 650 return FALSE; 651 } else if ((info->ChipFamily == CHIP_FAMILY_RS690) || 652 (info->ChipFamily == CHIP_FAMILY_RS740)) { 653 if (INMC(pScrn, RS690_MC_STATUS) & RS690_MC_STATUS_IDLE) 654 return TRUE; 655 else 656 return FALSE; 657 } else { 658 if (INMC(pScrn, R520_MC_STATUS) & R520_MC_STATUS_IDLE) 659 return TRUE; 660 else 661 return FALSE; 662 } 663} 664 665#define LOC_FB 0x1 666#define LOC_AGP 0x2 667static void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, uint32_t fb_loc, uint32_t agp_loc, uint32_t agp_loc_hi) 668{ 669 RADEONInfoPtr info = RADEONPTR(pScrn); 670 unsigned char *RADEONMMIO = info->MMIO; 671 672 if (info->ChipFamily >= CHIP_FAMILY_R600) { 673 if (mask & LOC_FB) 674 OUTREG(R600_MC_VM_FB_LOCATION, fb_loc); 675 if (mask & LOC_AGP) { 676 OUTREG(R600_MC_VM_AGP_BOT, agp_loc); 677 OUTREG(R600_MC_VM_AGP_TOP, agp_loc_hi); 678 } 679 } else if (info->ChipFamily == CHIP_FAMILY_RV515) { 680 if (mask & LOC_FB) 681 OUTMC(pScrn, RV515_MC_FB_LOCATION, fb_loc); 682 if (mask & LOC_AGP) 683 OUTMC(pScrn, RV515_MC_AGP_LOCATION, agp_loc); 684 (void)INMC(pScrn, RV515_MC_AGP_LOCATION); 685 } else if (info->ChipFamily == CHIP_FAMILY_RS600) { 686 if (mask & LOC_FB) 687 OUTMC(pScrn, RS600_MC_FB_LOCATION, fb_loc); 688 /* if (mask & LOC_AGP) 689 OUTMC(pScrn, RS600_MC_AGP_LOCATION, agp_loc);*/ 690 } else if ((info->ChipFamily == CHIP_FAMILY_RS690) || 691 (info->ChipFamily == CHIP_FAMILY_RS740)) { 692 if (mask & LOC_FB) 693 OUTMC(pScrn, RS690_MC_FB_LOCATION, fb_loc); 694 if (mask & LOC_AGP) 695 OUTMC(pScrn, RS690_MC_AGP_LOCATION, agp_loc); 696 } else if (info->ChipFamily >= CHIP_FAMILY_R520) { 697 if (mask & LOC_FB) 698 OUTMC(pScrn, R520_MC_FB_LOCATION, fb_loc); 699 if (mask & LOC_AGP) 700 OUTMC(pScrn, R520_MC_AGP_LOCATION, agp_loc); 701 (void)INMC(pScrn, R520_MC_FB_LOCATION); 702 } else { 703 if (mask & LOC_FB) 704 OUTREG(RADEON_MC_FB_LOCATION, fb_loc); 705 if (mask & LOC_AGP) 706 OUTREG(RADEON_MC_AGP_LOCATION, agp_loc); 707 } 708} 709 710static void radeon_read_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, uint32_t *fb_loc, uint32_t *agp_loc, uint32_t *agp_loc_hi) 711{ 712 RADEONInfoPtr info = RADEONPTR(pScrn); 713 unsigned char *RADEONMMIO = info->MMIO; 714 715 if (info->ChipFamily >= CHIP_FAMILY_R600) { 716 if (mask & LOC_FB) 717 *fb_loc = INREG(R600_MC_VM_FB_LOCATION); 718 if (mask & LOC_AGP) { 719 *agp_loc = INREG(R600_MC_VM_AGP_BOT); 720 *agp_loc_hi = INREG(R600_MC_VM_AGP_TOP); 721 } 722 } else if (info->ChipFamily == CHIP_FAMILY_RV515) { 723 if (mask & LOC_FB) 724 *fb_loc = INMC(pScrn, RV515_MC_FB_LOCATION); 725 if (mask & LOC_AGP) { 726 *agp_loc = INMC(pScrn, RV515_MC_AGP_LOCATION); 727 *agp_loc_hi = 0; 728 } 729 } else if (info->ChipFamily == CHIP_FAMILY_RS600) { 730 if (mask & LOC_FB) 731 *fb_loc = INMC(pScrn, RS600_MC_FB_LOCATION); 732 if (mask & LOC_AGP) { 733 *agp_loc = 0;//INMC(pScrn, RS600_MC_AGP_LOCATION); 734 *agp_loc_hi = 0; 735 } 736 } else if ((info->ChipFamily == CHIP_FAMILY_RS690) || 737 (info->ChipFamily == CHIP_FAMILY_RS740)) { 738 if (mask & LOC_FB) 739 *fb_loc = INMC(pScrn, RS690_MC_FB_LOCATION); 740 if (mask & LOC_AGP) { 741 *agp_loc = INMC(pScrn, RS690_MC_AGP_LOCATION); 742 *agp_loc_hi = 0; 743 } 744 } else if (info->ChipFamily >= CHIP_FAMILY_R520) { 745 if (mask & LOC_FB) 746 *fb_loc = INMC(pScrn, R520_MC_FB_LOCATION); 747 if (mask & LOC_AGP) { 748 *agp_loc = INMC(pScrn, R520_MC_AGP_LOCATION); 749 *agp_loc_hi = 0; 750 } 751 } else { 752 if (mask & LOC_FB) 753 *fb_loc = INREG(RADEON_MC_FB_LOCATION); 754 if (mask & LOC_AGP) 755 *agp_loc = INREG(RADEON_MC_AGP_LOCATION); 756 } 757} 758 759#if 0 760/* Read PAL information (only used for debugging) */ 761static int RADEONINPAL(int idx) 762{ 763 RADEONInfoPtr info = RADEONPTR(pScrn); 764 unsigned char *RADEONMMIO = info->MMIO; 765 766 OUTREG(RADEON_PALETTE_INDEX, idx << 16); 767 return INREG(RADEON_PALETTE_DATA); 768} 769#endif 770 771/* Wait for vertical sync on primary CRTC */ 772void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn) 773{ 774 RADEONInfoPtr info = RADEONPTR(pScrn); 775 unsigned char *RADEONMMIO = info->MMIO; 776 uint32_t crtc_gen_cntl; 777 struct timeval timeout; 778 779 crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); 780 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) || 781 !(crtc_gen_cntl & RADEON_CRTC_EN)) 782 return; 783 784 /* Clear the CRTC_VBLANK_SAVE bit */ 785 OUTREG(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR); 786 787 /* Wait for it to go back up */ 788 radeon_init_timeout(&timeout, RADEON_VSYNC_TIMEOUT); 789 while (!(INREG(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_SAVE) && 790 !radeon_timedout(&timeout)) 791 usleep(100); 792} 793 794/* Wait for vertical sync on secondary CRTC */ 795void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn) 796{ 797 RADEONInfoPtr info = RADEONPTR(pScrn); 798 unsigned char *RADEONMMIO = info->MMIO; 799 uint32_t crtc2_gen_cntl; 800 struct timeval timeout; 801 802 crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); 803 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) || 804 !(crtc2_gen_cntl & RADEON_CRTC2_EN)) 805 return; 806 807 /* Clear the CRTC2_VBLANK_SAVE bit */ 808 OUTREG(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR); 809 810 /* Wait for it to go back up */ 811 radeon_init_timeout(&timeout, RADEON_VSYNC_TIMEOUT); 812 while (!(INREG(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_SAVE) && 813 !radeon_timedout(&timeout)) 814 usleep(100); 815} 816 817 818/* Compute log base 2 of val */ 819int RADEONMinBits(int val) 820{ 821 int bits; 822 823 if (!val) return 1; 824 for (bits = 0; val; val >>= 1, ++bits); 825 return bits; 826} 827 828/* Compute n/d with rounding */ 829static int RADEONDiv(int n, int d) 830{ 831 return (n + (d / 2)) / d; 832} 833 834static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn) 835{ 836 RADEONInfoPtr info = RADEONPTR(pScrn); 837 RADEONPLLPtr pll = &info->pll; 838 unsigned char *RADEONMMIO = info->MMIO; 839 unsigned char ppll_div_sel; 840 unsigned mpll_fb_div, spll_fb_div, M; 841 unsigned xclk, tmp, ref_div; 842 int hTotal, vTotal, num, denom, m, n; 843 float hz, prev_xtal, vclk, xtal, mpll, spll; 844 long total_usecs; 845 struct timeval start, stop, to1, to2; 846 unsigned int f1, f2, f3; 847 int tries = 0; 848 849 prev_xtal = 0; 850 again: 851 xtal = 0; 852 if (++tries > 10) 853 goto failed; 854 855 gettimeofday(&to1, NULL); 856 f1 = INREG(RADEON_CRTC_CRNT_FRAME); 857 for (;;) { 858 f2 = INREG(RADEON_CRTC_CRNT_FRAME); 859 if (f1 != f2) 860 break; 861 gettimeofday(&to2, NULL); 862 if ((to2.tv_sec - to1.tv_sec) > 1) { 863 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Clock not counting...\n"); 864 goto failed; 865 } 866 } 867 gettimeofday(&start, NULL); 868 for(;;) { 869 f3 = INREG(RADEON_CRTC_CRNT_FRAME); 870 if (f3 != f2) 871 break; 872 gettimeofday(&to2, NULL); 873 if ((to2.tv_sec - start.tv_sec) > 1) 874 goto failed; 875 } 876 gettimeofday(&stop, NULL); 877 878 if ((stop.tv_sec - start.tv_sec) != 0) 879 goto again; 880 total_usecs = abs(stop.tv_usec - start.tv_usec); 881 if (total_usecs == 0) 882 goto again; 883 hz = 1000000.0/(float)total_usecs; 884 885 hTotal = ((INREG(RADEON_CRTC_H_TOTAL_DISP) & 0x3ff) + 1) * 8; 886 vTotal = ((INREG(RADEON_CRTC_V_TOTAL_DISP) & 0xfff) + 1); 887 vclk = (float)(hTotal * (float)(vTotal * hz)); 888 889 switch((INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x30000) >> 16) { 890 case 0: 891 default: 892 num = 1; 893 denom = 1; 894 break; 895 case 1: 896 n = ((INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) >> 16) & 0xff); 897 m = (INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) & 0xff); 898 num = 2*n; 899 denom = 2*m; 900 break; 901 case 2: 902 n = ((INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) >> 8) & 0xff); 903 m = (INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) & 0xff); 904 num = 2*n; 905 denom = 2*m; 906 break; 907 } 908 909 ppll_div_sel = INREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; 910 RADEONPllErrataAfterIndex(info); 911 912 n = (INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel) & 0x7ff); 913 m = (INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x3ff); 914 915 num *= n; 916 denom *= m; 917 918 switch ((INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) { 919 case 1: 920 denom *= 2; 921 break; 922 case 2: 923 denom *= 4; 924 break; 925 case 3: 926 denom *= 8; 927 break; 928 case 4: 929 denom *= 3; 930 break; 931 case 6: 932 denom *= 6; 933 break; 934 case 7: 935 denom *= 12; 936 break; 937 } 938 939 xtal = (int)(vclk *(float)denom/(float)num); 940 941 if ((xtal > 26900000) && (xtal < 27100000)) 942 xtal = 2700; 943 else if ((xtal > 14200000) && (xtal < 14400000)) 944 xtal = 1432; 945 else if ((xtal > 29400000) && (xtal < 29600000)) 946 xtal = 2950; 947 else 948 goto again; 949 failed: 950 if (xtal == 0) { 951 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Failed to probe xtal value ! " 952 "Using default 27Mhz\n"); 953 xtal = 2700; 954 } else { 955 if (prev_xtal == 0) { 956 prev_xtal = xtal; 957 tries = 0; 958 goto again; 959 } else if (prev_xtal != xtal) { 960 prev_xtal = 0; 961 goto again; 962 } 963 } 964 965 tmp = INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV); 966 ref_div = INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x3ff; 967 968 /* Some sanity check based on the BIOS code .... */ 969 if (ref_div < 2) { 970 uint32_t tmp; 971 tmp = INPLL(pScrn, RADEON_PPLL_REF_DIV); 972 if (IS_R300_VARIANT 973 || (info->ChipFamily == CHIP_FAMILY_RS300) 974 || (info->ChipFamily == CHIP_FAMILY_RS400) 975 || (info->ChipFamily == CHIP_FAMILY_RS480)) 976 ref_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> 977 R300_PPLL_REF_DIV_ACC_SHIFT; 978 else 979 ref_div = tmp & RADEON_PPLL_REF_DIV_MASK; 980 if (ref_div < 2) 981 ref_div = 12; 982 } 983 984 /* Calculate "base" xclk straight from MPLL, though that isn't 985 * really useful (hopefully). This isn't called XCLK anymore on 986 * radeon's... 987 */ 988 mpll_fb_div = (tmp & 0xff00) >> 8; 989 spll_fb_div = (tmp & 0xff0000) >> 16; 990 M = (tmp & 0xff); 991 xclk = RADEONDiv((2 * mpll_fb_div * xtal), (M)); 992 993 /* 994 * Calculate MCLK based on MCLK-A 995 */ 996 mpll = (2.0 * (float)mpll_fb_div * (xtal / 100.0)) / (float)M; 997 spll = (2.0 * (float)spll_fb_div * (xtal / 100.0)) / (float)M; 998 999 tmp = INPLL(pScrn, RADEON_MCLK_CNTL) & 0x7; 1000 switch(tmp) { 1001 case 1: info->mclk = mpll; break; 1002 case 2: info->mclk = mpll / 2.0; break; 1003 case 3: info->mclk = mpll / 4.0; break; 1004 case 4: info->mclk = mpll / 8.0; break; 1005 case 7: info->mclk = spll; break; 1006 default: 1007 info->mclk = 200.00; 1008 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unsupported MCLKA source" 1009 " setting %d, can't probe MCLK value !\n", tmp); 1010 } 1011 1012 /* 1013 * Calculate SCLK 1014 */ 1015 tmp = INPLL(pScrn, RADEON_SCLK_CNTL) & 0x7; 1016 switch(tmp) { 1017 case 1: info->sclk = spll; break; 1018 case 2: info->sclk = spll / 2.0; break; 1019 case 3: info->sclk = spll / 4.0; break; 1020 case 4: info->sclk = spll / 8.0; break; 1021 case 7: info->sclk = mpll; break; 1022 default: 1023 info->sclk = 200.00; 1024 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unsupported SCLK source" 1025 " setting %d, can't probe SCLK value !\n", tmp); 1026 } 1027 1028 /* we're done, hopefully these are sane values */ 1029 pll->reference_div = ref_div; 1030 pll->xclk = xclk; 1031 pll->reference_freq = xtal; 1032 1033 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Probed PLL values: xtal: %f Mhz, " 1034 "sclk: %f Mhz, mclk: %f Mhz\n", xtal/100.0, info->sclk, info->mclk); 1035 1036 return TRUE; 1037} 1038 1039static void RADEONGetClockInfo(ScrnInfoPtr pScrn) 1040{ 1041 RADEONInfoPtr info = RADEONPTR (pScrn); 1042 RADEONPLLPtr pll = &info->pll; 1043 double min_dotclock; 1044 1045 if (RADEONGetClockInfoFromBIOS(pScrn)) { 1046 if (pll->reference_div < 2) { 1047 /* retrive it from register setting for fitting into current PLL algorithm. 1048 We'll probably need a new routine to calculate the best ref_div from BIOS 1049 provided min_input_pll and max_input_pll 1050 */ 1051 uint32_t tmp; 1052 tmp = INPLL(pScrn, RADEON_PPLL_REF_DIV); 1053 if (IS_R300_VARIANT || 1054 (info->ChipFamily == CHIP_FAMILY_RS300) || 1055 (info->ChipFamily == CHIP_FAMILY_RS400) || 1056 (info->ChipFamily == CHIP_FAMILY_RS480)) { 1057 pll->reference_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT; 1058 } else { 1059 pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; 1060 } 1061 1062 if (pll->reference_div < 2) pll->reference_div = 12; 1063 } 1064 } else { 1065 xf86DrvMsg (pScrn->scrnIndex, X_WARNING, 1066 "Video BIOS not detected, using default clock settings!\n"); 1067 1068 /* Default min/max PLL values */ 1069 if (info->ChipFamily == CHIP_FAMILY_R420 || info->ChipFamily == CHIP_FAMILY_RV410) { 1070 pll->pll_in_min = 100; 1071 pll->pll_in_max = 1350; 1072 pll->pll_out_min = 20000; 1073 pll->pll_out_max = 50000; 1074 } else { 1075 pll->pll_in_min = 40; 1076 pll->pll_in_max = 500; 1077 pll->pll_out_min = 12500; 1078 pll->pll_out_max = 35000; 1079 } 1080 1081 if (!RADEONProbePLLParameters(pScrn)) { 1082 if (info->IsIGP) 1083 pll->reference_freq = 1432; 1084 else 1085 pll->reference_freq = 2700; 1086 1087 pll->reference_div = 12; 1088 pll->xclk = 10300; 1089 1090 info->sclk = 200.00; 1091 info->mclk = 200.00; 1092 } 1093 } 1094 1095 /* card limits for computing PLLs */ 1096 if (IS_AVIVO_VARIANT) { 1097 pll->min_post_div = 2; 1098 pll->max_post_div = 0x7f; 1099 } else { 1100 pll->min_post_div = 1; 1101 pll->max_post_div = 12; //16 on crtc0 1102 } 1103 pll->min_ref_div = 2; 1104 pll->max_ref_div = 0x3ff; 1105 pll->min_feedback_div = 4; 1106 pll->max_feedback_div = 0x7ff; 1107 pll->best_vco = 0; 1108 1109 xf86DrvMsg (pScrn->scrnIndex, X_INFO, 1110 "PLL parameters: rf=%u rd=%u min=%u max=%u; xclk=%u\n", 1111 pll->reference_freq, 1112 pll->reference_div, 1113 (unsigned)pll->pll_out_min, (unsigned)pll->pll_out_max, 1114 pll->xclk); 1115 1116 /* (Some?) Radeon BIOSes seem too lie about their minimum dot 1117 * clocks. Allow users to override the detected minimum dot clock 1118 * value (e.g., and allow it to be suitable for TV sets). 1119 */ 1120 if (xf86GetOptValFreq(info->Options, OPTION_MIN_DOTCLOCK, 1121 OPTUNITS_MHZ, &min_dotclock)) { 1122 if (min_dotclock < 12 || min_dotclock*100 >= pll->pll_out_max) { 1123 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1124 "Illegal minimum dotclock specified %.2f MHz " 1125 "(option ignored)\n", 1126 min_dotclock); 1127 } else { 1128 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1129 "Forced minimum dotclock to %.2f MHz " 1130 "(instead of detected %.2f MHz)\n", 1131 min_dotclock, ((double)pll->pll_out_min/1000)); 1132 pll->pll_out_min = min_dotclock * 1000; 1133 } 1134 } 1135} 1136 1137 1138 1139/* This is called by RADEONPreInit to set up the default visual */ 1140static Bool RADEONPreInitVisual(ScrnInfoPtr pScrn) 1141{ 1142 RADEONInfoPtr info = RADEONPTR(pScrn); 1143 1144 if (!xf86SetDepthBpp(pScrn, 0, 0, 0, Support32bppFb)) 1145 return FALSE; 1146 1147 switch (pScrn->depth) { 1148 case 8: 1149 case 15: 1150 case 16: 1151 case 24: 1152 break; 1153 1154 default: 1155 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1156 "Given depth (%d) is not supported by %s driver\n", 1157 pScrn->depth, RADEON_DRIVER_NAME); 1158 return FALSE; 1159 } 1160 1161 xf86PrintDepthBpp(pScrn); 1162 1163 info->fifo_slots = 0; 1164 info->pix24bpp = xf86GetBppFromDepth(pScrn, 1165 pScrn->depth); 1166 info->CurrentLayout.bitsPerPixel = pScrn->bitsPerPixel; 1167 info->CurrentLayout.depth = pScrn->depth; 1168 info->CurrentLayout.pixel_bytes = pScrn->bitsPerPixel / 8; 1169 info->CurrentLayout.pixel_code = (pScrn->bitsPerPixel != 16 1170 ? pScrn->bitsPerPixel 1171 : pScrn->depth); 1172 1173 if (info->pix24bpp == 24) { 1174 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1175 "Radeon does NOT support 24bpp\n"); 1176 return FALSE; 1177 } 1178 1179 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1180 "Pixel depth = %d bits stored in %d byte%s (%d bpp pixmaps)\n", 1181 pScrn->depth, 1182 info->CurrentLayout.pixel_bytes, 1183 info->CurrentLayout.pixel_bytes > 1 ? "s" : "", 1184 info->pix24bpp); 1185 1186 if (!xf86SetDefaultVisual(pScrn, -1)) return FALSE; 1187 1188 if (pScrn->depth > 8 && pScrn->defaultVisual != TrueColor) { 1189 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1190 "Default visual (%s) is not supported at depth %d\n", 1191 xf86GetVisualName(pScrn->defaultVisual), pScrn->depth); 1192 return FALSE; 1193 } 1194 return TRUE; 1195} 1196 1197/* This is called by RADEONPreInit to handle all color weight issues */ 1198static Bool RADEONPreInitWeight(ScrnInfoPtr pScrn) 1199{ 1200 RADEONInfoPtr info = RADEONPTR(pScrn); 1201 1202 /* Save flag for 6 bit DAC to use for 1203 setting CRTC registers. Otherwise use 1204 an 8 bit DAC, even if xf86SetWeight sets 1205 pScrn->rgbBits to some value other than 1206 8. */ 1207 info->dac6bits = FALSE; 1208 1209 if (pScrn->depth > 8) { 1210 rgb defaultWeight = { 0, 0, 0 }; 1211 1212 if (!xf86SetWeight(pScrn, defaultWeight, defaultWeight)) return FALSE; 1213 } else { 1214 pScrn->rgbBits = 8; 1215 if (xf86ReturnOptValBool(info->Options, OPTION_DAC_6BIT, FALSE)) { 1216 pScrn->rgbBits = 6; 1217 info->dac6bits = TRUE; 1218 } 1219 } 1220 1221 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1222 "Using %d bits per RGB (%d bit DAC)\n", 1223 pScrn->rgbBits, info->dac6bits ? 6 : 8); 1224 1225 return TRUE; 1226} 1227 1228void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, 1229 RADEONInfoPtr info) 1230{ 1231 save->mc_fb_location = info->mc_fb_location; 1232 save->mc_agp_location = info->mc_agp_location; 1233 1234 if (IS_AVIVO_VARIANT) { 1235 save->mc_agp_location_hi = info->mc_agp_location_hi; 1236 } else { 1237 save->display_base_addr = info->fbLocation; 1238 save->display2_base_addr = info->fbLocation; 1239 save->ov0_base_addr = info->fbLocation; 1240 } 1241} 1242 1243static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) 1244{ 1245 RADEONInfoPtr info = RADEONPTR(pScrn); 1246 unsigned char *RADEONMMIO = info->MMIO; 1247 uint32_t mem_size; 1248 uint32_t aper_size; 1249 1250 radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &info->mc_fb_location, 1251 &info->mc_agp_location, &info->mc_agp_location_hi); 1252 1253 /* We shouldn't use info->videoRam here which might have been clipped 1254 * but the real video RAM instead 1255 */ 1256 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1257 mem_size = INREG(R600_CONFIG_MEMSIZE); 1258 aper_size = INREG(R600_CONFIG_APER_SIZE); 1259 } else { 1260 mem_size = INREG(RADEON_CONFIG_MEMSIZE); 1261 aper_size = INREG(RADEON_CONFIG_APER_SIZE); 1262 } 1263 1264 if (mem_size == 0) 1265 mem_size = 0x800000; 1266 1267 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 1268 Novell bug 204882 + along with lots of ubuntu ones */ 1269 if (aper_size > mem_size) 1270 mem_size = aper_size; 1271 1272#ifdef XF86DRI 1273 /* Apply memory map limitation if using an old DRI */ 1274 if (info->directRenderingEnabled && !info->newMemoryMap) { 1275 if (aper_size < mem_size) 1276 mem_size = aper_size; 1277 } 1278#endif 1279 1280 if ((info->ChipFamily != CHIP_FAMILY_RS600) && 1281 (info->ChipFamily != CHIP_FAMILY_RS690) && 1282 (info->ChipFamily != CHIP_FAMILY_RS740)) { 1283 if (info->IsIGP) 1284 info->mc_fb_location = INREG(RADEON_NB_TOM); 1285 else 1286#ifdef XF86DRI 1287 /* Old DRI has restrictions on the memory map */ 1288 if ( info->directRenderingEnabled && 1289 info->pKernelDRMVersion->version_minor < 10 ) 1290 info->mc_fb_location = (mem_size - 1) & 0xffff0000U; 1291 else 1292#endif 1293 { 1294 uint32_t aper0_base; 1295 1296 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1297 aper0_base = INREG(R600_CONFIG_F0_BASE); 1298 } else { 1299 aper0_base = INREG(RADEON_CONFIG_APER_0_BASE); 1300 } 1301 1302 /* Recent chips have an "issue" with the memory controller, the 1303 * location must be aligned to the size. We just align it down, 1304 * too bad if we walk over the top of system memory, we don't 1305 * use DMA without a remapped anyway. 1306 * Affected chips are rv280, all r3xx, and all r4xx, but not IGP 1307 */ 1308 if (info->ChipFamily == CHIP_FAMILY_RV280 || 1309 info->ChipFamily == CHIP_FAMILY_R300 || 1310 info->ChipFamily == CHIP_FAMILY_R350 || 1311 info->ChipFamily == CHIP_FAMILY_RV350 || 1312 info->ChipFamily == CHIP_FAMILY_RV380 || 1313 info->ChipFamily == CHIP_FAMILY_R420 || 1314 info->ChipFamily == CHIP_FAMILY_RV410) 1315 aper0_base &= ~(mem_size - 1); 1316 1317 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1318 info->mc_fb_location = (aper0_base >> 24) | 1319 (((aper0_base + mem_size - 1) & 0xff000000U) >> 8); 1320 ErrorF("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location); 1321 } else { 1322 info->mc_fb_location = (aper0_base >> 16) | 1323 ((aper0_base + mem_size - 1) & 0xffff0000U); 1324 } 1325 } 1326 } 1327 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1328 info->fbLocation = (info->mc_fb_location & 0xffff) << 24; 1329 } else { 1330 info->fbLocation = (info->mc_fb_location & 0xffff) << 16; 1331 } 1332 /* Just disable the damn AGP apertures for now, it may be 1333 * re-enabled later by the DRM 1334 */ 1335 1336 if (IS_AVIVO_VARIANT) { 1337 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1338 OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) & 0xff0000); 1339 } else { 1340 OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location); 1341 } 1342 info->mc_agp_location = 0x003f0000; 1343 } else 1344 info->mc_agp_location = 0xffffffc0; 1345 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1346 "RADEONInitMemoryMap() : \n"); 1347 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1348 " mem_size : 0x%08x\n", (unsigned)mem_size); 1349 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1350 " MC_FB_LOCATION : 0x%08x\n", (unsigned)info->mc_fb_location); 1351 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1352 " MC_AGP_LOCATION : 0x%08x\n", 1353 (unsigned)info->mc_agp_location); 1354} 1355 1356static void RADEONGetVRamType(ScrnInfoPtr pScrn) 1357{ 1358 RADEONInfoPtr info = RADEONPTR(pScrn); 1359 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1360 unsigned char *RADEONMMIO = info->MMIO; 1361 uint32_t tmp; 1362 1363 if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300)) 1364 info->IsDDR = TRUE; 1365 else if (INREG(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) 1366 info->IsDDR = TRUE; 1367 else 1368 info->IsDDR = FALSE; 1369 1370 if ((info->ChipFamily >= CHIP_FAMILY_R600) && 1371 (info->ChipFamily <= CHIP_FAMILY_RV635)) { 1372 int chansize; 1373 /* r6xx */ 1374 tmp = INREG(R600_RAMCFG); 1375 if (tmp & R600_CHANSIZE_OVERRIDE) 1376 chansize = 16; 1377 else if (tmp & R600_CHANSIZE) 1378 chansize = 64; 1379 else 1380 chansize = 32; 1381 if (info->ChipFamily == CHIP_FAMILY_R600) 1382 info->RamWidth = 8 * chansize; 1383 else if (info->ChipFamily == CHIP_FAMILY_RV670) 1384 info->RamWidth = 4 * chansize; 1385 else if ((info->ChipFamily == CHIP_FAMILY_RV610) || 1386 (info->ChipFamily == CHIP_FAMILY_RV620)) 1387 info->RamWidth = chansize; 1388 else if ((info->ChipFamily == CHIP_FAMILY_RV630) || 1389 (info->ChipFamily == CHIP_FAMILY_RV635)) 1390 info->RamWidth = 2 * chansize; 1391 } else if (info->ChipFamily == CHIP_FAMILY_RV515) { 1392 /* rv515/rv550 */ 1393 tmp = INMC(pScrn, RV515_MC_CNTL); 1394 tmp &= RV515_MEM_NUM_CHANNELS_MASK; 1395 switch (tmp) { 1396 case 0: info->RamWidth = 64; break; 1397 case 1: info->RamWidth = 128; break; 1398 default: info->RamWidth = 128; break; 1399 } 1400 } else if ((info->ChipFamily >= CHIP_FAMILY_R520) && 1401 (info->ChipFamily <= CHIP_FAMILY_RV570)){ 1402 /* r520/rv530/rv560/rv570/r580 */ 1403 tmp = INMC(pScrn, R520_MC_CNTL0); 1404 switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) { 1405 case 0: info->RamWidth = 32; break; 1406 case 1: info->RamWidth = 64; break; 1407 case 2: info->RamWidth = 128; break; 1408 case 3: info->RamWidth = 256; break; 1409 default: info->RamWidth = 64; break; 1410 } 1411 if (tmp & R520_MC_CHANNEL_SIZE) { 1412 info->RamWidth *= 2; 1413 } 1414 } else if ((info->ChipFamily >= CHIP_FAMILY_R300) && 1415 (info->ChipFamily <= CHIP_FAMILY_RV410)) { 1416 /* r3xx, r4xx */ 1417 tmp = INREG(RADEON_MEM_CNTL); 1418 tmp &= R300_MEM_NUM_CHANNELS_MASK; 1419 switch (tmp) { 1420 case 0: info->RamWidth = 64; break; 1421 case 1: info->RamWidth = 128; break; 1422 case 2: info->RamWidth = 256; break; 1423 default: info->RamWidth = 128; break; 1424 } 1425 } else if ((info->ChipFamily == CHIP_FAMILY_RV100) || 1426 (info->ChipFamily == CHIP_FAMILY_RS100) || 1427 (info->ChipFamily == CHIP_FAMILY_RS200)){ 1428 tmp = INREG(RADEON_MEM_CNTL); 1429 if (tmp & RV100_HALF_MODE) 1430 info->RamWidth = 32; 1431 else 1432 info->RamWidth = 64; 1433 1434 if (!pRADEONEnt->HasCRTC2) { 1435 info->RamWidth /= 4; 1436 info->IsDDR = TRUE; 1437 } 1438 } else if (info->ChipFamily <= CHIP_FAMILY_RV280) { 1439 tmp = INREG(RADEON_MEM_CNTL); 1440 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) 1441 info->RamWidth = 128; 1442 else 1443 info->RamWidth = 64; 1444 } else { 1445 /* newer IGPs */ 1446 info->RamWidth = 128; 1447 } 1448 1449 /* This may not be correct, as some cards can have half of channel disabled 1450 * ToDo: identify these cases 1451 */ 1452} 1453 1454/* 1455 * Depending on card genertation, chipset bugs, etc... the amount of vram 1456 * accessible to the CPU can vary. This function is our best shot at figuring 1457 * it out. Returns a value in KB. 1458 */ 1459static uint32_t RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn) 1460{ 1461 RADEONInfoPtr info = RADEONPTR(pScrn); 1462 unsigned char *RADEONMMIO = info->MMIO; 1463 uint32_t aper_size; 1464 unsigned char byte; 1465 1466 if (info->ChipFamily >= CHIP_FAMILY_R600) 1467 aper_size = INREG(R600_CONFIG_APER_SIZE) / 1024; 1468 else 1469 aper_size = INREG(RADEON_CONFIG_APER_SIZE) / 1024; 1470 1471#ifdef XF86DRI 1472 /* If we use the DRI, we need to check if it's a version that has the 1473 * bug of always cropping MC_FB_LOCATION to one aperture, in which case 1474 * we need to limit the amount of accessible video memory 1475 */ 1476 if (info->directRenderingEnabled && 1477 info->pKernelDRMVersion->version_minor < 23) { 1478 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1479 "[dri] limiting video memory to one aperture of %uK\n", 1480 (unsigned)aper_size); 1481 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1482 "[dri] detected radeon kernel module version 1.%d but" 1483 " 1.23 or newer is required for full memory mapping.\n", 1484 info->pKernelDRMVersion->version_minor); 1485 info->newMemoryMap = FALSE; 1486 return aper_size; 1487 } 1488 info->newMemoryMap = TRUE; 1489#endif /* XF86DRI */ 1490 1491 /* Set HDP_APER_CNTL only on cards that are known not to be broken, 1492 * that is has the 2nd generation multifunction PCI interface 1493 */ 1494 if (info->ChipFamily == CHIP_FAMILY_RV280 || 1495 info->ChipFamily == CHIP_FAMILY_RV350 || 1496 info->ChipFamily == CHIP_FAMILY_RV380 || 1497 info->ChipFamily == CHIP_FAMILY_R420 || 1498 info->ChipFamily == CHIP_FAMILY_RV410 || 1499 IS_AVIVO_VARIANT) { 1500 OUTREGP (RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, 1501 ~RADEON_HDP_APER_CNTL); 1502 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1503 "Generation 2 PCI interface, using max accessible memory\n"); 1504 return aper_size * 2; 1505 } 1506 1507 /* Older cards have all sorts of funny issues to deal with. First 1508 * check if it's a multifunction card by reading the PCI config 1509 * header type... Limit those to one aperture size 1510 */ 1511 PCI_READ_BYTE(info->PciInfo, &byte, 0xe); 1512 if (byte & 0x80) { 1513 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1514 "Generation 1 PCI interface in multifunction mode" 1515 ", accessible memory limited to one aperture\n"); 1516 return aper_size; 1517 } 1518 1519 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS 1520 * have set it up. We don't write this as it's broken on some ASICs but 1521 * we expect the BIOS to have done the right thing (might be too optimistic...) 1522 */ 1523 if (INREG(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) 1524 return aper_size * 2; 1525 1526 return aper_size; 1527} 1528 1529static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) 1530{ 1531 RADEONInfoPtr info = RADEONPTR(pScrn); 1532 EntityInfoPtr pEnt = info->pEnt; 1533 GDevPtr dev = pEnt->device; 1534 unsigned char *RADEONMMIO = info->MMIO; 1535 MessageType from = X_PROBED; 1536 uint32_t accessible, bar_size; 1537 1538 if ((!IS_AVIVO_VARIANT) && info->IsIGP) { 1539 uint32_t tom = INREG(RADEON_NB_TOM); 1540 1541 pScrn->videoRam = (((tom >> 16) - 1542 (tom & 0xffff) + 1) << 6); 1543 1544 OUTREG(RADEON_CONFIG_MEMSIZE, pScrn->videoRam * 1024); 1545 } else { 1546 if (info->ChipFamily >= CHIP_FAMILY_R600) 1547 pScrn->videoRam = INREG(R600_CONFIG_MEMSIZE) / 1024; 1548 else { 1549 /* Read VRAM size from card */ 1550 pScrn->videoRam = INREG(RADEON_CONFIG_MEMSIZE) / 1024; 1551 1552 /* Some production boards of m6 will return 0 if it's 8 MB */ 1553 if (pScrn->videoRam == 0) { 1554 pScrn->videoRam = 8192; 1555 OUTREG(RADEON_CONFIG_MEMSIZE, 0x800000); 1556 } 1557 } 1558 } 1559 1560 /* Get accessible memory */ 1561 accessible = RADEONGetAccessibleVRAM(pScrn); 1562 1563 /* Crop it to the size of the PCI BAR */ 1564 bar_size = PCI_REGION_SIZE(info->PciInfo, 0) / 1024; 1565 if (bar_size == 0) 1566 bar_size = 0x20000; 1567 if (accessible > bar_size) 1568 accessible = bar_size; 1569 1570 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1571 "Detected total video RAM=%dK, accessible=%uK (PCI BAR=%uK)\n", 1572 pScrn->videoRam, (unsigned)accessible, (unsigned)bar_size); 1573 if (pScrn->videoRam > accessible) 1574 pScrn->videoRam = accessible; 1575 1576 if (!IS_AVIVO_VARIANT) 1577 info->MemCntl = INREG(RADEON_SDRAM_MODE_REG); 1578 info->BusCntl = INREG(RADEON_BUS_CNTL); 1579 1580 RADEONGetVRamType(pScrn); 1581 1582 if (dev->videoRam) { 1583 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1584 "Video RAM override, using %d kB instead of %d kB\n", 1585 dev->videoRam, 1586 pScrn->videoRam); 1587 from = X_CONFIG; 1588 pScrn->videoRam = dev->videoRam; 1589 } 1590 1591 xf86DrvMsg(pScrn->scrnIndex, from, 1592 "Mapped VideoRAM: %d kByte (%d bit %s SDRAM)\n", pScrn->videoRam, info->RamWidth, info->IsDDR?"DDR":"SDR"); 1593 1594 if (info->IsPrimary) { 1595 pScrn->videoRam /= 2; 1596 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1597 "Using %dk of videoram for primary head\n", 1598 pScrn->videoRam); 1599 } 1600 1601 if (info->IsSecondary) { 1602 pScrn->videoRam /= 2; 1603 info->LinearAddr += pScrn->videoRam * 1024; 1604 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1605 "Using %dk of videoram for secondary head\n", 1606 pScrn->videoRam); 1607 } 1608 1609 pScrn->videoRam &= ~1023; 1610 info->FbMapSize = pScrn->videoRam * 1024; 1611 1612 /* if the card is PCI Express reserve the last 32k for the gart table */ 1613#ifdef XF86DRI 1614 if (info->cardType == CARD_PCIE && info->directRenderingEnabled) 1615 /* work out the size of pcie aperture */ 1616 info->FbSecureSize = RADEONDRIGetPciAperTableSize(pScrn); 1617 else 1618#endif 1619 info->FbSecureSize = 0; 1620 1621 return TRUE; 1622} 1623 1624 1625/* This is called by RADEONPreInit to handle config file overrides for 1626 * things like chipset and memory regions. Also determine memory size 1627 * and type. If memory type ever needs an override, put it in this 1628 * routine. 1629 */ 1630static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) 1631{ 1632 RADEONInfoPtr info = RADEONPTR(pScrn); 1633 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1634 EntityInfoPtr pEnt = info->pEnt; 1635 GDevPtr dev = pEnt->device; 1636 unsigned char *RADEONMMIO = info->MMIO; 1637 MessageType from = X_PROBED; 1638 int i; 1639#ifdef XF86DRI 1640 const char *s; 1641 uint32_t cmd_stat; 1642#endif 1643 1644 /* Chipset */ 1645 from = X_PROBED; 1646 if (dev->chipset && *dev->chipset) { 1647 info->Chipset = xf86StringToToken(RADEONChipsets, dev->chipset); 1648 from = X_CONFIG; 1649 } else if (dev->chipID >= 0) { 1650 info->Chipset = dev->chipID; 1651 from = X_CONFIG; 1652 } else { 1653 info->Chipset = PCI_DEV_DEVICE_ID(info->PciInfo); 1654 } 1655 1656 pScrn->chipset = (char *)xf86TokenToString(RADEONChipsets, info->Chipset); 1657 if (!pScrn->chipset) { 1658 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1659 "ChipID 0x%04x is not recognized\n", info->Chipset); 1660 return FALSE; 1661 } 1662 if (info->Chipset < 0) { 1663 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1664 "Chipset \"%s\" is not recognized\n", pScrn->chipset); 1665 return FALSE; 1666 } 1667 xf86DrvMsg(pScrn->scrnIndex, from, 1668 "Chipset: \"%s\" (ChipID = 0x%04x)\n", 1669 pScrn->chipset, 1670 info->Chipset); 1671 1672 pRADEONEnt->HasCRTC2 = TRUE; 1673 info->IsMobility = FALSE; 1674 info->IsIGP = FALSE; 1675 info->IsDellServer = FALSE; 1676 info->HasSingleDAC = FALSE; 1677 info->InternalTVOut = TRUE; 1678 1679 for (i = 0; i < sizeof(RADEONCards) / sizeof(RADEONCardInfo); i++) { 1680 if (info->Chipset == RADEONCards[i].pci_device_id) { 1681 RADEONCardInfo *card = &RADEONCards[i]; 1682 info->ChipFamily = card->chip_family; 1683 info->IsMobility = card->mobility; 1684 info->IsIGP = card->igp; 1685 pRADEONEnt->HasCRTC2 = !card->nocrtc2; 1686 info->HasSingleDAC = card->singledac; 1687 info->InternalTVOut = !card->nointtvout; 1688 break; 1689 } 1690 } 1691 1692 switch (info->Chipset) { 1693 case PCI_CHIP_RN50_515E: /* RN50 is based on the RV100 but 3D isn't guaranteed to work. YMMV. */ 1694 case PCI_CHIP_RN50_5969: 1695 case PCI_CHIP_RV100_QY: 1696 case PCI_CHIP_RV100_QZ: 1697 /* DELL triple-head configuration. */ 1698 if ((PCI_SUB_VENDOR_ID(info->PciInfo) == PCI_VENDOR_DELL) && 1699 ((PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016c) || 1700 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016d) || 1701 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016e) || 1702 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016f) || 1703 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0170) || 1704 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x017d) || 1705 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x017e) || 1706 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0183) || 1707 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x018a) || 1708 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x019a))) { 1709 info->IsDellServer = TRUE; 1710 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "DELL server detected, force to special setup\n"); 1711 } 1712 break; 1713 case PCI_CHIP_RS482_5974: 1714 /* RH BZ 444586 - non mobility version 1715 * Dell appear to have the Vostro 1100 with a mobility part with the same pci-id */ 1716 if ((PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1462) && 1717 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x7141)) { 1718 info->IsMobility = FALSE; 1719 } 1720 default: 1721 break; 1722 } 1723 1724 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1725 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1726 "R600 support is mostly incomplete and very experimental\n"); 1727 } 1728 1729 if ((info->ChipFamily >= CHIP_FAMILY_RV515) && (info->ChipFamily < CHIP_FAMILY_R600)) { 1730 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1731 "R500 support is under development. Please report any issues to xorg-driver-ati@lists.x.org\n"); 1732 } 1733 1734 from = X_PROBED; 1735 info->LinearAddr = PCI_REGION_BASE(info->PciInfo, 0, REGION_MEM) & ~0x1ffffffUL; 1736 pScrn->memPhysBase = info->LinearAddr; 1737 if (dev->MemBase) { 1738 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1739 "Linear address override, using 0x%016lx instead of 0x%016lx\n", 1740 dev->MemBase, 1741 info->LinearAddr); 1742 info->LinearAddr = dev->MemBase; 1743 from = X_CONFIG; 1744 } else if (!info->LinearAddr) { 1745 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1746 "No valid linear framebuffer address\n"); 1747 return FALSE; 1748 } 1749 xf86DrvMsg(pScrn->scrnIndex, from, 1750 "Linear framebuffer at 0x%016lx\n", info->LinearAddr); 1751 1752#ifndef XSERVER_LIBPCIACCESS 1753 /* BIOS */ 1754 from = X_PROBED; 1755 info->BIOSAddr = info->PciInfo->biosBase & 0xfffe0000; 1756 if (dev->BiosBase) { 1757 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1758 "BIOS address override, using 0x%08lx instead of 0x%08lx\n", 1759 dev->BiosBase, 1760 info->BIOSAddr); 1761 info->BIOSAddr = dev->BiosBase; 1762 from = X_CONFIG; 1763 } 1764 if (info->BIOSAddr) { 1765 xf86DrvMsg(pScrn->scrnIndex, from, 1766 "BIOS at 0x%08lx\n", info->BIOSAddr); 1767 } 1768#endif 1769 1770 /* Read registers used to determine options */ 1771 /* Check chip errata */ 1772 info->ChipErrata = 0; 1773 1774 if (info->ChipFamily == CHIP_FAMILY_R300 && 1775 (INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) 1776 == RADEON_CFG_ATI_REV_A11) 1777 info->ChipErrata |= CHIP_ERRATA_R300_CG; 1778 1779 if (info->ChipFamily == CHIP_FAMILY_RV200 || 1780 info->ChipFamily == CHIP_FAMILY_RS200) 1781 info->ChipErrata |= CHIP_ERRATA_PLL_DUMMYREADS; 1782 1783 if (info->ChipFamily == CHIP_FAMILY_RV100 || 1784 info->ChipFamily == CHIP_FAMILY_RS100 || 1785 info->ChipFamily == CHIP_FAMILY_RS200) 1786 info->ChipErrata |= CHIP_ERRATA_PLL_DELAY; 1787 1788#ifdef XF86DRI 1789 /* AGP/PCI */ 1790 /* Proper autodetection of an AGP capable device requires examining 1791 * PCI config registers to determine if the device implements extended 1792 * PCI capabilities, and then walking the capability list as indicated 1793 * in the PCI 2.2 and AGP 2.0 specifications, to determine if AGP 1794 * capability is present. The procedure is outlined as follows: 1795 * 1796 * 1) Test bit 4 (CAP_LIST) of the PCI status register of the device 1797 * to determine wether or not this device implements any extended 1798 * capabilities. If this bit is zero, then the device is a PCI 2.1 1799 * or earlier device and is not AGP capable, and we can conclude it 1800 * to be a PCI device. 1801 * 1802 * 2) If bit 4 of the status register is set, then the device implements 1803 * extended capabilities. There is an 8 bit wide capabilities pointer 1804 * register located at offset 0x34 in PCI config space which points to 1805 * the first capability in a linked list of extended capabilities that 1806 * this device implements. The lower two bits of this register are 1807 * reserved and MBZ so must be masked out. 1808 * 1809 * 3) The extended capabilities list is formed by one or more extended 1810 * capabilities structures which are aligned on DWORD boundaries. 1811 * The first byte of the structure is the capability ID (CAP_ID) 1812 * indicating what extended capability this structure refers to. The 1813 * second byte of the structure is an offset from the beginning of 1814 * PCI config space pointing to the next capability in the linked 1815 * list (NEXT_PTR) or NULL (0x00) at the end of the list. The lower 1816 * two bits of this pointer are reserved and MBZ. By examining the 1817 * CAP_ID of each capability and walking through the list, we will 1818 * either find the AGP_CAP_ID (0x02) indicating this device is an 1819 * AGP device, or we'll reach the end of the list, indicating it is 1820 * a PCI device. 1821 * 1822 * Mike A. Harris <mharris@redhat.com> 1823 * 1824 * References: 1825 * - PCI Local Bus Specification Revision 2.2, Chapter 6 1826 * - AGP Interface Specification Revision 2.0, Section 6.1.5 1827 */ 1828 1829 info->cardType = CARD_PCI; 1830 1831 PCI_READ_LONG(info->PciInfo, &cmd_stat, PCI_CMD_STAT_REG); 1832 if (cmd_stat & RADEON_CAP_LIST) { 1833 uint32_t cap_ptr, cap_id; 1834 1835 PCI_READ_LONG(info->PciInfo, &cap_ptr, RADEON_CAPABILITIES_PTR_PCI_CONFIG); 1836 cap_ptr &= RADEON_CAP_PTR_MASK; 1837 1838 while(cap_ptr != RADEON_CAP_ID_NULL) { 1839 PCI_READ_LONG(info->PciInfo, &cap_id, cap_ptr); 1840 if ((cap_id & 0xff)== RADEON_CAP_ID_AGP) { 1841 info->cardType = CARD_AGP; 1842 break; 1843 } 1844 if ((cap_id & 0xff)== RADEON_CAP_ID_EXP) { 1845 info->cardType = CARD_PCIE; 1846 break; 1847 } 1848 cap_ptr = (cap_id >> 8) & RADEON_CAP_PTR_MASK; 1849 } 1850 } 1851 1852 1853 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s card detected\n", 1854 (info->cardType==CARD_PCI) ? "PCI" : 1855 (info->cardType==CARD_PCIE) ? "PCIE" : "AGP"); 1856 1857 /* treat PCIE IGP cards as PCI */ 1858 if (info->cardType == CARD_PCIE && info->IsIGP) 1859 info->cardType = CARD_PCI; 1860 1861 if ((s = xf86GetOptValString(info->Options, OPTION_BUS_TYPE))) { 1862 if (strcmp(s, "AGP") == 0) { 1863 info->cardType = CARD_AGP; 1864 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into AGP mode\n"); 1865 } else if (strcmp(s, "PCI") == 0) { 1866 info->cardType = CARD_PCI; 1867 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI mode\n"); 1868 } else if (strcmp(s, "PCIE") == 0) { 1869 info->cardType = CARD_PCIE; 1870 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI Express mode\n"); 1871 } else { 1872 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, 1873 "Invalid BusType option, using detected type\n"); 1874 } 1875 } 1876#endif 1877 xf86GetOptValBool(info->Options, OPTION_SHOWCACHE, &info->showCache); 1878 if (info->showCache) 1879 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, 1880 "Option ShowCache enabled\n"); 1881 1882#ifdef RENDER 1883 info->RenderAccel = xf86ReturnOptValBool(info->Options, OPTION_RENDER_ACCEL, 1884 info->Chipset != PCI_CHIP_RN50_515E && 1885 info->Chipset != PCI_CHIP_RN50_5969); 1886#endif 1887 1888 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1889 info->r600_shadow_fb = TRUE; 1890 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1891 "using shadow framebuffer\n"); 1892 if (!xf86LoadSubModule(pScrn, "shadow")) 1893 return FALSE; 1894 } 1895 1896 1897 if ((info->ChipFamily == CHIP_FAMILY_RS100) || 1898 (info->ChipFamily == CHIP_FAMILY_RS200) || 1899 (info->ChipFamily == CHIP_FAMILY_RS300) || 1900 (info->ChipFamily == CHIP_FAMILY_RS400) || 1901 (info->ChipFamily == CHIP_FAMILY_RS480) || 1902 (info->ChipFamily == CHIP_FAMILY_RS600) || 1903 (info->ChipFamily == CHIP_FAMILY_RS690) || 1904 (info->ChipFamily == CHIP_FAMILY_RS740)) 1905 info->has_tcl = FALSE; 1906 else { 1907 info->has_tcl = TRUE; 1908 } 1909 1910 return TRUE; 1911} 1912 1913 1914static void RADEONPreInitDDC(ScrnInfoPtr pScrn) 1915{ 1916 RADEONInfoPtr info = RADEONPTR(pScrn); 1917 /* vbeInfoPtr pVbe; */ 1918 1919 info->ddc1 = FALSE; 1920 info->ddc_bios = FALSE; 1921 if (!xf86LoadSubModule(pScrn, "ddc")) { 1922 info->ddc2 = FALSE; 1923 } else { 1924 info->ddc2 = TRUE; 1925 } 1926 1927 /* DDC can use I2C bus */ 1928 /* Load I2C if we have the code to use it */ 1929 if (info->ddc2) { 1930 xf86LoadSubModule(pScrn, "i2c"); 1931 } 1932} 1933 1934/* This is called by RADEONPreInit to initialize gamma correction */ 1935static Bool RADEONPreInitGamma(ScrnInfoPtr pScrn) 1936{ 1937 Gamma zeros = { 0.0, 0.0, 0.0 }; 1938 1939 if (!xf86SetGamma(pScrn, zeros)) return FALSE; 1940 return TRUE; 1941} 1942 1943/* This is called by RADEONPreInit to initialize the hardware cursor */ 1944static Bool RADEONPreInitCursor(ScrnInfoPtr pScrn) 1945{ 1946 RADEONInfoPtr info = RADEONPTR(pScrn); 1947 1948 if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) { 1949 if (!xf86LoadSubModule(pScrn, "ramdac")) return FALSE; 1950 } 1951 return TRUE; 1952} 1953 1954/* This is called by RADEONPreInit to initialize hardware acceleration */ 1955static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) 1956{ 1957 RADEONInfoPtr info = RADEONPTR(pScrn); 1958 MessageType from; 1959#if defined(USE_EXA) && defined(USE_XAA) 1960 char *optstr; 1961#endif 1962 1963 info->useEXA = FALSE; 1964 1965 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1966 xf86DrvMsg(pScrn->scrnIndex, X_DEFAULT, 1967 "No acceleration support available on R600 yet.\n"); 1968 return TRUE; 1969 } 1970 1971 if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { 1972 int errmaj = 0, errmin = 0; 1973 1974 from = X_DEFAULT; 1975#if defined(USE_EXA) 1976#if defined(USE_XAA) 1977 optstr = (char *)xf86GetOptValString(info->Options, OPTION_ACCELMETHOD); 1978 if (optstr != NULL) { 1979 if (xf86NameCmp(optstr, "EXA") == 0) { 1980 from = X_CONFIG; 1981 info->useEXA = TRUE; 1982 } else if (xf86NameCmp(optstr, "XAA") == 0) { 1983 from = X_CONFIG; 1984 } 1985 } 1986#else /* USE_XAA */ 1987 info->useEXA = TRUE; 1988#endif /* !USE_XAA */ 1989#endif /* USE_EXA */ 1990 xf86DrvMsg(pScrn->scrnIndex, from, 1991 "Using %s acceleration architecture\n", 1992 info->useEXA ? "EXA" : "XAA"); 1993 1994#ifdef USE_EXA 1995 if (info->useEXA) { 1996 info->exaReq.majorversion = EXA_VERSION_MAJOR; 1997 info->exaReq.minorversion = EXA_VERSION_MINOR; 1998 1999 if (!LoadSubModule(pScrn->module, "exa", NULL, NULL, NULL, 2000 &info->exaReq, &errmaj, &errmin)) { 2001 LoaderErrorMsg(NULL, "exa", errmaj, errmin); 2002 return FALSE; 2003 } 2004 } 2005#endif /* USE_EXA */ 2006#ifdef USE_XAA 2007 if (!info->useEXA) { 2008 info->xaaReq.majorversion = 1; 2009 info->xaaReq.minorversion = 2; 2010 2011 if (!LoadSubModule(pScrn->module, "xaa", NULL, NULL, NULL, 2012 &info->xaaReq, &errmaj, &errmin)) { 2013 info->xaaReq.minorversion = 1; 2014 2015 if (!LoadSubModule(pScrn->module, "xaa", NULL, NULL, NULL, 2016 &info->xaaReq, &errmaj, &errmin)) { 2017 info->xaaReq.minorversion = 0; 2018 2019 if (!LoadSubModule(pScrn->module, "xaa", NULL, NULL, NULL, 2020 &info->xaaReq, &errmaj, &errmin)) { 2021 LoaderErrorMsg(NULL, "xaa", errmaj, errmin); 2022 return FALSE; 2023 } 2024 } 2025 } 2026 } 2027#endif /* USE_XAA */ 2028 } 2029 2030 return TRUE; 2031} 2032 2033static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10) 2034{ 2035#if !defined(__powerpc__) && !defined(__sparc__) 2036 RADEONInfoPtr info = RADEONPTR(pScrn); 2037 unsigned char *RADEONMMIO = info->MMIO; 2038 uint32_t fp2_gen_ctl_save = 0; 2039 2040#ifdef XSERVER_LIBPCIACCESS 2041#if HAVE_PCI_DEVICE_ENABLE 2042 pci_device_enable(info->PciInfo); 2043#endif 2044#endif 2045 /* don't need int10 on atom cards. 2046 * in theory all radeons, but the older stuff 2047 * isn't 100% yet 2048 * secondary atom cards tend to hang when initializing int10, 2049 * however, on some stom cards, you can't read the bios without 2050 * intitializing int10. 2051 */ 2052 if (!xf86ReturnOptValBool(info->Options, OPTION_INT10, TRUE)) 2053 return TRUE; 2054 2055 if (xf86LoadSubModule(pScrn, "int10")) { 2056 /* The VGA BIOS on the RV100/QY cannot be read when the digital output 2057 * is enabled. Clear and restore FP2_ON around int10 to avoid this. 2058 */ 2059 if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) { 2060 fp2_gen_ctl_save = INREG(RADEON_FP2_GEN_CNTL); 2061 if (fp2_gen_ctl_save & RADEON_FP2_ON) { 2062 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "disabling digital out\n"); 2063 OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_ctl_save & ~RADEON_FP2_ON); 2064 } 2065 } 2066 2067 xf86DrvMsg(pScrn->scrnIndex,X_INFO,"initializing int10\n"); 2068 *ppInt10 = xf86InitInt10(info->pEnt->index); 2069 2070 if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) { 2071 if (fp2_gen_ctl_save & RADEON_FP2_ON) { 2072 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "re-enabling digital out\n"); 2073 OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_ctl_save); 2074 } 2075 } 2076 } 2077#endif 2078 return TRUE; 2079} 2080 2081#ifdef XF86DRI 2082static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) 2083{ 2084 RADEONInfoPtr info = RADEONPTR(pScrn); 2085 MessageType from; 2086 char *reason; 2087 2088 info->directRenderingEnabled = FALSE; 2089 info->directRenderingInited = FALSE; 2090 info->CPInUse = FALSE; 2091 info->CPStarted = FALSE; 2092 info->pLibDRMVersion = NULL; 2093 info->pKernelDRMVersion = NULL; 2094 2095 if (xf86IsEntityShared(info->pEnt->index)) { 2096 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2097 "Direct Rendering Disabled -- " 2098 "Dual-head configuration is not working with " 2099 "DRI at present.\n" 2100 "Please use the radeon MergedFB option if you " 2101 "want Dual-head with DRI.\n"); 2102 return FALSE; 2103 } 2104 if (info->IsSecondary) 2105 return FALSE; 2106 2107 if (info->Chipset == PCI_CHIP_RN50_515E || 2108 info->Chipset == PCI_CHIP_RN50_5969 || 2109 info->Chipset == PCI_CHIP_RC410_5A61 || 2110 info->Chipset == PCI_CHIP_RC410_5A62 || 2111 info->Chipset == PCI_CHIP_RS485_5975 || 2112 info->ChipFamily == CHIP_FAMILY_RS600 || 2113 info->ChipFamily >= CHIP_FAMILY_R600) { 2114 if (xf86ReturnOptValBool(info->Options, OPTION_DRI, FALSE)) { 2115 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2116 "Direct rendering for RN50/RC410/RS485/RS600/R600 forced on -- " 2117 "This is NOT officially supported at the hardware level " 2118 "and may cause instability or lockups\n"); 2119 } else { 2120 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2121 "Direct rendering not officially supported on RN50/RC410/R600\n"); 2122 return FALSE; 2123 } 2124 } 2125 2126 2127 if (!xf86ReturnOptValBool(info->Options, OPTION_DRI, TRUE)) { 2128 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2129 "Direct rendering forced off\n"); 2130 return FALSE; 2131 } 2132 2133 if (xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { 2134 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2135 "[dri] Acceleration disabled, not initializing the DRI\n"); 2136 return FALSE; 2137 } 2138 2139 if (!RADEONDRIGetVersion(pScrn)) 2140 return FALSE; 2141 2142 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2143 "[dri] Found DRI library version %d.%d.%d and kernel" 2144 " module version %d.%d.%d\n", 2145 info->pLibDRMVersion->version_major, 2146 info->pLibDRMVersion->version_minor, 2147 info->pLibDRMVersion->version_patchlevel, 2148 info->pKernelDRMVersion->version_major, 2149 info->pKernelDRMVersion->version_minor, 2150 info->pKernelDRMVersion->version_patchlevel); 2151 2152 if (info->Chipset == PCI_CHIP_RS400_5A41 || 2153 info->Chipset == PCI_CHIP_RS400_5A42 || 2154 info->Chipset == PCI_CHIP_RC410_5A61 || 2155 info->Chipset == PCI_CHIP_RC410_5A62 || 2156 info->Chipset == PCI_CHIP_RS480_5954 || 2157 info->Chipset == PCI_CHIP_RS480_5955 || 2158 info->Chipset == PCI_CHIP_RS482_5974 || 2159 info->Chipset == PCI_CHIP_RS485_5975) { 2160 2161 if (info->pKernelDRMVersion->version_minor < 27) { 2162 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2163 "Direct rendering broken on XPRESS 200 and 200M with DRI less than 1.27\n"); 2164 return FALSE; 2165 } 2166 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2167 "Direct rendering experimental on RS400/Xpress 200 enabled\n"); 2168 } 2169 2170 if (xf86ReturnOptValBool(info->Options, OPTION_CP_PIO, FALSE)) { 2171 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forcing CP into PIO mode\n"); 2172 info->CPMode = RADEON_DEFAULT_CP_PIO_MODE; 2173 } else { 2174 info->CPMode = RADEON_DEFAULT_CP_BM_MODE; 2175 } 2176 2177 info->gartSize = RADEON_DEFAULT_GART_SIZE; 2178 info->ringSize = RADEON_DEFAULT_RING_SIZE; 2179 info->bufSize = RADEON_DEFAULT_BUFFER_SIZE; 2180 info->gartTexSize = RADEON_DEFAULT_GART_TEX_SIZE; 2181 info->pciAperSize = RADEON_DEFAULT_PCI_APER_SIZE; 2182 info->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT; 2183 2184 if ((xf86GetOptValInteger(info->Options, 2185 OPTION_GART_SIZE, (int *)&(info->gartSize))) || 2186 (xf86GetOptValInteger(info->Options, 2187 OPTION_GART_SIZE_OLD, (int *)&(info->gartSize)))) { 2188 switch (info->gartSize) { 2189 case 4: 2190 case 8: 2191 case 16: 2192 case 32: 2193 case 64: 2194 case 128: 2195 case 256: 2196 break; 2197 2198 default: 2199 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2200 "Illegal GART size: %d MB\n", info->gartSize); 2201 return FALSE; 2202 } 2203 } 2204 2205 if (xf86GetOptValInteger(info->Options, 2206 OPTION_RING_SIZE, &(info->ringSize))) { 2207 if (info->ringSize < 1 || info->ringSize >= (int)info->gartSize) { 2208 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2209 "Illegal ring buffer size: %d MB\n", 2210 info->ringSize); 2211 return FALSE; 2212 } 2213 } 2214 2215 if (xf86GetOptValInteger(info->Options, 2216 OPTION_PCIAPER_SIZE, &(info->pciAperSize))) { 2217 switch(info->pciAperSize) { 2218 case 32: 2219 case 64: 2220 case 128: 2221 case 256: 2222 break; 2223 default: 2224 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2225 "Illegal pci aper size: %d MB\n", 2226 info->pciAperSize); 2227 return FALSE; 2228 } 2229 } 2230 2231 2232 if (xf86GetOptValInteger(info->Options, 2233 OPTION_BUFFER_SIZE, &(info->bufSize))) { 2234 if (info->bufSize < 1 || info->bufSize >= (int)info->gartSize) { 2235 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2236 "Illegal vertex/indirect buffers size: %d MB\n", 2237 info->bufSize); 2238 return FALSE; 2239 } 2240 if (info->bufSize > 2) { 2241 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2242 "Illegal vertex/indirect buffers size: %d MB\n", 2243 info->bufSize); 2244 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2245 "Clamping vertex/indirect buffers size to 2 MB\n"); 2246 info->bufSize = 2; 2247 } 2248 } 2249 2250 if (info->ringSize + info->bufSize + info->gartTexSize > 2251 (int)info->gartSize) { 2252 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2253 "Buffers are too big for requested GART space\n"); 2254 return FALSE; 2255 } 2256 2257 info->gartTexSize = info->gartSize - (info->ringSize + info->bufSize); 2258 2259 if (xf86GetOptValInteger(info->Options, OPTION_USEC_TIMEOUT, 2260 &(info->CPusecTimeout))) { 2261 /* This option checked by the RADEON DRM kernel module */ 2262 } 2263 2264 /* Two options to try and squeeze as much texture memory as possible 2265 * for dedicated 3d rendering boxes 2266 */ 2267 info->noBackBuffer = xf86ReturnOptValBool(info->Options, 2268 OPTION_NO_BACKBUFFER, 2269 FALSE); 2270 2271 info->allowPageFlip = 0; 2272 2273#ifdef DAMAGE 2274 if (info->noBackBuffer) { 2275 from = X_DEFAULT; 2276 reason = " because back buffer disabled"; 2277 } else { 2278 from = xf86GetOptValBool(info->Options, OPTION_PAGE_FLIP, 2279 &info->allowPageFlip) ? X_CONFIG : X_DEFAULT; 2280 2281 if (IS_AVIVO_VARIANT) { 2282 info->allowPageFlip = 0; 2283 reason = " on r5xx and newer chips.\n"; 2284 } else { 2285 reason = ""; 2286 } 2287 2288 } 2289#else 2290 from = X_DEFAULT; 2291 reason = " because Damage layer not available at build time"; 2292#endif 2293 2294 xf86DrvMsg(pScrn->scrnIndex, from, "Page Flipping %sabled%s\n", 2295 info->allowPageFlip ? "en" : "dis", reason); 2296 2297 info->DMAForXv = TRUE; 2298 from = xf86GetOptValBool(info->Options, OPTION_XV_DMA, &info->DMAForXv) 2299 ? X_CONFIG : X_INFO; 2300 xf86DrvMsg(pScrn->scrnIndex, from, 2301 "Will %stry to use DMA for Xv image transfers\n", 2302 info->DMAForXv ? "" : "not "); 2303 2304 return TRUE; 2305} 2306#endif /* XF86DRI */ 2307 2308static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) 2309{ 2310 RADEONInfoPtr info = RADEONPTR(pScrn); 2311 2312 info->allowColorTiling = xf86ReturnOptValBool(info->Options, 2313 OPTION_COLOR_TILING, TRUE); 2314 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { 2315 /* this may be 4096 on r4xx -- need to double check */ 2316 info->MaxSurfaceWidth = 3968; /* one would have thought 4096...*/ 2317 info->MaxLines = 4096; 2318 } else { 2319 info->MaxSurfaceWidth = 2048; 2320 info->MaxLines = 2048; 2321 } 2322 2323 if (!info->allowColorTiling) 2324 return; 2325 2326 if (info->ChipFamily >= CHIP_FAMILY_R600) 2327 info->allowColorTiling = FALSE; 2328 2329 /* for zaphod disable tiling for now */ 2330 if (info->IsPrimary || info->IsSecondary) 2331 info->allowColorTiling = FALSE; 2332 2333#ifdef XF86DRI 2334 if (info->directRenderingEnabled && 2335 info->pKernelDRMVersion->version_minor < 14) { 2336 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2337 "[dri] color tiling disabled because of version " 2338 "mismatch.\n" 2339 "[dri] radeon.o kernel module version is %d.%d.%d but " 2340 "1.14.0 or later is required for color tiling.\n", 2341 info->pKernelDRMVersion->version_major, 2342 info->pKernelDRMVersion->version_minor, 2343 info->pKernelDRMVersion->version_patchlevel); 2344 info->allowColorTiling = FALSE; 2345 return; 2346 } 2347#endif /* XF86DRI */ 2348 2349 if (info->allowColorTiling) { 2350 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Color tiling enabled by default\n"); 2351 } else { 2352 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Color tiling disabled\n"); 2353 } 2354} 2355 2356 2357static Bool RADEONPreInitXv(ScrnInfoPtr pScrn) 2358{ 2359 RADEONInfoPtr info = RADEONPTR(pScrn); 2360 uint16_t mm_table; 2361 uint16_t bios_header; 2362 uint16_t pll_info_block; 2363#ifdef XvExtension 2364 char* microc_path = NULL; 2365 char* microc_type = NULL; 2366 MessageType from; 2367 2368 if (xf86GetOptValInteger(info->Options, OPTION_VIDEO_KEY, 2369 &(info->videoKey))) { 2370 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "video key set to 0x%x\n", 2371 info->videoKey); 2372 } else { 2373 info->videoKey = 0x1E; 2374 } 2375 2376 if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_CRYSTAL, &(info->RageTheatreCrystal))) { 2377 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre Crystal frequency was specified as %d.%d Mhz\n", 2378 info->RageTheatreCrystal/100, info->RageTheatreCrystal % 100); 2379 } else { 2380 info->RageTheatreCrystal=-1; 2381 } 2382 2383 if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_TUNER_PORT, &(info->RageTheatreTunerPort))) { 2384 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre tuner port was specified as %d\n", 2385 info->RageTheatreTunerPort); 2386 } else { 2387 info->RageTheatreTunerPort=-1; 2388 } 2389 2390 if(info->RageTheatreTunerPort>5){ 2391 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to assign Rage Theatre tuner port to invalid value. Disabling setting\n"); 2392 info->RageTheatreTunerPort=-1; 2393 } 2394 2395 if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_COMPOSITE_PORT, &(info->RageTheatreCompositePort))) { 2396 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre composite port was specified as %d\n", 2397 info->RageTheatreCompositePort); 2398 } else { 2399 info->RageTheatreCompositePort=-1; 2400 } 2401 2402 if(info->RageTheatreCompositePort>6){ 2403 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to assign Rage Theatre composite port to invalid value. Disabling setting\n"); 2404 info->RageTheatreCompositePort=-1; 2405 } 2406 2407 if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_SVIDEO_PORT, &(info->RageTheatreSVideoPort))) { 2408 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre SVideo Port was specified as %d\n", 2409 info->RageTheatreSVideoPort); 2410 } else { 2411 info->RageTheatreSVideoPort=-1; 2412 } 2413 2414 if(info->RageTheatreSVideoPort>6){ 2415 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to assign Rage Theatre SVideo port to invalid value. Disabling setting\n"); 2416 info->RageTheatreSVideoPort=-1; 2417 } 2418 2419 if(xf86GetOptValInteger(info->Options, OPTION_TUNER_TYPE, &(info->tunerType))) { 2420 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Tuner type was specified as %d\n", 2421 info->tunerType); 2422 } else { 2423 info->tunerType=-1; 2424 } 2425 2426 if(info->tunerType>31){ 2427 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to set tuner type to invalid value. Disabling setting\n"); 2428 info->tunerType=-1; 2429 } 2430 2431 if((microc_path = xf86GetOptValString(info->Options, OPTION_RAGE_THEATRE_MICROC_PATH)) != NULL) 2432 { 2433 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre Microcode path was specified as %s\n", microc_path); 2434 info->RageTheatreMicrocPath = microc_path; 2435 } else { 2436 info->RageTheatreMicrocPath= NULL; 2437 } 2438 2439 if((microc_type = xf86GetOptValString(info->Options, OPTION_RAGE_THEATRE_MICROC_TYPE)) != NULL) 2440 { 2441 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre Microcode type was specified as %s\n", microc_type); 2442 info->RageTheatreMicrocType = microc_type; 2443 } else { 2444 info->RageTheatreMicrocType= NULL; 2445 } 2446 2447 if(xf86GetOptValInteger(info->Options, OPTION_SCALER_WIDTH, &(info->overlay_scaler_buffer_width))) { 2448 if ((info->overlay_scaler_buffer_width < 1024) || 2449 (info->overlay_scaler_buffer_width > 2048) || 2450 ((info->overlay_scaler_buffer_width % 64) != 0)) { 2451 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to set illegal scaler width. Using default\n"); 2452 from = X_DEFAULT; 2453 info->overlay_scaler_buffer_width = 0; 2454 } else 2455 from = X_CONFIG; 2456 } else { 2457 from = X_DEFAULT; 2458 info->overlay_scaler_buffer_width = 0; 2459 } 2460 if (!info->overlay_scaler_buffer_width) { 2461 /* overlay scaler line length differs for different revisions 2462 this needs to be maintained by hand */ 2463 switch(info->ChipFamily){ 2464 case CHIP_FAMILY_R200: 2465 case CHIP_FAMILY_R300: 2466 case CHIP_FAMILY_RV350: 2467 info->overlay_scaler_buffer_width = 1920; 2468 break; 2469 default: 2470 info->overlay_scaler_buffer_width = 1536; 2471 } 2472 } 2473 xf86DrvMsg(pScrn->scrnIndex, from, "Assuming overlay scaler buffer width is %d\n", 2474 info->overlay_scaler_buffer_width); 2475#endif 2476 2477 /* Rescue MM_TABLE before VBIOS is freed */ 2478 info->MM_TABLE_valid = FALSE; 2479 2480 if((info->VBIOS==NULL)||(info->VBIOS[0]!=0x55)||(info->VBIOS[1]!=0xaa)){ 2481 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Cannot access BIOS or it is not valid.\n" 2482 "\t\tIf your card is TV-in capable you will need to specify options RageTheatreCrystal, RageTheatreTunerPort, \n" 2483 "\t\tRageTheatreSVideoPort and TunerType in /etc/X11/xorg.conf.\n" 2484 ); 2485 info->MM_TABLE_valid = FALSE; 2486 return TRUE; 2487 } 2488 2489 bios_header=info->VBIOS[0x48]; 2490 bios_header+=(((int)info->VBIOS[0x49]+0)<<8); 2491 2492 mm_table=info->VBIOS[bios_header+0x38]; 2493 if(mm_table==0) 2494 { 2495 xf86DrvMsg(pScrn->scrnIndex,X_INFO,"No MM_TABLE found - assuming CARD is not TV-in capable.\n"); 2496 info->MM_TABLE_valid = FALSE; 2497 return TRUE; 2498 } 2499 mm_table+=(((int)info->VBIOS[bios_header+0x39]+0)<<8)-2; 2500 2501 if(mm_table>0) 2502 { 2503 memcpy(&(info->MM_TABLE), &(info->VBIOS[mm_table]), sizeof(info->MM_TABLE)); 2504 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "MM_TABLE: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 2505 info->MM_TABLE.table_revision, 2506 info->MM_TABLE.table_size, 2507 info->MM_TABLE.tuner_type, 2508 info->MM_TABLE.audio_chip, 2509 info->MM_TABLE.product_id, 2510 info->MM_TABLE.tuner_voltage_teletext_fm, 2511 info->MM_TABLE.i2s_config, 2512 info->MM_TABLE.video_decoder_type, 2513 info->MM_TABLE.video_decoder_host_config, 2514 info->MM_TABLE.input[0], 2515 info->MM_TABLE.input[1], 2516 info->MM_TABLE.input[2], 2517 info->MM_TABLE.input[3], 2518 info->MM_TABLE.input[4]); 2519 2520 /* Is it an MM_TABLE we know about ? */ 2521 if(info->MM_TABLE.table_size != 0xc){ 2522 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "This card has MM_TABLE we do not recognize.\n" 2523 "\t\tIf your card is TV-in capable you will need to specify options RageTheatreCrystal, RageTheatreTunerPort, \n" 2524 "\t\tRageTheatreSVideoPort and TunerType in /etc/X11/xorg.conf.\n" 2525 ); 2526 info->MM_TABLE_valid = FALSE; 2527 return TRUE; 2528 } 2529 info->MM_TABLE_valid = TRUE; 2530 } else { 2531 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "No MM_TABLE found - assuming card is not TV-in capable (mm_table=%d).\n", mm_table); 2532 info->MM_TABLE_valid = FALSE; 2533 } 2534 2535 pll_info_block=info->VBIOS[bios_header+0x30]; 2536 pll_info_block+=(((int)info->VBIOS[bios_header+0x31]+0)<<8); 2537 2538 info->video_decoder_type=info->VBIOS[pll_info_block+0x08]; 2539 info->video_decoder_type+=(((int)info->VBIOS[pll_info_block+0x09]+0)<<8); 2540 2541 return TRUE; 2542} 2543 2544static Bool 2545RADEONPreInitBIOS(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) 2546{ 2547 RADEONInfoPtr info = RADEONPTR(pScrn); 2548 2549 if (!RADEONGetBIOSInfo(pScrn, pInt10)) { 2550 /* Avivo chips require bios for atom */ 2551 if (IS_AVIVO_VARIANT) 2552 return FALSE; 2553 } 2554 return TRUE; 2555} 2556 2557static void RADEONFixZaphodOutputs(ScrnInfoPtr pScrn) 2558{ 2559 RADEONInfoPtr info = RADEONPTR(pScrn); 2560 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 2561 2562 if (info->IsPrimary) { 2563 xf86OutputDestroy(config->output[0]); 2564 while(config->num_output > 1) { 2565 xf86OutputDestroy(config->output[1]); 2566 } 2567 } else { 2568 while(config->num_output > 1) { 2569 xf86OutputDestroy(config->output[1]); 2570 } 2571 } 2572} 2573 2574static Bool RADEONPreInitControllers(ScrnInfoPtr pScrn) 2575{ 2576 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 2577 RADEONInfoPtr info = RADEONPTR(pScrn); 2578 int i; 2579 int mask; 2580 int found = 0; 2581 2582 if (!info->IsPrimary && !info->IsSecondary) 2583 mask = 3; 2584 else if (info->IsPrimary) 2585 mask = 1; 2586 else 2587 mask = 2; 2588 2589 if (!RADEONAllocateControllers(pScrn, mask)) 2590 return FALSE; 2591 2592 RADEONGetClockInfo(pScrn); 2593 2594 if (!RADEONSetupConnectors(pScrn)) { 2595 return FALSE; 2596 } 2597 2598 if (info->IsPrimary || info->IsSecondary) { 2599 /* fixup outputs for zaphod */ 2600 RADEONFixZaphodOutputs(pScrn); 2601 } 2602 2603 RADEONPrintPortMap(pScrn); 2604 2605 info->first_load_no_devices = FALSE; 2606 for (i = 0; i < config->num_output; i++) { 2607 xf86OutputPtr output = config->output[i]; 2608 2609 output->status = (*output->funcs->detect) (output); 2610 ErrorF("finished output detect: %d\n", i); 2611 if (info->IsPrimary || info->IsSecondary) { 2612 if (output->status != XF86OutputStatusConnected) 2613 return FALSE; 2614 } 2615 if (output->status != XF86OutputStatusDisconnected) 2616 found++; 2617 } 2618 2619 if (!found) { 2620 /* nothing connected, light up some defaults so the server comes up */ 2621 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No connected devices found!\n"); 2622 info->first_load_no_devices = TRUE; 2623 } 2624 2625 ErrorF("finished all detect\n"); 2626 return TRUE; 2627} 2628 2629static void 2630RADEONProbeDDC(ScrnInfoPtr pScrn, int indx) 2631{ 2632 vbeInfoPtr pVbe; 2633 2634 if (xf86LoadSubModule(pScrn, "vbe")) { 2635 pVbe = VBEInit(NULL,indx); 2636 ConfiguredMonitor = vbeDoEDID(pVbe, NULL); 2637 } 2638} 2639 2640static Bool 2641RADEONCRTCResize(ScrnInfoPtr scrn, int width, int height) 2642{ 2643 scrn->virtualX = width; 2644 scrn->virtualY = height; 2645 /* RADEONSetPitch(scrn); */ 2646 return TRUE; 2647} 2648 2649static const xf86CrtcConfigFuncsRec RADEONCRTCResizeFuncs = { 2650 RADEONCRTCResize 2651}; 2652 2653Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) 2654{ 2655 xf86CrtcConfigPtr xf86_config; 2656 RADEONInfoPtr info; 2657 xf86Int10InfoPtr pInt10 = NULL; 2658 void *int10_save = NULL; 2659 const char *s; 2660 int crtc_max_X, crtc_max_Y; 2661 RADEONEntPtr pRADEONEnt; 2662 DevUnion* pPriv; 2663 2664 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2665 "RADEONPreInit\n"); 2666 if (pScrn->numEntities != 1) return FALSE; 2667 2668 if (!RADEONGetRec(pScrn)) return FALSE; 2669 2670 info = RADEONPTR(pScrn); 2671 info->MMIO = NULL; 2672 2673 info->IsSecondary = FALSE; 2674 info->IsPrimary = FALSE; 2675 2676 info->pEnt = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]); 2677 if (info->pEnt->location.type != BUS_PCI) goto fail; 2678 2679 pPriv = xf86GetEntityPrivate(pScrn->entityList[0], 2680 getRADEONEntityIndex()); 2681 pRADEONEnt = pPriv->ptr; 2682 2683 if(xf86IsEntityShared(pScrn->entityList[0])) 2684 { 2685 if(xf86IsPrimInitDone(pScrn->entityList[0])) 2686 { 2687 info->IsSecondary = TRUE; 2688 pRADEONEnt->pSecondaryScrn = pScrn; 2689 info->SavedReg = &pRADEONEnt->SavedReg; 2690 info->ModeReg = &pRADEONEnt->ModeReg; 2691 } 2692 else 2693 { 2694 info->IsPrimary = TRUE; 2695 xf86SetPrimInitDone(pScrn->entityList[0]); 2696 pRADEONEnt->pPrimaryScrn = pScrn; 2697 pRADEONEnt->HasSecondary = FALSE; 2698 info->SavedReg = &pRADEONEnt->SavedReg; 2699 info->ModeReg = &pRADEONEnt->ModeReg; 2700 } 2701 } else { 2702 info->SavedReg = &pRADEONEnt->SavedReg; 2703 info->ModeReg = &pRADEONEnt->ModeReg; 2704 } 2705 2706 info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index); 2707 info->PciTag = pciTag(PCI_DEV_BUS(info->PciInfo), 2708 PCI_DEV_DEV(info->PciInfo), 2709 PCI_DEV_FUNC(info->PciInfo)); 2710 info->MMIOAddr = PCI_REGION_BASE(info->PciInfo, 2, REGION_MEM) & ~0xffUL; 2711 info->MMIOSize = PCI_REGION_SIZE(info->PciInfo, 2); 2712 if (info->pEnt->device->IOBase) { 2713 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, 2714 "MMIO address override, using 0x%08lx instead of 0x%08lx\n", 2715 info->pEnt->device->IOBase, 2716 info->MMIOAddr); 2717 info->MMIOAddr = info->pEnt->device->IOBase; 2718 } else if (!info->MMIOAddr) { 2719 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid MMIO address\n"); 2720 goto fail1; 2721 } 2722 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2723 "MMIO registers at 0x%016lx: size %ldKB\n", info->MMIOAddr, info->MMIOSize / 1024); 2724 2725 if(!RADEONMapMMIO(pScrn)) { 2726 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2727 "Memory map the MMIO region failed\n"); 2728 goto fail1; 2729 } 2730 2731#if !defined(__alpha__) 2732 if ( 2733#ifndef XSERVER_LIBPCIACCESS 2734 xf86GetPciDomain(info->PciTag) || 2735#endif 2736 !xf86IsPrimaryPci(info->PciInfo)) 2737 RADEONPreInt10Save(pScrn, &int10_save); 2738#else 2739 /* [Alpha] On the primary, the console already ran the BIOS and we're 2740 * going to run it again - so make sure to "fix up" the card 2741 * so that (1) we can read the BIOS ROM and (2) the BIOS will 2742 * get the memory config right. 2743 */ 2744 RADEONPreInt10Save(pScrn, &int10_save); 2745#endif 2746 2747 if (flags & PROBE_DETECT) { 2748 RADEONProbeDDC(pScrn, info->pEnt->index); 2749 RADEONPostInt10Check(pScrn, int10_save); 2750 if(info->MMIO) RADEONUnmapMMIO(pScrn); 2751 return TRUE; 2752 } 2753 2754 2755 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2756 "PCI bus %d card %d func %d\n", 2757 PCI_DEV_BUS(info->PciInfo), 2758 PCI_DEV_DEV(info->PciInfo), 2759 PCI_DEV_FUNC(info->PciInfo)); 2760 2761 if (xf86RegisterResources(info->pEnt->index, 0, ResExclusive)) 2762 goto fail; 2763 2764 xf86SetOperatingState(resVga, info->pEnt->index, ResUnusedOpr); 2765 2766 pScrn->racMemFlags = RAC_FB | RAC_COLORMAP | RAC_VIEWPORT | RAC_CURSOR; 2767 pScrn->monitor = pScrn->confScreen->monitor; 2768 2769 /* Allocate an xf86CrtcConfig */ 2770 xf86CrtcConfigInit (pScrn, &RADEONCRTCResizeFuncs); 2771 xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 2772 2773 2774 if (!RADEONPreInitVisual(pScrn)) 2775 goto fail; 2776 2777 /* We can't do this until we have a 2778 pScrn->display. */ 2779 xf86CollectOptions(pScrn, NULL); 2780 if (!(info->Options = xalloc(sizeof(RADEONOptions)))) 2781 goto fail; 2782 2783 memcpy(info->Options, RADEONOptions, sizeof(RADEONOptions)); 2784 xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options); 2785 2786 /* By default, don't do VGA IOs on ppc/sparc */ 2787#if defined(__powerpc__) || defined(__sparc__) || !defined(WITH_VGAHW) 2788 info->VGAAccess = FALSE; 2789#else 2790 info->VGAAccess = TRUE; 2791#endif 2792 2793#ifdef WITH_VGAHW 2794 xf86GetOptValBool(info->Options, OPTION_VGA_ACCESS, &info->VGAAccess); 2795 if (info->VGAAccess) { 2796 if (!xf86LoadSubModule(pScrn, "vgahw")) 2797 info->VGAAccess = FALSE; 2798 else { 2799 if (!vgaHWGetHWRec(pScrn)) 2800 info->VGAAccess = FALSE; 2801 } 2802 if (!info->VGAAccess) 2803 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Loading VGA module failed," 2804 " trying to run without it\n"); 2805 } else 2806 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VGAAccess option set to FALSE," 2807 " VGA module load skipped\n"); 2808 if (info->VGAAccess) 2809 vgaHWGetIOBase(VGAHWPTR(pScrn)); 2810#endif 2811 2812 2813 if (!RADEONPreInitWeight(pScrn)) 2814 goto fail; 2815 2816 info->DispPriority = 1; 2817 if ((s = xf86GetOptValString(info->Options, OPTION_DISP_PRIORITY))) { 2818 if (strcmp(s, "AUTO") == 0) { 2819 info->DispPriority = 1; 2820 } else if (strcmp(s, "BIOS") == 0) { 2821 info->DispPriority = 0; 2822 } else if (strcmp(s, "HIGH") == 0) { 2823 info->DispPriority = 2; 2824 } else 2825 info->DispPriority = 1; 2826 } 2827 2828 if (!RADEONPreInitChipType(pScrn)) 2829 goto fail; 2830 2831 if (!RADEONPreInitInt10(pScrn, &pInt10)) 2832 goto fail; 2833 2834 RADEONPostInt10Check(pScrn, int10_save); 2835 2836 if (!RADEONPreInitBIOS(pScrn, pInt10)) 2837 goto fail; 2838 2839#ifdef XF86DRI 2840 /* PreInit DRI first of all since we need that for getting a proper 2841 * memory map 2842 */ 2843 info->directRenderingEnabled = RADEONPreInitDRI(pScrn); 2844#endif 2845 if (!RADEONPreInitVRAM(pScrn)) 2846 goto fail; 2847 2848 RADEONPreInitColorTiling(pScrn); 2849 2850 /* we really need an FB manager... */ 2851 if (pScrn->display->virtualX) { 2852 crtc_max_X = pScrn->display->virtualX; 2853 crtc_max_Y = pScrn->display->virtualY; 2854 if (info->allowColorTiling) { 2855 if (crtc_max_X > info->MaxSurfaceWidth || 2856 crtc_max_Y > info->MaxLines) { 2857 info->allowColorTiling = FALSE; 2858 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2859 "Requested desktop size exceeds surface limts for tiling, ColorTiling disabled\n"); 2860 } 2861 } 2862 if (crtc_max_X > 8192) 2863 crtc_max_X = 8192; 2864 if (crtc_max_Y > 8192) 2865 crtc_max_Y = 8192; 2866 } else { 2867 /* 2868 * note that these aren't really the CRTC limits, they're just 2869 * heuristics until we have a better memory manager. 2870 */ 2871 if (pScrn->videoRam <= 16384) { 2872 crtc_max_X = 1600; 2873 crtc_max_Y = 1200; 2874 } else if (IS_R300_VARIANT) { 2875 crtc_max_X = 2560; 2876 crtc_max_Y = 1200; 2877 } else if (IS_AVIVO_VARIANT) { 2878 crtc_max_X = 2560; 2879 crtc_max_Y = 1600; 2880 } else { 2881 crtc_max_X = 2048; 2882 crtc_max_Y = 1200; 2883 } 2884 } 2885 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Max desktop size set to %dx%d\n", 2886 crtc_max_X, crtc_max_Y); 2887 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2888 "For a larger or smaller max desktop size, add a Virtual line to your xorg.conf\n"); 2889 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2890 "If you are having trouble with 3D, " 2891 "reduce the desktop size by adjusting the Virtual line to your xorg.conf\n"); 2892 2893 /*xf86CrtcSetSizeRange (pScrn, 320, 200, info->MaxSurfaceWidth, info->MaxLines);*/ 2894 xf86CrtcSetSizeRange (pScrn, 320, 200, crtc_max_X, crtc_max_Y); 2895 2896 RADEONPreInitDDC(pScrn); 2897 2898 if (!RADEONPreInitControllers(pScrn)) 2899 goto fail; 2900 2901 2902 ErrorF("before xf86InitialConfiguration\n"); 2903 2904 if (!xf86InitialConfiguration (pScrn, FALSE)) 2905 { 2906 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid modes.\n"); 2907 goto fail; 2908 } 2909 2910 ErrorF("after xf86InitialConfiguration\n"); 2911 2912 RADEONSetPitch(pScrn); 2913 2914 /* Set display resolution */ 2915 xf86SetDpi(pScrn, 0, 0); 2916 2917 /* Get ScreenInit function */ 2918 if (!xf86LoadSubModule(pScrn, "fb")) return FALSE; 2919 2920 if (!RADEONPreInitGamma(pScrn)) goto fail; 2921 2922 if (!RADEONPreInitCursor(pScrn)) goto fail; 2923 2924 if (!RADEONPreInitAccel(pScrn)) goto fail; 2925 2926 if (!IS_AVIVO_VARIANT) { 2927 if (!RADEONPreInitXv(pScrn)) goto fail; 2928 } 2929 2930 if (!xf86RandR12PreInit (pScrn)) 2931 { 2932 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "RandR initialization failure\n"); 2933 goto fail; 2934 } 2935 2936 if (pScrn->modes == NULL) { 2937 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No modes.\n"); 2938 goto fail; 2939 } 2940 2941 2942 /* Free int10 info */ 2943 if (pInt10) 2944 xf86FreeInt10(pInt10); 2945 2946 if(info->MMIO) RADEONUnmapMMIO(pScrn); 2947 info->MMIO = NULL; 2948 2949 xf86DrvMsg(pScrn->scrnIndex, X_NOTICE, 2950 "For information on using the multimedia capabilities\n\tof this" 2951 " adapter, please see http://gatos.sf.net.\n"); 2952 2953 xf86DrvMsg(pScrn->scrnIndex, X_NOTICE, 2954 "MergedFB support has been removed and replaced with" 2955 " xrandr 1.2 support\n"); 2956 2957 return TRUE; 2958 2959fail: 2960 /* Pre-init failed. */ 2961 /* Free the video bios (if applicable) */ 2962 if (info->VBIOS) { 2963 xfree(info->VBIOS); 2964 info->VBIOS = NULL; 2965 } 2966 2967 /* Free int10 info */ 2968 if (pInt10) 2969 xf86FreeInt10(pInt10); 2970 2971#ifdef WITH_VGAHW 2972 if (info->VGAAccess) 2973 vgaHWFreeHWRec(pScrn); 2974#endif 2975 2976 if(info->MMIO) RADEONUnmapMMIO(pScrn); 2977 info->MMIO = NULL; 2978 2979 fail1: 2980 RADEONFreeRec(pScrn); 2981 2982 return FALSE; 2983} 2984 2985/* Load a palette */ 2986static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors, 2987 int *indices, LOCO *colors, VisualPtr pVisual) 2988{ 2989 RADEONInfoPtr info = RADEONPTR(pScrn); 2990 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 2991 int i; 2992 int index, j; 2993 uint16_t lut_r[256], lut_g[256], lut_b[256]; 2994 int c; 2995 2996#ifdef XF86DRI 2997 if (info->CPStarted && pScrn->pScreen) DRILock(pScrn->pScreen, 0); 2998#endif 2999 3000 if (info->accelOn && pScrn->pScreen) 3001 RADEON_SYNC(info, pScrn); 3002 3003 { 3004 3005 for (c = 0; c < xf86_config->num_crtc; c++) { 3006 xf86CrtcPtr crtc = xf86_config->crtc[c]; 3007 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 3008 3009 for (i = 0 ; i < 256; i++) { 3010 lut_r[i] = radeon_crtc->lut_r[i] << 8; 3011 lut_g[i] = radeon_crtc->lut_g[i] << 8; 3012 lut_b[i] = radeon_crtc->lut_b[i] << 8; 3013 } 3014 3015 switch (info->CurrentLayout.depth) { 3016 case 15: 3017 for (i = 0; i < numColors; i++) { 3018 index = indices[i]; 3019 for (j = 0; j < 8; j++) { 3020 lut_r[index * 8 + j] = colors[index].red << 8; 3021 lut_g[index * 8 + j] = colors[index].green << 8; 3022 lut_b[index * 8 + j] = colors[index].blue << 8; 3023 } 3024 } 3025 case 16: 3026 for (i = 0; i < numColors; i++) { 3027 index = indices[i]; 3028 3029 if (i <= 31) { 3030 for (j = 0; j < 8; j++) { 3031 lut_r[index * 8 + j] = colors[index].red << 8; 3032 lut_b[index * 8 + j] = colors[index].blue << 8; 3033 } 3034 } 3035 3036 for (j = 0; j < 4; j++) { 3037 lut_g[index * 4 + j] = colors[index].green << 8; 3038 } 3039 } 3040 default: 3041 for (i = 0; i < numColors; i++) { 3042 index = indices[i]; 3043 lut_r[index] = colors[index].red << 8; 3044 lut_g[index] = colors[index].green << 8; 3045 lut_b[index] = colors[index].blue << 8; 3046 } 3047 break; 3048 } 3049 3050 /* Make the change through RandR */ 3051#ifdef RANDR_12_INTERFACE 3052 if (crtc->randr_crtc) 3053 RRCrtcGammaSet(crtc->randr_crtc, lut_r, lut_g, lut_b); 3054 else 3055#endif 3056 crtc->funcs->gamma_set(crtc, lut_r, lut_g, lut_b, 256); 3057 } 3058 } 3059 3060#ifdef XF86DRI 3061 if (info->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen); 3062#endif 3063} 3064 3065static void RADEONBlockHandler(int i, pointer blockData, 3066 pointer pTimeout, pointer pReadmask) 3067{ 3068 ScreenPtr pScreen = screenInfo.screens[i]; 3069 ScrnInfoPtr pScrn = xf86Screens[i]; 3070 RADEONInfoPtr info = RADEONPTR(pScrn); 3071 3072 pScreen->BlockHandler = info->BlockHandler; 3073 (*pScreen->BlockHandler) (i, blockData, pTimeout, pReadmask); 3074 pScreen->BlockHandler = RADEONBlockHandler; 3075 3076 if (info->VideoTimerCallback) 3077 (*info->VideoTimerCallback)(pScrn, currentTime.milliseconds); 3078 3079#if defined(RENDER) && defined(USE_XAA) 3080 if(info->RenderCallback) 3081 (*info->RenderCallback)(pScrn); 3082#endif 3083 3084#ifdef USE_EXA 3085 info->engineMode = EXA_ENGINEMODE_UNKNOWN; 3086#endif 3087} 3088 3089static void 3090RADEONPointerMoved(int index, int x, int y) 3091{ 3092 ScrnInfoPtr pScrn = xf86Screens[index]; 3093 RADEONInfoPtr info = RADEONPTR(pScrn); 3094 int newX = x, newY = y; 3095 3096 switch (info->rotation) { 3097 case RR_Rotate_0: 3098 break; 3099 case RR_Rotate_90: 3100 newX = y; 3101 newY = pScrn->pScreen->width - x - 1; 3102 break; 3103 case RR_Rotate_180: 3104 newX = pScrn->pScreen->width - x - 1; 3105 newY = pScrn->pScreen->height - y - 1; 3106 break; 3107 case RR_Rotate_270: 3108 newX = pScrn->pScreen->height - y - 1; 3109 newY = x; 3110 break; 3111 } 3112 3113 (*info->PointerMoved)(index, newX, newY); 3114} 3115 3116static void 3117RADEONInitBIOSRegisters(ScrnInfoPtr pScrn) 3118{ 3119 RADEONInfoPtr info = RADEONPTR(pScrn); 3120 unsigned char *RADEONMMIO = info->MMIO; 3121 RADEONSavePtr save = info->ModeReg; 3122 3123 save->bios_0_scratch = info->SavedReg->bios_0_scratch; 3124 save->bios_1_scratch = info->SavedReg->bios_1_scratch; 3125 save->bios_2_scratch = info->SavedReg->bios_2_scratch; 3126 save->bios_3_scratch = info->SavedReg->bios_3_scratch; 3127 save->bios_4_scratch = info->SavedReg->bios_4_scratch; 3128 save->bios_5_scratch = info->SavedReg->bios_5_scratch; 3129 save->bios_6_scratch = info->SavedReg->bios_6_scratch; 3130 save->bios_7_scratch = info->SavedReg->bios_7_scratch; 3131 3132 if (info->IsAtomBios) { 3133 /* let the bios control the backlight */ 3134 save->bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; 3135 /* tell the bios not to handle mode switching */ 3136 save->bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | 3137 ATOM_S6_ACC_MODE); 3138 3139 if (info->ChipFamily >= CHIP_FAMILY_R600) { 3140 OUTREG(R600_BIOS_2_SCRATCH, save->bios_2_scratch); 3141 OUTREG(R600_BIOS_6_SCRATCH, save->bios_6_scratch); 3142 } else { 3143 OUTREG(RADEON_BIOS_2_SCRATCH, save->bios_2_scratch); 3144 OUTREG(RADEON_BIOS_6_SCRATCH, save->bios_6_scratch); 3145 } 3146 } else { 3147 /* let the bios control the backlight */ 3148 save->bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN; 3149 /* tell the bios not to handle mode switching */ 3150 save->bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS | 3151 RADEON_ACC_MODE_CHANGE); 3152 /* tell the bios a driver is loaded */ 3153 save->bios_7_scratch |= RADEON_DRV_LOADED; 3154 3155 OUTREG(RADEON_BIOS_0_SCRATCH, save->bios_0_scratch); 3156 OUTREG(RADEON_BIOS_6_SCRATCH, save->bios_6_scratch); 3157 //OUTREG(RADEON_BIOS_7_SCRATCH, save->bios_7_scratch); 3158 } 3159 3160} 3161 3162 3163/* Called at the start of each server generation. */ 3164Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, 3165 int argc, char **argv) 3166{ 3167 ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; 3168 RADEONInfoPtr info = RADEONPTR(pScrn); 3169 int hasDRI = 0; 3170#ifdef RENDER 3171 int subPixelOrder = SubPixelUnknown; 3172 char* s; 3173#endif 3174 3175 3176 info->accelOn = FALSE; 3177#ifdef USE_XAA 3178 info->accel = NULL; 3179#endif 3180#ifdef XF86DRI 3181 pScrn->fbOffset = info->frontOffset; 3182#endif 3183 3184 if (info->IsSecondary) pScrn->fbOffset = pScrn->videoRam * 1024; 3185#ifdef XF86DRI 3186 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3187 "RADEONScreenInit %lx %ld %d\n", 3188 pScrn->memPhysBase, pScrn->fbOffset, info->frontOffset); 3189#else 3190 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3191 "RADEONScreenInit %lx %ld\n", 3192 pScrn->memPhysBase, pScrn->fbOffset); 3193#endif 3194 if (!RADEONMapMem(pScrn)) return FALSE; 3195 3196#ifdef XF86DRI 3197 info->fbX = 0; 3198 info->fbY = 0; 3199#endif 3200 3201 info->PaletteSavedOnVT = FALSE; 3202 3203 info->crtc_on = FALSE; 3204 info->crtc2_on = FALSE; 3205 3206 RADEONSave(pScrn); 3207 3208 /* set initial bios scratch reg state */ 3209 RADEONInitBIOSRegisters(pScrn); 3210 3211 /* blank the outputs/crtcs */ 3212 RADEONBlank(pScrn); 3213 3214 if (info->IsMobility && !IS_AVIVO_VARIANT) { 3215 if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) { 3216 RADEONSetDynamicClock(pScrn, 1); 3217 } else { 3218 RADEONSetDynamicClock(pScrn, 0); 3219 } 3220 } else if (IS_AVIVO_VARIANT) { 3221 if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) { 3222 atombios_static_pwrmgt_setup(pScrn, 1); 3223 atombios_dyn_clk_setup(pScrn, 1); 3224 } 3225 } 3226 3227 if (IS_R300_VARIANT || IS_RV100_VARIANT) 3228 RADEONForceSomeClocks(pScrn); 3229 3230 if (info->allowColorTiling && (pScrn->virtualX > info->MaxSurfaceWidth)) { 3231 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3232 "Color tiling not supported with virtual x resolutions larger than %d, disabling\n", 3233 info->MaxSurfaceWidth); 3234 info->allowColorTiling = FALSE; 3235 } 3236 if (info->allowColorTiling) { 3237 info->tilingEnabled = (pScrn->currentMode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; 3238 } 3239 3240 /* Visual setup */ 3241 miClearVisualTypes(); 3242 if (!miSetVisualTypes(pScrn->depth, 3243 miGetDefaultVisualMask(pScrn->depth), 3244 pScrn->rgbBits, 3245 pScrn->defaultVisual)) return FALSE; 3246 miSetPixmapDepths (); 3247 3248#ifdef XF86DRI 3249 if (info->directRenderingEnabled) { 3250 MessageType from; 3251 3252 info->depthBits = pScrn->depth; 3253 3254 from = xf86GetOptValInteger(info->Options, OPTION_DEPTH_BITS, 3255 &info->depthBits) 3256 ? X_CONFIG : X_DEFAULT; 3257 3258 if (info->depthBits != 16 && info->depthBits != 24) { 3259 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3260 "Value for Option \"DepthBits\" must be 16 or 24\n"); 3261 info->depthBits = pScrn->depth; 3262 from = X_DEFAULT; 3263 } 3264 3265 xf86DrvMsg(pScrn->scrnIndex, from, 3266 "Using %d bit depth buffer\n", info->depthBits); 3267 } 3268 3269 3270 hasDRI = info->directRenderingEnabled; 3271#endif /* XF86DRI */ 3272 3273 /* Initialize the memory map, this basically calculates the values 3274 * we'll use later on for MC_FB_LOCATION & MC_AGP_LOCATION 3275 */ 3276 RADEONInitMemoryMap(pScrn); 3277 3278 /* empty the surfaces */ 3279 { 3280 unsigned char *RADEONMMIO = info->MMIO; 3281 unsigned int j; 3282 for (j = 0; j < 8; j++) { 3283 OUTREG(RADEON_SURFACE0_INFO + 16 * j, 0); 3284 OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * j, 0); 3285 OUTREG(RADEON_SURFACE0_UPPER_BOUND + 16 * j, 0); 3286 } 3287 } 3288 3289#ifdef XF86DRI 3290 /* Depth moves are disabled by default since they are extremely slow */ 3291 info->depthMoves = xf86ReturnOptValBool(info->Options, 3292 OPTION_DEPTH_MOVE, FALSE); 3293 if (info->depthMoves && info->allowColorTiling) { 3294 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Enabling depth moves\n"); 3295 } else if (info->depthMoves) { 3296 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3297 "Depth moves don't work without color tiling, disabled\n"); 3298 info->depthMoves = FALSE; 3299 } else { 3300 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3301 "Depth moves disabled by default\n"); 3302 } 3303#endif 3304 3305 /* Initial setup of surfaces */ 3306 if (info->ChipFamily < CHIP_FAMILY_R600) { 3307 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3308 "Setting up initial surfaces\n"); 3309 RADEONChangeSurfaces(pScrn); 3310 } 3311 3312 /* Memory manager setup */ 3313 3314 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3315 "Setting up accel memmap\n"); 3316 3317#ifdef USE_EXA 3318 if (info->useEXA) { 3319#ifdef XF86DRI 3320 MessageType from = X_DEFAULT; 3321 3322 if (hasDRI) { 3323 info->accelDFS = info->cardType != CARD_AGP; 3324 3325 if (xf86GetOptValInteger(info->Options, OPTION_ACCEL_DFS, 3326 &info->accelDFS)) { 3327 from = X_CONFIG; 3328 } 3329 3330 /* Reserve approx. half of offscreen memory for local textures by 3331 * default, can be overridden with Option "FBTexPercent". 3332 * Round down to a whole number of texture regions. 3333 */ 3334 info->textureSize = 50; 3335 3336 if (xf86GetOptValInteger(info->Options, OPTION_FBTEX_PERCENT, 3337 &(info->textureSize))) { 3338 if (info->textureSize < 0 || info->textureSize > 100) { 3339 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3340 "Illegal texture memory percentage: %dx, setting to default 50%%\n", 3341 info->textureSize); 3342 info->textureSize = 50; 3343 } 3344 } 3345 } 3346 3347 xf86DrvMsg(pScrn->scrnIndex, from, 3348 "%ssing accelerated EXA DownloadFromScreen hook\n", 3349 info->accelDFS ? "U" : "Not u"); 3350#endif /* XF86DRI */ 3351 3352 if (!RADEONSetupMemEXA(pScreen)) 3353 return FALSE; 3354 } 3355#endif 3356 3357#if defined(XF86DRI) && defined(USE_XAA) 3358 if (!info->useEXA && hasDRI) { 3359 info->textureSize = -1; 3360 if (xf86GetOptValInteger(info->Options, OPTION_FBTEX_PERCENT, 3361 &(info->textureSize))) { 3362 if (info->textureSize < 0 || info->textureSize > 100) { 3363 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3364 "Illegal texture memory percentage: %dx, using default behaviour\n", 3365 info->textureSize); 3366 info->textureSize = -1; 3367 } 3368 } 3369 if (!RADEONSetupMemXAA_DRI(scrnIndex, pScreen)) 3370 return FALSE; 3371 pScrn->fbOffset = info->frontOffset; 3372 } 3373#endif 3374 3375#ifdef USE_XAA 3376 if (!info->useEXA && !hasDRI && !RADEONSetupMemXAA(scrnIndex, pScreen)) 3377 return FALSE; 3378#endif 3379 3380 info->dst_pitch_offset = (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64) 3381 << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10)); 3382 3383 /* Setup DRI after visuals have been established, but before fbScreenInit is 3384 * called. fbScreenInit will eventually call the driver's InitGLXVisuals 3385 * call back. */ 3386#ifdef XF86DRI 3387 if (info->directRenderingEnabled) { 3388 /* FIXME: When we move to dynamic allocation of back and depth 3389 * buffers, we will want to revisit the following check for 3 3390 * times the virtual size of the screen below. 3391 */ 3392 int width_bytes = (pScrn->displayWidth * 3393 info->CurrentLayout.pixel_bytes); 3394 int maxy = info->FbMapSize / width_bytes; 3395 3396 if (maxy <= pScrn->virtualY * 3) { 3397 xf86DrvMsg(scrnIndex, X_ERROR, 3398 "Static buffer allocation failed. Disabling DRI.\n"); 3399 xf86DrvMsg(scrnIndex, X_ERROR, 3400 "At least %d kB of video memory needed at this " 3401 "resolution and depth.\n", 3402 (pScrn->displayWidth * pScrn->virtualY * 3403 info->CurrentLayout.pixel_bytes * 3 + 1023) / 1024); 3404 info->directRenderingEnabled = FALSE; 3405 } else { 3406 info->directRenderingEnabled = RADEONDRIScreenInit(pScreen); 3407 } 3408 } 3409 3410 /* Tell DRI about new memory map */ 3411 if (info->directRenderingEnabled && info->newMemoryMap) { 3412 if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_NEW_MEMMAP, 1) < 0) { 3413 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 3414 "[drm] failed to enable new memory map\n"); 3415 RADEONDRICloseScreen(pScreen); 3416 info->directRenderingEnabled = FALSE; 3417 } 3418 } 3419#endif 3420 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3421 "Initializing fb layer\n"); 3422 3423 if (info->r600_shadow_fb) { 3424 info->fb_shadow = xcalloc(1, 3425 pScrn->displayWidth * pScrn->virtualY * 3426 ((pScrn->bitsPerPixel + 7) >> 3)); 3427 if (info->fb_shadow == NULL) { 3428 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3429 "Failed to allocate shadow framebuffer\n"); 3430 info->r600_shadow_fb = FALSE; 3431 } else { 3432 if (!fbScreenInit(pScreen, info->fb_shadow, 3433 pScrn->virtualX, pScrn->virtualY, 3434 pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, 3435 pScrn->bitsPerPixel)) 3436 return FALSE; 3437 } 3438 } 3439 3440 if (info->r600_shadow_fb == FALSE) { 3441 /* Init fb layer */ 3442 if (!fbScreenInit(pScreen, info->FB, 3443 pScrn->virtualX, pScrn->virtualY, 3444 pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, 3445 pScrn->bitsPerPixel)) 3446 return FALSE; 3447 } 3448 3449 xf86SetBlackWhitePixels(pScreen); 3450 3451 if (pScrn->bitsPerPixel > 8) { 3452 VisualPtr visual; 3453 3454 visual = pScreen->visuals + pScreen->numVisuals; 3455 while (--visual >= pScreen->visuals) { 3456 if ((visual->class | DynamicClass) == DirectColor) { 3457 visual->offsetRed = pScrn->offset.red; 3458 visual->offsetGreen = pScrn->offset.green; 3459 visual->offsetBlue = pScrn->offset.blue; 3460 visual->redMask = pScrn->mask.red; 3461 visual->greenMask = pScrn->mask.green; 3462 visual->blueMask = pScrn->mask.blue; 3463 } 3464 } 3465 } 3466 3467 /* Must be after RGB order fixed */ 3468 fbPictureInit (pScreen, 0, 0); 3469 3470#ifdef RENDER 3471 if ((s = xf86GetOptValString(info->Options, OPTION_SUBPIXEL_ORDER))) { 3472 if (strcmp(s, "RGB") == 0) subPixelOrder = SubPixelHorizontalRGB; 3473 else if (strcmp(s, "BGR") == 0) subPixelOrder = SubPixelHorizontalBGR; 3474 else if (strcmp(s, "NONE") == 0) subPixelOrder = SubPixelNone; 3475 PictureSetSubpixelOrder (pScreen, subPixelOrder); 3476 } 3477#endif 3478 3479 pScrn->vtSema = TRUE; 3480 3481 /* xf86CrtcRotate() accesses pScrn->pScreen */ 3482 pScrn->pScreen = pScreen; 3483 3484 if (!xf86SetDesiredModes (pScrn)) 3485 return FALSE; 3486 3487 RADEONSaveScreen(pScreen, SCREEN_SAVER_ON); 3488 3489 /* Backing store setup */ 3490 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3491 "Initializing backing store\n"); 3492 miInitializeBackingStore(pScreen); 3493 xf86SetBackingStore(pScreen); 3494 3495 /* DRI finalisation */ 3496#ifdef XF86DRI 3497 if (info->directRenderingEnabled && 3498 (info->cardType==CARD_PCIE || info->cardType==CARD_PCI) && 3499 info->pKernelDRMVersion->version_minor >= 19) 3500 { 3501 if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_LOCATION, info->pciGartOffset) < 0) 3502 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3503 "[drm] failed set pci gart location\n"); 3504 3505 if (info->pKernelDRMVersion->version_minor >= 26) { 3506 if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_TABLE_SIZE, info->pciGartSize) < 0) 3507 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3508 "[drm] failed set pci gart table size\n"); 3509 } 3510 } 3511 if (info->directRenderingEnabled) { 3512 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3513 "DRI Finishing init !\n"); 3514 info->directRenderingEnabled = RADEONDRIFinishScreenInit(pScreen); 3515 } 3516 if (info->directRenderingEnabled) { 3517 /* DRI final init might have changed the memory map, we need to adjust 3518 * our local image to make sure we restore them properly on mode 3519 * changes or VT switches 3520 */ 3521 RADEONAdjustMemMapRegisters(pScrn, info->ModeReg); 3522 3523 if ((info->DispPriority == 1) && (info->cardType==CARD_AGP)) { 3524 /* we need to re-calculate bandwidth because of AGPMode difference. */ 3525 RADEONInitDispBandwidth(pScrn); 3526 } 3527 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n"); 3528 3529 /* we might already be in tiled mode, tell drm about it */ 3530 if (info->directRenderingEnabled && info->tilingEnabled) { 3531 if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0) 3532 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3533 "[drm] failed changing tiling status\n"); 3534 } 3535 } else { 3536 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 3537 "Direct rendering disabled\n"); 3538 } 3539#endif 3540 3541 /* Make sure surfaces are allright since DRI setup may have changed them */ 3542 if (info->ChipFamily < CHIP_FAMILY_R600) { 3543 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3544 "Setting up final surfaces\n"); 3545 3546 RADEONChangeSurfaces(pScrn); 3547 } 3548 3549 3550 /* Enable aceleration */ 3551 if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { 3552 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3553 "Initializing Acceleration\n"); 3554 if (RADEONAccelInit(pScreen)) { 3555 xf86DrvMsg(scrnIndex, X_INFO, "Acceleration enabled\n"); 3556 info->accelOn = TRUE; 3557 } else { 3558 xf86DrvMsg(scrnIndex, X_ERROR, 3559 "Acceleration initialization failed\n"); 3560 xf86DrvMsg(scrnIndex, X_INFO, "Acceleration disabled\n"); 3561 info->accelOn = FALSE; 3562 } 3563 } else { 3564 xf86DrvMsg(scrnIndex, X_INFO, "Acceleration disabled\n"); 3565 info->accelOn = FALSE; 3566 } 3567 3568 /* Init DPMS */ 3569 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3570 "Initializing DPMS\n"); 3571 xf86DPMSInit(pScreen, xf86DPMSSet, 0); 3572 3573 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3574 "Initializing Cursor\n"); 3575 3576 /* Set Silken Mouse */ 3577 xf86SetSilkenMouse(pScreen); 3578 3579 /* Cursor setup */ 3580 miDCInitialize(pScreen, xf86GetPointerScreenFuncs()); 3581 3582 /* Hardware cursor setup */ 3583 if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) { 3584 if (RADEONCursorInit(pScreen)) { 3585#ifdef USE_XAA 3586 if (!info->useEXA) { 3587 int width, height; 3588 3589 if (xf86QueryLargestOffscreenArea(pScreen, &width, &height, 3590 0, 0, 0)) { 3591 xf86DrvMsg(scrnIndex, X_INFO, 3592 "Largest offscreen area available: %d x %d\n", 3593 width, height); 3594 } 3595 } 3596#endif /* USE_XAA */ 3597 } else { 3598 xf86DrvMsg(scrnIndex, X_ERROR, 3599 "Hardware cursor initialization failed\n"); 3600 xf86DrvMsg(scrnIndex, X_INFO, "Using software cursor\n"); 3601 } 3602 } else { 3603 xf86DrvMsg(scrnIndex, X_INFO, "Using software cursor\n"); 3604 } 3605 3606 /* DGA setup */ 3607 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3608 "Initializing DGA\n"); 3609 RADEONDGAInit(pScreen); 3610 3611 /* Init Xv */ 3612 if (info->ChipFamily < CHIP_FAMILY_R600) { 3613 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3614 "Initializing Xv\n"); 3615 RADEONInitVideo(pScreen); 3616 } 3617 3618 if (info->r600_shadow_fb == TRUE) { 3619 if (!shadowSetup(pScreen)) { 3620 return FALSE; 3621 } 3622 } 3623 3624 /* Provide SaveScreen & wrap BlockHandler and CloseScreen */ 3625 /* Wrap CloseScreen */ 3626 info->CloseScreen = pScreen->CloseScreen; 3627 pScreen->CloseScreen = RADEONCloseScreen; 3628 pScreen->SaveScreen = RADEONSaveScreen; 3629 info->BlockHandler = pScreen->BlockHandler; 3630 pScreen->BlockHandler = RADEONBlockHandler; 3631 info->CreateScreenResources = pScreen->CreateScreenResources; 3632 pScreen->CreateScreenResources = RADEONCreateScreenResources; 3633 3634 if (!xf86CrtcScreenInit (pScreen)) 3635 return FALSE; 3636 3637 /* Wrap pointer motion to flip touch screen around */ 3638 info->PointerMoved = pScrn->PointerMoved; 3639 pScrn->PointerMoved = RADEONPointerMoved; 3640 3641 /* Colormap setup */ 3642 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3643 "Initializing color map\n"); 3644 if (!miCreateDefColormap(pScreen)) return FALSE; 3645 if (!xf86HandleColormaps(pScreen, 256, info->dac6bits ? 6 : 8, 3646 RADEONLoadPalette, NULL, 3647 CMAP_PALETTED_TRUECOLOR 3648#if 0 /* This option messes up text mode! (eich@suse.de) */ 3649 | CMAP_LOAD_EVEN_IF_OFFSCREEN 3650#endif 3651 | CMAP_RELOAD_ON_MODE_SWITCH)) return FALSE; 3652 3653 /* Note unused options */ 3654 if (serverGeneration == 1) 3655 xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options); 3656 3657 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3658 "RADEONScreenInit finished\n"); 3659 3660 return TRUE; 3661} 3662 3663/* Write memory mapping registers */ 3664void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, 3665 RADEONSavePtr restore) 3666{ 3667 RADEONInfoPtr info = RADEONPTR(pScrn); 3668 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 3669 unsigned char *RADEONMMIO = info->MMIO; 3670 int timeout; 3671 uint32_t mc_fb_loc, mc_agp_loc, mc_agp_loc_hi; 3672 3673 radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &mc_fb_loc, 3674 &mc_agp_loc, &mc_agp_loc_hi); 3675 3676 if (info->IsSecondary) 3677 return; 3678 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3679 "RADEONRestoreMemMapRegisters() : \n"); 3680 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3681 " MC_FB_LOCATION : 0x%08x 0x%08x\n", 3682 (unsigned)restore->mc_fb_location, (unsigned int)mc_fb_loc); 3683 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3684 " MC_AGP_LOCATION : 0x%08x\n", 3685 (unsigned)restore->mc_agp_location); 3686 3687 if (IS_AVIVO_VARIANT) { 3688 3689 if (mc_fb_loc != restore->mc_fb_location || 3690 mc_agp_loc != restore->mc_agp_location) { 3691 uint32_t tmp; 3692 3693 RADEONWaitForIdleMMIO(pScrn); 3694 3695 OUTREG(AVIVO_D1VGA_CONTROL, INREG(AVIVO_D1VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 3696 OUTREG(AVIVO_D2VGA_CONTROL, INREG(AVIVO_D2VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 3697 3698 /* Stop display & memory access */ 3699 tmp = INREG(AVIVO_D1CRTC_CONTROL); 3700 OUTREG(AVIVO_D1CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN); 3701 3702 tmp = INREG(AVIVO_D2CRTC_CONTROL); 3703 OUTREG(AVIVO_D2CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN); 3704 3705 tmp = INREG(AVIVO_D2CRTC_CONTROL); 3706 3707 usleep(10000); 3708 timeout = 0; 3709 while (!(avivo_get_mc_idle(pScrn))) { 3710 if (++timeout > 1000000) { 3711 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3712 "Timeout trying to update memory controller settings !\n"); 3713 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3714 "You will probably crash now ... \n"); 3715 /* Nothing we can do except maybe try to kill the server, 3716 * let's wait 2 seconds to leave the above message a chance 3717 * to maybe hit the disk and continue trying to setup despite 3718 * the MC being non-idle 3719 */ 3720 usleep(2000000); 3721 } 3722 usleep(10); 3723 } 3724 3725 radeon_write_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, 3726 restore->mc_fb_location, 3727 restore->mc_agp_location, 3728 restore->mc_agp_location_hi); 3729 3730 if (info->ChipFamily < CHIP_FAMILY_R600) { 3731 OUTREG(AVIVO_HDP_FB_LOCATION, restore->mc_fb_location); 3732 } else { 3733 OUTREG(R600_HDP_NONSURFACE_BASE, (restore->mc_fb_location << 16) & 0xff0000); 3734 } 3735 3736 /* Reset the engine and HDP */ 3737 RADEONEngineReset(pScrn); 3738 } 3739 } else { 3740 3741 /* Write memory mapping registers only if their value change 3742 * since we must ensure no access is done while they are 3743 * reprogrammed 3744 */ 3745 if (mc_fb_loc != restore->mc_fb_location || 3746 mc_agp_loc != restore->mc_agp_location) { 3747 uint32_t crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl; 3748 uint32_t old_mc_status, status_idle; 3749 3750 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3751 " Map Changed ! Applying ...\n"); 3752 3753 /* Make sure engine is idle. We assume the CCE is stopped 3754 * at this point 3755 */ 3756 RADEONWaitForIdleMMIO(pScrn); 3757 3758 if (info->IsIGP) 3759 goto igp_no_mcfb; 3760 3761 /* Capture MC_STATUS in case things go wrong ... */ 3762 old_mc_status = INREG(RADEON_MC_STATUS); 3763 3764 /* Stop display & memory access */ 3765 ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL); 3766 OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE); 3767 crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL); 3768 OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS); 3769 crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); 3770 RADEONWaitForVerticalSync(pScrn); 3771 OUTREG(RADEON_CRTC_GEN_CNTL, 3772 (crtc_gen_cntl 3773 & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) 3774 | RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN); 3775 3776 if (pRADEONEnt->HasCRTC2) { 3777 crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); 3778 RADEONWaitForVerticalSync2(pScrn); 3779 OUTREG(RADEON_CRTC2_GEN_CNTL, 3780 (crtc2_gen_cntl 3781 & ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) 3782 | RADEON_CRTC2_DISP_REQ_EN_B); 3783 } 3784 3785 /* Make sure the chip settles down (paranoid !) */ 3786 usleep(100000); 3787 3788 /* Wait for MC idle */ 3789 if (IS_R300_VARIANT) 3790 status_idle = R300_MC_IDLE; 3791 else 3792 status_idle = RADEON_MC_IDLE; 3793 3794 timeout = 0; 3795 while (!(INREG(RADEON_MC_STATUS) & status_idle)) { 3796 if (++timeout > 1000000) { 3797 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3798 "Timeout trying to update memory controller settings !\n"); 3799 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3800 "MC_STATUS = 0x%08x (on entry = 0x%08x)\n", 3801 (unsigned int)INREG(RADEON_MC_STATUS), (unsigned int)old_mc_status); 3802 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3803 "You will probably crash now ... \n"); 3804 /* Nothing we can do except maybe try to kill the server, 3805 * let's wait 2 seconds to leave the above message a chance 3806 * to maybe hit the disk and continue trying to setup despite 3807 * the MC being non-idle 3808 */ 3809 usleep(2000000); 3810 } 3811 usleep(10); 3812 } 3813 3814 /* Update maps, first clearing out AGP to make sure we don't get 3815 * a temporary overlap 3816 */ 3817 OUTREG(RADEON_MC_AGP_LOCATION, 0xfffffffc); 3818 OUTREG(RADEON_MC_FB_LOCATION, restore->mc_fb_location); 3819 radeon_write_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, restore->mc_fb_location, 3820 0xfffffffc, 0); 3821 igp_no_mcfb: 3822 radeon_write_mc_fb_agp_location(pScrn, LOC_AGP, 0, 3823 restore->mc_agp_location, 0); 3824 /* Make sure map fully reached the chip */ 3825 (void)INREG(RADEON_MC_FB_LOCATION); 3826 3827 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3828 " Map applied, resetting engine ...\n"); 3829 3830 /* Reset the engine and HDP */ 3831 RADEONEngineReset(pScrn); 3832 3833 /* Make sure we have sane offsets before re-enabling the CRTCs, disable 3834 * stereo, clear offsets, and wait for offsets to catch up with hw 3835 */ 3836 3837 OUTREG(RADEON_CRTC_OFFSET_CNTL, RADEON_CRTC_OFFSET_FLIP_CNTL); 3838 OUTREG(RADEON_CRTC_OFFSET, 0); 3839 OUTREG(RADEON_CUR_OFFSET, 0); 3840 timeout = 0; 3841 while(INREG(RADEON_CRTC_OFFSET) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) { 3842 if (timeout++ > 1000000) { 3843 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3844 "Timeout waiting for CRTC offset to update !\n"); 3845 break; 3846 } 3847 usleep(1000); 3848 } 3849 if (pRADEONEnt->HasCRTC2) { 3850 OUTREG(RADEON_CRTC2_OFFSET_CNTL, RADEON_CRTC2_OFFSET_FLIP_CNTL); 3851 OUTREG(RADEON_CRTC2_OFFSET, 0); 3852 OUTREG(RADEON_CUR2_OFFSET, 0); 3853 timeout = 0; 3854 while(INREG(RADEON_CRTC2_OFFSET) & RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET) { 3855 if (timeout++ > 1000000) { 3856 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3857 "Timeout waiting for CRTC2 offset to update !\n"); 3858 break; 3859 } 3860 usleep(1000); 3861 } 3862 } 3863 } 3864 3865 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3866 "Updating display base addresses...\n"); 3867 3868 OUTREG(RADEON_DISPLAY_BASE_ADDR, restore->display_base_addr); 3869 if (pRADEONEnt->HasCRTC2) 3870 OUTREG(RADEON_DISPLAY2_BASE_ADDR, restore->display2_base_addr); 3871 OUTREG(RADEON_OV0_BASE_ADDR, restore->ov0_base_addr); 3872 (void)INREG(RADEON_OV0_BASE_ADDR); 3873 3874 /* More paranoia delays, wait 100ms */ 3875 usleep(100000); 3876 3877 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3878 "Memory map updated.\n"); 3879 } 3880} 3881 3882#ifdef XF86DRI 3883static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) 3884{ 3885 RADEONInfoPtr info = RADEONPTR(pScrn); 3886 uint32_t fb, agp, agp_hi; 3887 int changed = 0; 3888 3889 if (info->IsSecondary) 3890 return; 3891 3892 radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &fb, &agp, &agp_hi); 3893 3894 if (fb != save->mc_fb_location || agp != save->mc_agp_location || 3895 agp_hi != save->mc_agp_location_hi) 3896 changed = 1; 3897 3898 if (changed) { 3899 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 3900 "DRI init changed memory map, adjusting ...\n"); 3901 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 3902 " MC_FB_LOCATION was: 0x%08lx is: 0x%08lx\n", 3903 (long unsigned int)info->mc_fb_location, (long unsigned int)fb); 3904 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 3905 " MC_AGP_LOCATION was: 0x%08lx is: 0x%08lx\n", 3906 (long unsigned int)info->mc_agp_location, (long unsigned int)agp); 3907 info->mc_fb_location = fb; 3908 info->mc_agp_location = agp; 3909 if (info->ChipFamily >= CHIP_FAMILY_R600) 3910 info->fbLocation = (info->mc_fb_location & 0xffff) << 24; 3911 else 3912 info->fbLocation = (info->mc_fb_location & 0xffff) << 16; 3913 3914 info->dst_pitch_offset = 3915 (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64) 3916 << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10)); 3917 RADEONInitMemMapRegisters(pScrn, save, info); 3918 RADEONRestoreMemMapRegisters(pScrn, save); 3919 } 3920 3921#ifdef USE_EXA 3922 if (info->accelDFS) 3923 { 3924 drmRadeonGetParam gp; 3925 int gart_base; 3926 3927 memset(&gp, 0, sizeof(gp)); 3928 gp.param = RADEON_PARAM_GART_BASE; 3929 gp.value = &gart_base; 3930 3931 if (drmCommandWriteRead(info->drmFD, DRM_RADEON_GETPARAM, &gp, 3932 sizeof(gp)) < 0) { 3933 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3934 "Failed to determine GART area MC location, not using " 3935 "accelerated DownloadFromScreen hook!\n"); 3936 info->accelDFS = FALSE; 3937 } else { 3938 info->gartLocation = gart_base; 3939 } 3940 } 3941#endif /* USE_EXA */ 3942} 3943#endif 3944 3945/* restore original surface info (for fb console). */ 3946static void RADEONRestoreSurfaces(ScrnInfoPtr pScrn, RADEONSavePtr restore) 3947{ 3948 RADEONInfoPtr info = RADEONPTR(pScrn); 3949 unsigned char *RADEONMMIO = info->MMIO; 3950 unsigned int surfnr; 3951 3952 for ( surfnr = 0; surfnr < 8; surfnr++ ) { 3953 OUTREG(RADEON_SURFACE0_INFO + 16 * surfnr, restore->surfaces[surfnr][0]); 3954 OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * surfnr, restore->surfaces[surfnr][1]); 3955 OUTREG(RADEON_SURFACE0_UPPER_BOUND + 16 * surfnr, restore->surfaces[surfnr][2]); 3956 } 3957} 3958 3959/* save original surface info (for fb console). */ 3960static void RADEONSaveSurfaces(ScrnInfoPtr pScrn, RADEONSavePtr save) 3961{ 3962 RADEONInfoPtr info = RADEONPTR(pScrn); 3963 unsigned char *RADEONMMIO = info->MMIO; 3964 unsigned int surfnr; 3965 3966 for ( surfnr = 0; surfnr < 8; surfnr++ ) { 3967 save->surfaces[surfnr][0] = INREG(RADEON_SURFACE0_INFO + 16 * surfnr); 3968 save->surfaces[surfnr][1] = INREG(RADEON_SURFACE0_LOWER_BOUND + 16 * surfnr); 3969 save->surfaces[surfnr][2] = INREG(RADEON_SURFACE0_UPPER_BOUND + 16 * surfnr); 3970 } 3971} 3972 3973void RADEONChangeSurfaces(ScrnInfoPtr pScrn) 3974{ 3975 /* the idea here is to only set up front buffer as tiled, and back/depth buffer when needed. 3976 Everything else is left as untiled. This means we need to use eplicit src/dst pitch control 3977 when blitting, based on the src/target address, and can no longer use a default offset. 3978 But OTOH we don't need to dynamically change surfaces (for xv for instance), and some 3979 ugly offset / fb reservation (cursor) is gone. And as a bonus, everything actually works... 3980 For simplicity, just always update everything (just let the ioctl fail - could do better). 3981 All surface addresses are relative to RADEON_MC_FB_LOCATION */ 3982 3983 RADEONInfoPtr info = RADEONPTR(pScrn); 3984 int cpp = info->CurrentLayout.pixel_bytes; 3985 /* depth/front/back pitch must be identical (and the same as displayWidth) */ 3986 int width_bytes = pScrn->displayWidth * cpp; 3987 int bufferSize = ((((pScrn->virtualY + 15) & ~15) * width_bytes 3988 + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN); 3989 unsigned int color_pattern, swap_pattern; 3990 3991 if (!info->allowColorTiling) 3992 return; 3993 3994 swap_pattern = 0; 3995#if X_BYTE_ORDER == X_BIG_ENDIAN 3996 switch (pScrn->bitsPerPixel) { 3997 case 16: 3998 swap_pattern = RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; 3999 break; 4000 4001 case 32: 4002 swap_pattern = RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; 4003 break; 4004 } 4005#endif 4006 if (info->ChipFamily < CHIP_FAMILY_R200) { 4007 color_pattern = RADEON_SURF_TILE_COLOR_MACRO; 4008 } else if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { 4009 color_pattern = R300_SURF_TILE_COLOR_MACRO; 4010 } else { 4011 color_pattern = R200_SURF_TILE_COLOR_MACRO; 4012 } 4013#ifdef XF86DRI 4014 if (info->directRenderingInited) { 4015 drmRadeonSurfaceFree drmsurffree; 4016 drmRadeonSurfaceAlloc drmsurfalloc; 4017 int retvalue; 4018 int depthCpp = (info->depthBits - 8) / 4; 4019 int depth_width_bytes = pScrn->displayWidth * depthCpp; 4020 int depthBufferSize = ((((pScrn->virtualY + 15) & ~15) * depth_width_bytes 4021 + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN); 4022 unsigned int depth_pattern; 4023 4024 drmsurffree.address = info->frontOffset; 4025 retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_FREE, 4026 &drmsurffree, sizeof(drmsurffree)); 4027 4028 if (!((info->ChipFamily == CHIP_FAMILY_RV100) || 4029 (info->ChipFamily == CHIP_FAMILY_RS100) || 4030 (info->ChipFamily == CHIP_FAMILY_RS200))) { 4031 drmsurffree.address = info->depthOffset; 4032 retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_FREE, 4033 &drmsurffree, sizeof(drmsurffree)); 4034 } 4035 4036 if (!info->noBackBuffer) { 4037 drmsurffree.address = info->backOffset; 4038 retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_FREE, 4039 &drmsurffree, sizeof(drmsurffree)); 4040 } 4041 4042 drmsurfalloc.size = bufferSize; 4043 drmsurfalloc.address = info->frontOffset; 4044 drmsurfalloc.flags = swap_pattern; 4045 4046 if (info->tilingEnabled) { 4047 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) 4048 drmsurfalloc.flags |= (width_bytes / 8) | color_pattern; 4049 else 4050 drmsurfalloc.flags |= (width_bytes / 16) | color_pattern; 4051 } 4052 retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_ALLOC, 4053 &drmsurfalloc, sizeof(drmsurfalloc)); 4054 if (retvalue < 0) 4055 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4056 "drm: could not allocate surface for front buffer!\n"); 4057 4058 if ((info->have3DWindows) && (!info->noBackBuffer)) { 4059 drmsurfalloc.address = info->backOffset; 4060 retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_ALLOC, 4061 &drmsurfalloc, sizeof(drmsurfalloc)); 4062 if (retvalue < 0) 4063 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4064 "drm: could not allocate surface for back buffer!\n"); 4065 } 4066 4067 if (info->ChipFamily < CHIP_FAMILY_R200) { 4068 if (depthCpp == 2) 4069 depth_pattern = RADEON_SURF_TILE_DEPTH_16BPP; 4070 else 4071 depth_pattern = RADEON_SURF_TILE_DEPTH_32BPP; 4072 } else if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { 4073 if (depthCpp == 2) 4074 depth_pattern = R300_SURF_TILE_COLOR_MACRO; 4075 else 4076 depth_pattern = R300_SURF_TILE_COLOR_MACRO | R300_SURF_TILE_DEPTH_32BPP; 4077 } else { 4078 if (depthCpp == 2) 4079 depth_pattern = R200_SURF_TILE_DEPTH_16BPP; 4080 else 4081 depth_pattern = R200_SURF_TILE_DEPTH_32BPP; 4082 } 4083 4084 /* rv100 and probably the derivative igps don't have depth tiling on all the time? */ 4085 if (info->have3DWindows && 4086 (!((info->ChipFamily == CHIP_FAMILY_RV100) || 4087 (info->ChipFamily == CHIP_FAMILY_RS100) || 4088 (info->ChipFamily == CHIP_FAMILY_RS200)))) { 4089 drmRadeonSurfaceAlloc drmsurfalloc; 4090 drmsurfalloc.size = depthBufferSize; 4091 drmsurfalloc.address = info->depthOffset; 4092 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) 4093 drmsurfalloc.flags = swap_pattern | (depth_width_bytes / 8) | depth_pattern; 4094 else 4095 drmsurfalloc.flags = swap_pattern | (depth_width_bytes / 16) | depth_pattern; 4096 retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_ALLOC, 4097 &drmsurfalloc, sizeof(drmsurfalloc)); 4098 if (retvalue < 0) 4099 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4100 "drm: could not allocate surface for depth buffer!\n"); 4101 } 4102 } 4103 else 4104#endif 4105 { 4106 unsigned int surf_info = swap_pattern; 4107 unsigned char *RADEONMMIO = info->MMIO; 4108 /* we don't need anything like WaitForFifo, no? */ 4109 if (info->tilingEnabled) { 4110 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) 4111 surf_info |= (width_bytes / 8) | color_pattern; 4112 else 4113 surf_info |= (width_bytes / 16) | color_pattern; 4114 } 4115 OUTREG(RADEON_SURFACE0_INFO, surf_info); 4116 OUTREG(RADEON_SURFACE0_LOWER_BOUND, 0); 4117 OUTREG(RADEON_SURFACE0_UPPER_BOUND, bufferSize - 1); 4118/* xf86DrvMsg(pScrn->scrnIndex, X_INFO, 4119 "surface0 set to %x, LB 0x%x UB 0x%x\n", 4120 surf_info, 0, bufferSize - 1024);*/ 4121 } 4122 4123 /* Update surface images */ 4124 if (info->ChipFamily < CHIP_FAMILY_R600) 4125 RADEONSaveSurfaces(pScrn, info->ModeReg); 4126} 4127 4128/* Read memory map */ 4129static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) 4130{ 4131 RADEONInfoPtr info = RADEONPTR(pScrn); 4132 unsigned char *RADEONMMIO = info->MMIO; 4133 4134 radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &save->mc_fb_location, 4135 &save->mc_agp_location, &save->mc_agp_location_hi); 4136 4137 if (!IS_AVIVO_VARIANT) { 4138 save->display_base_addr = INREG(RADEON_DISPLAY_BASE_ADDR); 4139 save->display2_base_addr = INREG(RADEON_DISPLAY2_BASE_ADDR); 4140 save->ov0_base_addr = INREG(RADEON_OV0_BASE_ADDR); 4141 } 4142} 4143 4144 4145#if 0 4146/* Read palette data */ 4147static void RADEONSavePalette(ScrnInfoPtr pScrn, RADEONSavePtr save) 4148{ 4149 RADEONInfoPtr info = RADEONPTR(pScrn); 4150 unsigned char *RADEONMMIO = info->MMIO; 4151 int i; 4152 4153#ifdef ENABLE_FLAT_PANEL 4154 /* Select palette 0 (main CRTC) if using FP-enabled chip */ 4155 /* if (info->Port1 == MT_DFP) PAL_SELECT(1); */ 4156#endif 4157 PAL_SELECT(1); 4158 INPAL_START(0); 4159 for (i = 0; i < 256; i++) save->palette2[i] = INPAL_NEXT(); 4160 PAL_SELECT(0); 4161 INPAL_START(0); 4162 for (i = 0; i < 256; i++) save->palette[i] = INPAL_NEXT(); 4163 save->palette_valid = TRUE; 4164} 4165#endif 4166 4167static void 4168avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) 4169{ 4170 RADEONInfoPtr info = RADEONPTR(pScrn); 4171 unsigned char *RADEONMMIO = info->MMIO; 4172 struct avivo_state *state = &save->avivo; 4173 int i, j; 4174 4175 // state->vga_memory_base = INREG(AVIVO_VGA_MEMORY_BASE); 4176 // state->vga_fb_start = INREG(AVIVO_VGA_FB_START); 4177 state->vga1_cntl = INREG(AVIVO_D1VGA_CONTROL); 4178 state->vga2_cntl = INREG(AVIVO_D2VGA_CONTROL); 4179 4180 state->crtc_master_en = INREG(AVIVO_DC_CRTC_MASTER_EN); 4181 state->crtc_tv_control = INREG(AVIVO_DC_CRTC_TV_CONTROL); 4182 4183 state->pll1.ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC); 4184 state->pll1.ref_div = INREG(AVIVO_EXT1_PPLL_REF_DIV); 4185 state->pll1.fb_div = INREG(AVIVO_EXT1_PPLL_FB_DIV); 4186 state->pll1.post_div_src = INREG(AVIVO_EXT1_PPLL_POST_DIV_SRC); 4187 state->pll1.post_div = INREG(AVIVO_EXT1_PPLL_POST_DIV); 4188 state->pll1.ext_ppll_cntl = INREG(AVIVO_EXT1_PPLL_CNTL); 4189 state->pll1.pll_cntl = INREG(AVIVO_P1PLL_CNTL); 4190 state->pll1.int_ss_cntl = INREG(AVIVO_P1PLL_INT_SS_CNTL); 4191 4192 state->pll2.ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC); 4193 state->pll2.ref_div = INREG(AVIVO_EXT2_PPLL_REF_DIV); 4194 state->pll2.fb_div = INREG(AVIVO_EXT2_PPLL_FB_DIV); 4195 state->pll2.post_div_src = INREG(AVIVO_EXT2_PPLL_POST_DIV_SRC); 4196 state->pll2.post_div = INREG(AVIVO_EXT2_PPLL_POST_DIV); 4197 state->pll2.ext_ppll_cntl = INREG(AVIVO_EXT2_PPLL_CNTL); 4198 state->pll2.pll_cntl = INREG(AVIVO_P2PLL_CNTL); 4199 state->pll2.int_ss_cntl = INREG(AVIVO_P2PLL_INT_SS_CNTL); 4200 4201 state->crtc1.pll_source = INREG(AVIVO_PCLK_CRTC1_CNTL); 4202 4203 state->crtc1.h_total = INREG(AVIVO_D1CRTC_H_TOTAL); 4204 state->crtc1.h_blank_start_end = INREG(AVIVO_D1CRTC_H_BLANK_START_END); 4205 state->crtc1.h_sync_a = INREG(AVIVO_D1CRTC_H_SYNC_A); 4206 state->crtc1.h_sync_a_cntl = INREG(AVIVO_D1CRTC_H_SYNC_A_CNTL); 4207 state->crtc1.h_sync_b = INREG(AVIVO_D1CRTC_H_SYNC_B); 4208 state->crtc1.h_sync_b_cntl = INREG(AVIVO_D1CRTC_H_SYNC_B_CNTL); 4209 4210 state->crtc1.v_total = INREG(AVIVO_D1CRTC_V_TOTAL); 4211 state->crtc1.v_blank_start_end = INREG(AVIVO_D1CRTC_V_BLANK_START_END); 4212 state->crtc1.v_sync_a = INREG(AVIVO_D1CRTC_V_SYNC_A); 4213 state->crtc1.v_sync_a_cntl = INREG(AVIVO_D1CRTC_V_SYNC_A_CNTL); 4214 state->crtc1.v_sync_b = INREG(AVIVO_D1CRTC_V_SYNC_B); 4215 state->crtc1.v_sync_b_cntl = INREG(AVIVO_D1CRTC_V_SYNC_B_CNTL); 4216 4217 state->crtc1.control = INREG(AVIVO_D1CRTC_CONTROL); 4218 state->crtc1.blank_control = INREG(AVIVO_D1CRTC_BLANK_CONTROL); 4219 state->crtc1.interlace_control = INREG(AVIVO_D1CRTC_INTERLACE_CONTROL); 4220 state->crtc1.stereo_control = INREG(AVIVO_D1CRTC_STEREO_CONTROL); 4221 4222 state->crtc1.cursor_control = INREG(AVIVO_D1CUR_CONTROL); 4223 4224 state->grph1.enable = INREG(AVIVO_D1GRPH_ENABLE); 4225 state->grph1.control = INREG(AVIVO_D1GRPH_CONTROL); 4226 state->grph1.control = INREG(AVIVO_D1GRPH_CONTROL); 4227 state->grph1.prim_surf_addr = INREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS); 4228 state->grph1.sec_surf_addr = INREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS); 4229 state->grph1.pitch = INREG(AVIVO_D1GRPH_PITCH); 4230 state->grph1.x_offset = INREG(AVIVO_D1GRPH_SURFACE_OFFSET_X); 4231 state->grph1.y_offset = INREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y); 4232 state->grph1.x_start = INREG(AVIVO_D1GRPH_X_START); 4233 state->grph1.y_start = INREG(AVIVO_D1GRPH_Y_START); 4234 state->grph1.x_end = INREG(AVIVO_D1GRPH_X_END); 4235 state->grph1.y_end = INREG(AVIVO_D1GRPH_Y_END); 4236 4237 state->grph1.viewport_start = INREG(AVIVO_D1MODE_VIEWPORT_START); 4238 state->grph1.viewport_size = INREG(AVIVO_D1MODE_VIEWPORT_SIZE); 4239 4240 state->crtc2.pll_source = INREG(AVIVO_PCLK_CRTC2_CNTL); 4241 4242 state->crtc2.h_total = INREG(AVIVO_D2CRTC_H_TOTAL); 4243 state->crtc2.h_blank_start_end = INREG(AVIVO_D2CRTC_H_BLANK_START_END); 4244 state->crtc2.h_sync_a = INREG(AVIVO_D2CRTC_H_SYNC_A); 4245 state->crtc2.h_sync_a_cntl = INREG(AVIVO_D2CRTC_H_SYNC_A_CNTL); 4246 state->crtc2.h_sync_b = INREG(AVIVO_D2CRTC_H_SYNC_B); 4247 state->crtc2.h_sync_b_cntl = INREG(AVIVO_D2CRTC_H_SYNC_B_CNTL); 4248 4249 state->crtc2.v_total = INREG(AVIVO_D2CRTC_V_TOTAL); 4250 state->crtc2.v_blank_start_end = INREG(AVIVO_D2CRTC_V_BLANK_START_END); 4251 state->crtc2.v_sync_a = INREG(AVIVO_D2CRTC_V_SYNC_A); 4252 state->crtc2.v_sync_a_cntl = INREG(AVIVO_D2CRTC_V_SYNC_A_CNTL); 4253 state->crtc2.v_sync_b = INREG(AVIVO_D2CRTC_V_SYNC_B); 4254 state->crtc2.v_sync_b_cntl = INREG(AVIVO_D2CRTC_V_SYNC_B_CNTL); 4255 4256 state->crtc2.control = INREG(AVIVO_D2CRTC_CONTROL); 4257 state->crtc2.blank_control = INREG(AVIVO_D2CRTC_BLANK_CONTROL); 4258 state->crtc2.interlace_control = INREG(AVIVO_D2CRTC_INTERLACE_CONTROL); 4259 state->crtc2.stereo_control = INREG(AVIVO_D2CRTC_STEREO_CONTROL); 4260 4261 state->crtc2.cursor_control = INREG(AVIVO_D2CUR_CONTROL); 4262 4263 state->grph2.enable = INREG(AVIVO_D2GRPH_ENABLE); 4264 state->grph2.control = INREG(AVIVO_D2GRPH_CONTROL); 4265 state->grph2.control = INREG(AVIVO_D2GRPH_CONTROL); 4266 state->grph2.prim_surf_addr = INREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS); 4267 state->grph2.sec_surf_addr = INREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS); 4268 state->grph2.pitch = INREG(AVIVO_D2GRPH_PITCH); 4269 state->grph2.x_offset = INREG(AVIVO_D2GRPH_SURFACE_OFFSET_X); 4270 state->grph2.y_offset = INREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y); 4271 state->grph2.x_start = INREG(AVIVO_D2GRPH_X_START); 4272 state->grph2.y_start = INREG(AVIVO_D2GRPH_Y_START); 4273 state->grph2.x_end = INREG(AVIVO_D2GRPH_X_END); 4274 state->grph2.y_end = INREG(AVIVO_D2GRPH_Y_END); 4275 4276 state->grph2.viewport_start = INREG(AVIVO_D2MODE_VIEWPORT_START); 4277 state->grph2.viewport_size = INREG(AVIVO_D2MODE_VIEWPORT_SIZE); 4278 4279 if (IS_DCE3_VARIANT) { 4280 /* save DVOA regs */ 4281 state->dvoa[0] = INREG(0x7080); 4282 state->dvoa[1] = INREG(0x7084); 4283 state->dvoa[2] = INREG(0x708c); 4284 state->dvoa[3] = INREG(0x7090); 4285 state->dvoa[4] = INREG(0x7094); 4286 state->dvoa[5] = INREG(0x70ac); 4287 state->dvoa[6] = INREG(0x70b0); 4288 4289 j = 0; 4290 /* save DAC regs */ 4291 for (i = 0x7000; i <= 0x7040; i += 4) { 4292 state->daca[j] = INREG(i); 4293 state->dacb[j] = INREG(i + 0x100); 4294 j++; 4295 } 4296 for (i = 0x7058; i <= 0x7060; i += 4) { 4297 state->daca[j] = INREG(i); 4298 state->dacb[j] = INREG(i + 0x100); 4299 j++; 4300 } 4301 for (i = 0x7068; i <= 0x706c; i += 4) { 4302 state->daca[j] = INREG(i); 4303 state->dacb[j] = INREG(i + 0x100); 4304 j++; 4305 } 4306 for (i = 0x7ef0; i <= 0x7ef8; i += 4) { 4307 state->daca[j] = INREG(i); 4308 state->dacb[j] = INREG(i + 0x100); 4309 j++; 4310 } 4311 state->daca[j] = INREG(0x7050); 4312 state->dacb[j] = INREG(0x7050 + 0x100); 4313 4314 j = 0; 4315 /* save FMT regs */ 4316 for (i = 0x6700; i <= 0x6744; i += 4) { 4317 state->fmt1[j] = INREG(i); 4318 state->fmt2[j] = INREG(i + 0x800); 4319 j++; 4320 } 4321 4322 j = 0; 4323 /* save DIG regs */ 4324 for (i = 0x75a0; i <= 0x75e0; i += 4) { 4325 state->dig1[j] = INREG(i); 4326 state->dig2[j] = INREG(i + 0x400); 4327 j++; 4328 } 4329 for (i = 0x75e8; i <= 0x75ec; i += 4) { 4330 state->dig1[j] = INREG(i); 4331 state->dig2[j] = INREG(i + 0x400); 4332 j++; 4333 } 4334 4335 j = 0; 4336 /* save HDMI regs */ 4337 for (i = 0x7400; i <= 0x741c; i += 4) { 4338 state->hdmi1[j] = INREG(i); 4339 state->hdmi2[j] = INREG(i + 0x400); 4340 j++; 4341 } 4342 for (i = 0x7430; i <= 0x74ec; i += 4) { 4343 state->hdmi1[j] = INREG(i); 4344 state->hdmi2[j] = INREG(i + 0x400); 4345 j++; 4346 } 4347 state->hdmi1[j] = INREG(0x7428); 4348 state->hdmi2[j] = INREG(0x7828); 4349 4350 j = 0; 4351 /* save AUX regs */ 4352 for (i = 0x7780; i <= 0x77b4; i += 4) { 4353 state->aux_cntl1[j] = INREG(i); 4354 state->aux_cntl2[j] = INREG(i + 0x040); 4355 state->aux_cntl3[j] = INREG(i + 0x400); 4356 state->aux_cntl4[j] = INREG(i + 0x440); 4357 j++; 4358 } 4359 4360 j = 0; 4361 /* save UNIPHY regs */ 4362 for (i = 0x7ec0; i <= 0x7edc; i += 4) { 4363 state->uniphy1[j] = INREG(i); 4364 state->uniphy2[j] = INREG(i + 0x100); 4365 j++; 4366 } 4367 j = 0; 4368 /* save PHY,LINK regs */ 4369 for (i = 0x7f20; i <= 0x7f34; i += 4) { 4370 state->phy[j] = INREG(i); 4371 j++; 4372 } 4373 for (i = 0x7f9c; i <= 0x7fa4; i += 4) { 4374 state->phy[j] = INREG(i); 4375 j++; 4376 } 4377 state->phy[j] = INREG(0x7f40); 4378 4379 j = 0; 4380 /* save LVTMA regs */ 4381 for (i = 0x7f00; i <= 0x7f1c; i += 4) { 4382 state->lvtma[j] = INREG(i); 4383 j++; 4384 } 4385 for (i = 0x7f80; i <= 0x7f98; i += 4) { 4386 state->lvtma[j] = INREG(i); 4387 j++; 4388 } 4389 } else { 4390 j = 0; 4391 /* save DVOA regs */ 4392 for (i = 0x7980; i <= 0x79bc; i += 4) { 4393 state->dvoa[j] = INREG(i); 4394 j++; 4395 } 4396 4397 j = 0; 4398 /* save DAC regs */ 4399 for (i = 0x7800; i <= 0x782c; i += 4) { 4400 state->daca[j] = INREG(i); 4401 state->dacb[j] = INREG(i + 0x200); 4402 j++; 4403 } 4404 for (i = 0x7834; i <= 0x7840; i += 4) { 4405 state->daca[j] = INREG(i); 4406 state->dacb[j] = INREG(i + 0x200); 4407 j++; 4408 } 4409 for (i = 0x7850; i <= 0x7868; i += 4) { 4410 state->daca[j] = INREG(i); 4411 state->dacb[j] = INREG(i + 0x200); 4412 j++; 4413 } 4414 4415 j = 0; 4416 /* save TMDSA regs */ 4417 for (i = 0x7880; i <= 0x78e0; i += 4) { 4418 state->tmdsa[j] = INREG(i); 4419 j++; 4420 } 4421 for (i = 0x7904; i <= 0x7918; i += 4) { 4422 state->tmdsa[j] = INREG(i); 4423 j++; 4424 } 4425 4426 j = 0; 4427 /* save LVTMA regs */ 4428 for (i = 0x7a80; i <= 0x7b18; i += 4) { 4429 state->lvtma[j] = INREG(i); 4430 j++; 4431 } 4432 4433 if ((info->ChipFamily == CHIP_FAMILY_RS600) || 4434 (info->ChipFamily == CHIP_FAMILY_RS690) || 4435 (info->ChipFamily == CHIP_FAMILY_RS740)) { 4436 j = 0; 4437 /* save DDIA regs */ 4438 for (i = 0x7200; i <= 0x7290; i += 4) { 4439 state->ddia[j] = INREG(i); 4440 j++; 4441 } 4442 } 4443 } 4444 4445 /* scalers */ 4446 j = 0; 4447 for (i = 0x6578; i <= 0x65e4; i += 4) { 4448 state->d1scl[j] = INREG(i); 4449 state->d2scl[j] = INREG(i + 0x800); 4450 j++; 4451 } 4452 for (i = 0x6600; i <= 0x662c; i += 4) { 4453 state->d1scl[j] = INREG(i); 4454 state->d2scl[j] = INREG(i + 0x800); 4455 j++; 4456 } 4457 j = 0; 4458 for (i = 0x66e8; i <= 0x66fc; i += 4) { 4459 state->dxscl[j] = INREG(i); 4460 j++; 4461 } 4462 state->dxscl[6] = INREG(0x6e30); 4463 state->dxscl[7] = INREG(0x6e34); 4464 4465 if (state->crtc1.control & AVIVO_CRTC_EN) 4466 info->crtc_on = TRUE; 4467 4468 if (state->crtc2.control & AVIVO_CRTC_EN) 4469 info->crtc2_on = TRUE; 4470 4471} 4472 4473static void 4474avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) 4475{ 4476 RADEONInfoPtr info = RADEONPTR(pScrn); 4477 unsigned char *RADEONMMIO = info->MMIO; 4478 struct avivo_state *state = &restore->avivo; 4479 int i, j; 4480 4481 // OUTMC(pScrn, AVIVO_MC_MEMORY_MAP, state->mc_memory_map); 4482 // OUTREG(AVIVO_VGA_MEMORY_BASE, state->vga_memory_base); 4483 // OUTREG(AVIVO_VGA_FB_START, state->vga_fb_start); 4484 4485 4486 OUTREG(AVIVO_DC_CRTC_MASTER_EN, state->crtc_master_en); 4487 OUTREG(AVIVO_DC_CRTC_TV_CONTROL, state->crtc_tv_control); 4488 4489 OUTREG(AVIVO_EXT1_PPLL_REF_DIV_SRC, state->pll1.ref_div_src); 4490 OUTREG(AVIVO_EXT1_PPLL_REF_DIV, state->pll1.ref_div); 4491 OUTREG(AVIVO_EXT1_PPLL_FB_DIV, state->pll1.fb_div); 4492 OUTREG(AVIVO_EXT1_PPLL_POST_DIV_SRC, state->pll1.post_div_src); 4493 OUTREG(AVIVO_EXT1_PPLL_POST_DIV, state->pll1.post_div); 4494 OUTREG(AVIVO_EXT1_PPLL_CNTL, state->pll1.ext_ppll_cntl); 4495 OUTREG(AVIVO_P1PLL_CNTL, state->pll1.pll_cntl); 4496 OUTREG(AVIVO_P1PLL_INT_SS_CNTL, state->pll1.int_ss_cntl); 4497 4498 OUTREG(AVIVO_EXT2_PPLL_REF_DIV_SRC, state->pll2.ref_div_src); 4499 OUTREG(AVIVO_EXT2_PPLL_REF_DIV, state->pll2.ref_div); 4500 OUTREG(AVIVO_EXT2_PPLL_FB_DIV, state->pll2.fb_div); 4501 OUTREG(AVIVO_EXT2_PPLL_POST_DIV_SRC, state->pll2.post_div_src); 4502 OUTREG(AVIVO_EXT2_PPLL_POST_DIV, state->pll2.post_div); 4503 OUTREG(AVIVO_EXT2_PPLL_CNTL, state->pll2.ext_ppll_cntl); 4504 OUTREG(AVIVO_P2PLL_CNTL, state->pll2.pll_cntl); 4505 OUTREG(AVIVO_P2PLL_INT_SS_CNTL, state->pll2.int_ss_cntl); 4506 4507 OUTREG(AVIVO_PCLK_CRTC1_CNTL, state->crtc1.pll_source); 4508 4509 OUTREG(AVIVO_D1CRTC_H_TOTAL, state->crtc1.h_total); 4510 OUTREG(AVIVO_D1CRTC_H_BLANK_START_END, state->crtc1.h_blank_start_end); 4511 OUTREG(AVIVO_D1CRTC_H_SYNC_A, state->crtc1.h_sync_a); 4512 OUTREG(AVIVO_D1CRTC_H_SYNC_A_CNTL, state->crtc1.h_sync_a_cntl); 4513 OUTREG(AVIVO_D1CRTC_H_SYNC_B, state->crtc1.h_sync_b); 4514 OUTREG(AVIVO_D1CRTC_H_SYNC_B_CNTL, state->crtc1.h_sync_b_cntl); 4515 4516 OUTREG(AVIVO_D1CRTC_V_TOTAL, state->crtc1.v_total); 4517 OUTREG(AVIVO_D1CRTC_V_BLANK_START_END, state->crtc1.v_blank_start_end); 4518 OUTREG(AVIVO_D1CRTC_V_SYNC_A, state->crtc1.v_sync_a); 4519 OUTREG(AVIVO_D1CRTC_V_SYNC_A_CNTL, state->crtc1.v_sync_a_cntl); 4520 OUTREG(AVIVO_D1CRTC_V_SYNC_B, state->crtc1.v_sync_b); 4521 OUTREG(AVIVO_D1CRTC_V_SYNC_B_CNTL, state->crtc1.v_sync_b_cntl); 4522 4523 OUTREG(AVIVO_D1CRTC_CONTROL, state->crtc1.control); 4524 OUTREG(AVIVO_D1CRTC_BLANK_CONTROL, state->crtc1.blank_control); 4525 OUTREG(AVIVO_D1CRTC_INTERLACE_CONTROL, state->crtc1.interlace_control); 4526 OUTREG(AVIVO_D1CRTC_STEREO_CONTROL, state->crtc1.stereo_control); 4527 4528 OUTREG(AVIVO_D1CUR_CONTROL, state->crtc1.cursor_control); 4529 4530 OUTREG(AVIVO_D1GRPH_ENABLE, state->grph1.enable); 4531 OUTREG(AVIVO_D1GRPH_CONTROL, state->grph1.control); 4532 OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, state->grph1.prim_surf_addr); 4533 OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS, state->grph1.sec_surf_addr); 4534 OUTREG(AVIVO_D1GRPH_PITCH, state->grph1.pitch); 4535 OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X, state->grph1.x_offset); 4536 OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y, state->grph1.y_offset); 4537 OUTREG(AVIVO_D1GRPH_X_START, state->grph1.x_start); 4538 OUTREG(AVIVO_D1GRPH_Y_START, state->grph1.y_start); 4539 OUTREG(AVIVO_D1GRPH_X_END, state->grph1.x_end); 4540 OUTREG(AVIVO_D1GRPH_Y_END, state->grph1.y_end); 4541 4542 OUTREG(AVIVO_D1MODE_VIEWPORT_START, state->grph1.viewport_start); 4543 OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE, state->grph1.viewport_size); 4544 4545 OUTREG(AVIVO_PCLK_CRTC2_CNTL, state->crtc2.pll_source); 4546 4547 OUTREG(AVIVO_D2CRTC_H_TOTAL, state->crtc2.h_total); 4548 OUTREG(AVIVO_D2CRTC_H_BLANK_START_END, state->crtc2.h_blank_start_end); 4549 OUTREG(AVIVO_D2CRTC_H_SYNC_A, state->crtc2.h_sync_a); 4550 OUTREG(AVIVO_D2CRTC_H_SYNC_A_CNTL, state->crtc2.h_sync_a_cntl); 4551 OUTREG(AVIVO_D2CRTC_H_SYNC_B, state->crtc2.h_sync_b); 4552 OUTREG(AVIVO_D2CRTC_H_SYNC_B_CNTL, state->crtc2.h_sync_b_cntl); 4553 4554 OUTREG(AVIVO_D2CRTC_V_TOTAL, state->crtc2.v_total); 4555 OUTREG(AVIVO_D2CRTC_V_BLANK_START_END, state->crtc2.v_blank_start_end); 4556 OUTREG(AVIVO_D2CRTC_V_SYNC_A, state->crtc2.v_sync_a); 4557 OUTREG(AVIVO_D2CRTC_V_SYNC_A_CNTL, state->crtc2.v_sync_a_cntl); 4558 OUTREG(AVIVO_D2CRTC_V_SYNC_B, state->crtc2.v_sync_b); 4559 OUTREG(AVIVO_D2CRTC_V_SYNC_B_CNTL, state->crtc2.v_sync_b_cntl); 4560 4561 OUTREG(AVIVO_D2CRTC_CONTROL, state->crtc2.control); 4562 OUTREG(AVIVO_D2CRTC_BLANK_CONTROL, state->crtc2.blank_control); 4563 OUTREG(AVIVO_D2CRTC_INTERLACE_CONTROL, state->crtc2.interlace_control); 4564 OUTREG(AVIVO_D2CRTC_STEREO_CONTROL, state->crtc2.stereo_control); 4565 4566 OUTREG(AVIVO_D2CUR_CONTROL, state->crtc2.cursor_control); 4567 4568 OUTREG(AVIVO_D2GRPH_ENABLE, state->grph2.enable); 4569 OUTREG(AVIVO_D2GRPH_CONTROL, state->grph2.control); 4570 OUTREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, state->grph2.prim_surf_addr); 4571 OUTREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS, state->grph2.sec_surf_addr); 4572 OUTREG(AVIVO_D2GRPH_PITCH, state->grph2.pitch); 4573 OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_X, state->grph2.x_offset); 4574 OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y, state->grph2.y_offset); 4575 OUTREG(AVIVO_D2GRPH_X_START, state->grph2.x_start); 4576 OUTREG(AVIVO_D2GRPH_Y_START, state->grph2.y_start); 4577 OUTREG(AVIVO_D2GRPH_X_END, state->grph2.x_end); 4578 OUTREG(AVIVO_D2GRPH_Y_END, state->grph2.y_end); 4579 4580 OUTREG(AVIVO_D2MODE_VIEWPORT_START, state->grph2.viewport_start); 4581 OUTREG(AVIVO_D2MODE_VIEWPORT_SIZE, state->grph2.viewport_size); 4582 4583 4584 if (IS_DCE3_VARIANT) { 4585 /* DVOA regs */ 4586 OUTREG(0x7080, state->dvoa[0]); 4587 OUTREG(0x7084, state->dvoa[1]); 4588 OUTREG(0x708c, state->dvoa[2]); 4589 OUTREG(0x7090, state->dvoa[3]); 4590 OUTREG(0x7094, state->dvoa[4]); 4591 OUTREG(0x70ac, state->dvoa[5]); 4592 OUTREG(0x70b0, state->dvoa[6]); 4593 4594 j = 0; 4595 /* DAC regs */ 4596 for (i = 0x7000; i <= 0x7040; i += 4) { 4597 OUTREG(i, state->daca[j]); 4598 OUTREG((i + 0x100), state->dacb[j]); 4599 j++; 4600 } 4601 for (i = 0x7058; i <= 0x7060; i += 4) { 4602 OUTREG(i, state->daca[j]); 4603 OUTREG((i + 0x100), state->dacb[j]); 4604 j++; 4605 } 4606 for (i = 0x7068; i <= 0x706c; i += 4) { 4607 OUTREG(i, state->daca[j]); 4608 OUTREG((i + 0x100), state->dacb[j]); 4609 j++; 4610 } 4611 for (i = 0x7ef0; i <= 0x7ef8; i += 4) { 4612 OUTREG(i, state->daca[j]); 4613 OUTREG((i + 0x100), state->dacb[j]); 4614 j++; 4615 } 4616 OUTREG(0x7050, state->daca[j]); 4617 OUTREG((0x7050 + 0x100), state->dacb[j]); 4618 4619 j = 0; 4620 /* FMT regs */ 4621 for (i = 0x6700; i <= 0x6744; i += 4) { 4622 OUTREG(i, state->fmt1[j]); 4623 OUTREG((i + 0x800), state->fmt2[j]); 4624 j++; 4625 } 4626 4627 j = 0; 4628 /* DIG regs */ 4629 for (i = 0x75a0; i <= 0x75e0; i += 4) { 4630 OUTREG(i, state->dig1[j]); 4631 OUTREG((i + 0x400), state->dig2[j]); 4632 j++; 4633 } 4634 for (i = 0x75e8; i <= 0x75ec; i += 4) { 4635 OUTREG(i, state->dig1[j]); 4636 OUTREG((i + 0x400), state->dig2[j]); 4637 j++; 4638 } 4639 4640 j = 0; 4641 /* HDMI regs */ 4642 for (i = 0x7400; i <= 0x741c; i += 4) { 4643 OUTREG(i, state->hdmi1[j]); 4644 OUTREG((i + 0x400), state->hdmi2[j]); 4645 j++; 4646 } 4647 for (i = 0x7430; i <= 0x74ec; i += 4) { 4648 OUTREG(i, state->hdmi1[j]); 4649 OUTREG((i + 0x400), state->hdmi2[j]); 4650 j++; 4651 } 4652 OUTREG(0x7428, state->hdmi1[j]); 4653 OUTREG((0x7428 + 0x400), state->hdmi2[j]); 4654 4655 j = 0; 4656 /* save AUX regs */ 4657 for (i = 0x7780; i <= 0x77b4; i += 4) { 4658 OUTREG(i, state->aux_cntl1[j]); 4659 OUTREG((i + 0x040), state->aux_cntl2[j]); 4660 OUTREG((i + 0x400), state->aux_cntl3[j]); 4661 OUTREG((i + 0x440), state->aux_cntl4[j]); 4662 j++; 4663 } 4664 4665 j = 0; 4666 /* save UNIPHY regs */ 4667 for (i = 0x7ec0; i <= 0x7edc; i += 4) { 4668 OUTREG(i, state->uniphy1[j]); 4669 OUTREG((i + 0x100), state->uniphy2[j]); 4670 j++; 4671 } 4672 j = 0; 4673 /* save PHY,LINK regs */ 4674 for (i = 0x7f20; i <= 0x7f34; i += 4) { 4675 OUTREG(i, state->phy[j]); 4676 j++; 4677 } 4678 for (i = 0x7f9c; i <= 0x7fa4; i += 4) { 4679 OUTREG(i, state->phy[j]); 4680 j++; 4681 } 4682 state->phy[j] = INREG(0x7f40); 4683 4684 j = 0; 4685 /* save LVTMA regs */ 4686 for (i = 0x7f00; i <= 0x7f1c; i += 4) { 4687 OUTREG(i, state->lvtma[j]); 4688 j++; 4689 } 4690 for (i = 0x7f80; i <= 0x7f98; i += 4) { 4691 OUTREG(i, state->lvtma[j]); 4692 j++; 4693 } 4694 } else { 4695 j = 0; 4696 /* DVOA regs */ 4697 for (i = 0x7980; i <= 0x79bc; i += 4) { 4698 OUTREG(i, state->dvoa[j]); 4699 j++; 4700 } 4701 4702 j = 0; 4703 /* DAC regs */ 4704 for (i = 0x7800; i <= 0x782c; i += 4) { 4705 OUTREG(i, state->daca[j]); 4706 OUTREG((i + 0x200), state->dacb[j]); 4707 j++; 4708 } 4709 for (i = 0x7834; i <= 0x7840; i += 4) { 4710 OUTREG(i, state->daca[j]); 4711 OUTREG((i + 0x200), state->dacb[j]); 4712 j++; 4713 } 4714 for (i = 0x7850; i <= 0x7868; i += 4) { 4715 OUTREG(i, state->daca[j]); 4716 OUTREG((i + 0x200), state->dacb[j]); 4717 j++; 4718 } 4719 4720 j = 0; 4721 /* TMDSA regs */ 4722 for (i = 0x7880; i <= 0x78e0; i += 4) { 4723 OUTREG(i, state->tmdsa[j]); 4724 j++; 4725 } 4726 for (i = 0x7904; i <= 0x7918; i += 4) { 4727 OUTREG(i, state->tmdsa[j]); 4728 j++; 4729 } 4730 4731 j = 0; 4732 /* LVTMA regs */ 4733 for (i = 0x7a80; i <= 0x7b18; i += 4) { 4734 OUTREG(i, state->lvtma[j]); 4735 j++; 4736 } 4737 4738 /* DDIA regs */ 4739 if ((info->ChipFamily == CHIP_FAMILY_RS600) || 4740 (info->ChipFamily == CHIP_FAMILY_RS690) || 4741 (info->ChipFamily == CHIP_FAMILY_RS740)) { 4742 j = 0; 4743 for (i = 0x7200; i <= 0x7290; i += 4) { 4744 OUTREG(i, state->ddia[j]); 4745 j++; 4746 } 4747 } 4748 } 4749 4750 /* scalers */ 4751 j = 0; 4752 for (i = 0x6578; i <= 0x65e4; i += 4) { 4753 OUTREG(i, state->d1scl[j]); 4754 OUTREG((i + 0x800), state->d2scl[j]); 4755 j++; 4756 } 4757 for (i = 0x6600; i <= 0x662c; i += 4) { 4758 OUTREG(i, state->d1scl[j]); 4759 OUTREG((i + 0x800), state->d2scl[j]); 4760 j++; 4761 } 4762 j = 0; 4763 for (i = 0x66e8; i <= 0x66fc; i += 4) { 4764 OUTREG(i, state->dxscl[j]); 4765 j++; 4766 } 4767 OUTREG(0x6e30, state->dxscl[6]); 4768 OUTREG(0x6e34, state->dxscl[7]); 4769 4770 OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl); 4771 OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl); 4772} 4773 4774static void avivo_restore_vga_regs(ScrnInfoPtr pScrn, RADEONSavePtr restore) 4775{ 4776 RADEONInfoPtr info = RADEONPTR(pScrn); 4777 unsigned char *RADEONMMIO = info->MMIO; 4778 struct avivo_state *state = &restore->avivo; 4779 4780 OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl); 4781 OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl); 4782} 4783 4784static void 4785RADEONRestoreBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) 4786{ 4787 RADEONInfoPtr info = RADEONPTR(pScrn); 4788 unsigned char *RADEONMMIO = info->MMIO; 4789 4790 if (info->ChipFamily >= CHIP_FAMILY_R600) { 4791 OUTREG(R600_BIOS_0_SCRATCH, restore->bios_0_scratch); 4792 OUTREG(R600_BIOS_1_SCRATCH, restore->bios_1_scratch); 4793 OUTREG(R600_BIOS_2_SCRATCH, restore->bios_2_scratch); 4794 OUTREG(R600_BIOS_3_SCRATCH, restore->bios_3_scratch); 4795 OUTREG(R600_BIOS_4_SCRATCH, restore->bios_4_scratch); 4796 OUTREG(R600_BIOS_5_SCRATCH, restore->bios_5_scratch); 4797 OUTREG(R600_BIOS_6_SCRATCH, restore->bios_6_scratch); 4798 OUTREG(R600_BIOS_7_SCRATCH, restore->bios_7_scratch); 4799 } else { 4800 OUTREG(RADEON_BIOS_0_SCRATCH, restore->bios_0_scratch); 4801 OUTREG(RADEON_BIOS_1_SCRATCH, restore->bios_1_scratch); 4802 OUTREG(RADEON_BIOS_2_SCRATCH, restore->bios_2_scratch); 4803 OUTREG(RADEON_BIOS_3_SCRATCH, restore->bios_3_scratch); 4804 OUTREG(RADEON_BIOS_4_SCRATCH, restore->bios_4_scratch); 4805 OUTREG(RADEON_BIOS_5_SCRATCH, restore->bios_5_scratch); 4806 OUTREG(RADEON_BIOS_6_SCRATCH, restore->bios_6_scratch); 4807 OUTREG(RADEON_BIOS_7_SCRATCH, restore->bios_7_scratch); 4808 } 4809} 4810 4811static void 4812RADEONSaveBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) 4813{ 4814 RADEONInfoPtr info = RADEONPTR(pScrn); 4815 unsigned char *RADEONMMIO = info->MMIO; 4816 4817 if (info->ChipFamily >= CHIP_FAMILY_R600) { 4818 save->bios_0_scratch = INREG(R600_BIOS_0_SCRATCH); 4819 save->bios_1_scratch = INREG(R600_BIOS_1_SCRATCH); 4820 save->bios_2_scratch = INREG(R600_BIOS_2_SCRATCH); 4821 save->bios_3_scratch = INREG(R600_BIOS_3_SCRATCH); 4822 save->bios_4_scratch = INREG(R600_BIOS_4_SCRATCH); 4823 save->bios_5_scratch = INREG(R600_BIOS_5_SCRATCH); 4824 save->bios_6_scratch = INREG(R600_BIOS_6_SCRATCH); 4825 save->bios_7_scratch = INREG(R600_BIOS_7_SCRATCH); 4826 } else { 4827 save->bios_0_scratch = INREG(RADEON_BIOS_0_SCRATCH); 4828 save->bios_1_scratch = INREG(RADEON_BIOS_1_SCRATCH); 4829 save->bios_2_scratch = INREG(RADEON_BIOS_2_SCRATCH); 4830 save->bios_3_scratch = INREG(RADEON_BIOS_3_SCRATCH); 4831 save->bios_4_scratch = INREG(RADEON_BIOS_4_SCRATCH); 4832 save->bios_5_scratch = INREG(RADEON_BIOS_5_SCRATCH); 4833 save->bios_6_scratch = INREG(RADEON_BIOS_6_SCRATCH); 4834 save->bios_7_scratch = INREG(RADEON_BIOS_7_SCRATCH); 4835 } 4836} 4837 4838/* Save everything needed to restore the original VC state */ 4839static void RADEONSave(ScrnInfoPtr pScrn) 4840{ 4841 RADEONInfoPtr info = RADEONPTR(pScrn); 4842 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 4843 unsigned char *RADEONMMIO = info->MMIO; 4844 RADEONSavePtr save = info->SavedReg; 4845 4846 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 4847 "RADEONSave\n"); 4848 4849#ifdef WITH_VGAHW 4850 if (info->VGAAccess) { 4851 vgaHWPtr hwp = VGAHWPTR(pScrn); 4852 4853 vgaHWUnlock(hwp); 4854# if defined(__powerpc__) 4855 /* temporary hack to prevent crashing on PowerMacs when trying to 4856 * read VGA fonts and colormap, will find a better solution 4857 * in the future. TODO: Check if there's actually some VGA stuff 4858 * setup in the card at all !! 4859 */ 4860 vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE); /* Save mode only */ 4861# elif defined(__linux__) 4862 /* Save only mode * & fonts */ 4863 vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS ); 4864# else 4865 /* Save mode * & fonts & cmap */ 4866 vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_ALL); 4867# endif 4868 vgaHWLock(hwp); 4869 } 4870#endif 4871 4872 if (IS_AVIVO_VARIANT) { 4873 RADEONSaveMemMapRegisters(pScrn, save); 4874 avivo_save(pScrn, save); 4875 } else { 4876 save->dp_datatype = INREG(RADEON_DP_DATATYPE); 4877 save->rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET); 4878 save->clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX); 4879 RADEONPllErrataAfterIndex(info); 4880 4881 RADEONSaveMemMapRegisters(pScrn, save); 4882 RADEONSaveCommonRegisters(pScrn, save); 4883 RADEONSavePLLRegisters(pScrn, save); 4884 RADEONSaveCrtcRegisters(pScrn, save); 4885 RADEONSaveFPRegisters(pScrn, save); 4886 RADEONSaveDACRegisters(pScrn, save); 4887 if (pRADEONEnt->HasCRTC2) { 4888 RADEONSaveCrtc2Registers(pScrn, save); 4889 RADEONSavePLL2Registers(pScrn, save); 4890 } 4891 if (info->InternalTVOut) 4892 RADEONSaveTVRegisters(pScrn, save); 4893 } 4894 4895 RADEONSaveBIOSRegisters(pScrn, save); 4896 if (info->ChipFamily < CHIP_FAMILY_R600) 4897 RADEONSaveSurfaces(pScrn, save); 4898 4899} 4900 4901/* Restore the original (text) mode */ 4902static void RADEONRestore(ScrnInfoPtr pScrn) 4903{ 4904 RADEONInfoPtr info = RADEONPTR(pScrn); 4905 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 4906 unsigned char *RADEONMMIO = info->MMIO; 4907 RADEONSavePtr restore = info->SavedReg; 4908 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 4909 xf86CrtcPtr crtc; 4910 4911 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 4912 "RADEONRestore\n"); 4913 4914#if X_BYTE_ORDER == X_BIG_ENDIAN 4915 RADEONWaitForFifo(pScrn, 1); 4916 OUTREG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_NONE); 4917#endif 4918 4919 RADEONBlank(pScrn); 4920 4921 if (IS_AVIVO_VARIANT) { 4922 RADEONRestoreMemMapRegisters(pScrn, restore); 4923 avivo_restore(pScrn, restore); 4924 } else { 4925 OUTREG(RADEON_CLOCK_CNTL_INDEX, restore->clock_cntl_index); 4926 RADEONPllErrataAfterIndex(info); 4927 OUTREG(RADEON_RBBM_SOFT_RESET, restore->rbbm_soft_reset); 4928 OUTREG(RADEON_DP_DATATYPE, restore->dp_datatype); 4929 OUTREG(RADEON_GRPH_BUFFER_CNTL, restore->grph_buffer_cntl); 4930 OUTREG(RADEON_GRPH2_BUFFER_CNTL, restore->grph2_buffer_cntl); 4931 4932 if (!info->IsSecondary) { 4933 RADEONRestoreMemMapRegisters(pScrn, restore); 4934 RADEONRestoreCommonRegisters(pScrn, restore); 4935 4936 if (pRADEONEnt->HasCRTC2) { 4937 RADEONRestoreCrtc2Registers(pScrn, restore); 4938 RADEONRestorePLL2Registers(pScrn, restore); 4939 } 4940 4941 RADEONRestoreCrtcRegisters(pScrn, restore); 4942 RADEONRestorePLLRegisters(pScrn, restore); 4943 RADEONRestoreRMXRegisters(pScrn, restore); 4944 RADEONRestoreFPRegisters(pScrn, restore); 4945 RADEONRestoreFP2Registers(pScrn, restore); 4946 RADEONRestoreLVDSRegisters(pScrn, restore); 4947 4948 if (info->InternalTVOut) 4949 RADEONRestoreTVRegisters(pScrn, restore); 4950 } 4951 4952 RADEONRestoreBIOSRegisters(pScrn, restore); 4953 } 4954 4955 4956#if 1 4957 /* Temp fix to "solve" VT switch problems. When switching VTs on 4958 * some systems, the console can either hang or the fonts can be 4959 * corrupted. This hack solves the problem 99% of the time. A 4960 * correct fix is being worked on. 4961 */ 4962 usleep(100000); 4963#endif 4964 4965 if (info->ChipFamily < CHIP_FAMILY_R600) 4966 RADEONRestoreSurfaces(pScrn, restore); 4967 4968 /* need to make sure we don't enable a crtc by accident or we may get a hang */ 4969 if (pRADEONEnt->HasCRTC2 && !info->IsSecondary) { 4970 if (info->crtc2_on && xf86_config->num_crtc > 1) { 4971 crtc = xf86_config->crtc[1]; 4972 crtc->funcs->dpms(crtc, DPMSModeOn); 4973 } 4974 } 4975 if (info->crtc_on) { 4976 crtc = xf86_config->crtc[0]; 4977 crtc->funcs->dpms(crtc, DPMSModeOn); 4978 } 4979 4980#ifdef WITH_VGAHW 4981 if (info->VGAAccess) { 4982 vgaHWPtr hwp = VGAHWPTR(pScrn); 4983 vgaHWUnlock(hwp); 4984# if defined(__powerpc__) 4985 /* Temporary hack to prevent crashing on PowerMacs when trying to 4986 * write VGA fonts, will find a better solution in the future 4987 */ 4988 vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE ); 4989# elif defined(__linux__) 4990 vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS ); 4991# else 4992 vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_ALL ); 4993# endif 4994 vgaHWLock(hwp); 4995 } 4996#endif 4997 4998 /* to restore console mode, DAC registers should be set after every other registers are set, 4999 * otherwise,we may get blank screen 5000 */ 5001 if (IS_AVIVO_VARIANT) 5002 avivo_restore_vga_regs(pScrn, restore); 5003 5004 if (!IS_AVIVO_VARIANT) 5005 RADEONRestoreDACRegisters(pScrn, restore); 5006 5007#if 0 5008 RADEONWaitForVerticalSync(pScrn); 5009#endif 5010} 5011 5012#if 0 5013/* Define initial palette for requested video mode. This doesn't do 5014 * anything for XFree86 4.0. 5015 */ 5016static void RADEONInitPalette(RADEONSavePtr save) 5017{ 5018 save->palette_valid = FALSE; 5019} 5020#endif 5021 5022static Bool RADEONSaveScreen(ScreenPtr pScreen, int mode) 5023{ 5024 ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; 5025 Bool unblank; 5026 5027 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5028 "RADEONSaveScreen(%d)\n", mode); 5029 5030 unblank = xf86IsUnblank(mode); 5031 if (unblank) SetTimeSinceLastInputEvent(); 5032 5033 if ((pScrn != NULL) && pScrn->vtSema) { 5034 if (unblank) 5035 RADEONUnblank(pScrn); 5036 else 5037 RADEONBlank(pScrn); 5038 } 5039 return TRUE; 5040} 5041 5042Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) 5043{ 5044 ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; 5045 RADEONInfoPtr info = RADEONPTR(pScrn); 5046 Bool tilingOld = info->tilingEnabled; 5047 Bool ret; 5048#ifdef XF86DRI 5049 Bool CPStarted = info->CPStarted; 5050 5051 if (CPStarted) { 5052 DRILock(pScrn->pScreen, 0); 5053 RADEONCP_STOP(pScrn, info); 5054 } 5055#endif 5056 5057 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5058 "RADEONSwitchMode() !n"); 5059 5060 if (info->allowColorTiling) { 5061 info->tilingEnabled = (mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; 5062#ifdef XF86DRI 5063 if (info->directRenderingEnabled && (info->tilingEnabled != tilingOld)) { 5064 RADEONSAREAPrivPtr pSAREAPriv; 5065 if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0) 5066 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 5067 "[drm] failed changing tiling status\n"); 5068 pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen); 5069 info->tilingEnabled = pSAREAPriv->tiling_enabled ? TRUE : FALSE; 5070 } 5071#endif 5072 } 5073 5074 if (info->accelOn) 5075 RADEON_SYNC(info, pScrn); 5076 5077 ret = xf86SetSingleMode (pScrn, mode, RR_Rotate_0); 5078 5079 if (info->tilingEnabled != tilingOld) { 5080 /* need to redraw front buffer, I guess this can be considered a hack ? */ 5081 xf86EnableDisableFBAccess(scrnIndex, FALSE); 5082 RADEONChangeSurfaces(pScrn); 5083 xf86EnableDisableFBAccess(scrnIndex, TRUE); 5084 /* xf86SetRootClip would do, but can't access that here */ 5085 } 5086 5087 if (info->accelOn) { 5088 RADEON_SYNC(info, pScrn); 5089 RADEONEngineRestore(pScrn); 5090 } 5091 5092#ifdef XF86DRI 5093 if (CPStarted) { 5094 RADEONCP_START(pScrn, info); 5095 DRIUnlock(pScrn->pScreen); 5096 } 5097#endif 5098 5099 /* reset ecp for overlay */ 5100 info->ecp_div = -1; 5101 5102 return ret; 5103} 5104 5105#ifdef X_XF86MiscPassMessage 5106Bool RADEONHandleMessage(int scrnIndex, const char* msgtype, 5107 const char* msgval, char** retmsg) 5108{ 5109 ErrorF("RADEONHandleMessage(%d, \"%s\", \"%s\", retmsg)\n", scrnIndex, 5110 msgtype, msgval); 5111 *retmsg = ""; 5112 return 0; 5113} 5114#endif 5115 5116#ifndef HAVE_XF86MODEBANDWIDTH 5117/** Calculates the memory bandwidth (in MiB/sec) of a mode. */ 5118_X_HIDDEN unsigned int 5119xf86ModeBandwidth(DisplayModePtr mode, int depth) 5120{ 5121 float a_active, a_total, active_percent, pixels_per_second; 5122 int bytes_per_pixel = (depth + 7) / 8; 5123 5124 if (!mode->HTotal || !mode->VTotal || !mode->Clock) 5125 return 0; 5126 5127 a_active = mode->HDisplay * mode->VDisplay; 5128 a_total = mode->HTotal * mode->VTotal; 5129 active_percent = a_active / a_total; 5130 pixels_per_second = active_percent * mode->Clock * 1000.0; 5131 5132 return (unsigned int)(pixels_per_second * bytes_per_pixel / (1024 * 1024)); 5133} 5134#endif 5135 5136/* Used to disallow modes that are not supported by the hardware */ 5137ModeStatus RADEONValidMode(int scrnIndex, DisplayModePtr mode, 5138 Bool verbose, int flag) 5139{ 5140 ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; 5141 RADEONInfoPtr info = RADEONPTR(pScrn); 5142 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 5143 5144 /* 5145 * RN50 has effective maximum mode bandwidth of about 300MiB/s. 5146 * XXX should really do this for all chips by properly computing 5147 * memory bandwidth and an overhead factor. 5148 */ 5149 if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) { 5150 if (xf86ModeBandwidth(mode, pScrn->bitsPerPixel) > 300) 5151 return MODE_BANDWIDTH; 5152 } 5153 5154 /* There are problems with double scan mode at high clocks 5155 * They're likely related PLL and display buffer settings. 5156 * Disable these modes for now. 5157 */ 5158 if (mode->Flags & V_DBLSCAN) { 5159 if ((mode->CrtcHDisplay >= 1024) || (mode->CrtcVDisplay >= 768)) 5160 return MODE_CLOCK_RANGE; 5161 } 5162 return MODE_OK; 5163} 5164 5165/* Adjust viewport into virtual desktop such that (0,0) in viewport 5166 * space is (x,y) in virtual space. 5167 */ 5168void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool crtc2) 5169{ 5170 RADEONInfoPtr info = RADEONPTR(pScrn); 5171 unsigned char *RADEONMMIO = info->MMIO; 5172 int Base, reg, regcntl, crtcoffsetcntl, xytilereg, crtcxytile = 0; 5173#ifdef XF86DRI 5174 RADEONSAREAPrivPtr pSAREAPriv; 5175 XF86DRISAREAPtr pSAREA; 5176#endif 5177 5178#if 0 /* Verbose */ 5179 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5180 "RADEONDoAdjustFrame(%d,%d,%d)\n", x, y, clone); 5181#endif 5182 5183 if (info->showCache && y) { 5184 int lastline = info->FbMapSize / 5185 ((pScrn->displayWidth * pScrn->bitsPerPixel) / 8); 5186 5187 lastline -= pScrn->currentMode->VDisplay; 5188 y += (pScrn->virtualY - 1) * (y / 3 + 1); 5189 if (y > lastline) y = lastline; 5190 } 5191 5192 Base = pScrn->fbOffset; 5193 5194 /* note we cannot really simply use the info->ModeReg.crtc_offset_cntl value, since the 5195 drm might have set FLIP_CNTL since we wrote that. Unfortunately FLIP_CNTL causes 5196 flickering when scrolling vertically in a virtual screen, possibly because crtc will 5197 pick up the new offset value at the end of each scanline, but the new offset_cntl value 5198 only after a vsync. We'd probably need to wait (in drm) for vsync and only then update 5199 OFFSET and OFFSET_CNTL, if the y coord has changed. Seems hard to fix. */ 5200 if (crtc2) { 5201 reg = RADEON_CRTC2_OFFSET; 5202 regcntl = RADEON_CRTC2_OFFSET_CNTL; 5203 xytilereg = R300_CRTC2_TILE_X0_Y0; 5204 } else { 5205 reg = RADEON_CRTC_OFFSET; 5206 regcntl = RADEON_CRTC_OFFSET_CNTL; 5207 xytilereg = R300_CRTC_TILE_X0_Y0; 5208 } 5209 crtcoffsetcntl = INREG(regcntl) & ~0xf; 5210#if 0 5211 /* try to get rid of flickering when scrolling at least for 2d */ 5212#ifdef XF86DRI 5213 if (!info->have3DWindows) 5214#endif 5215 crtcoffsetcntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL; 5216#endif 5217 if (info->tilingEnabled) { 5218 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { 5219 /* On r300/r400 when tiling is enabled crtc_offset is set to the address of 5220 * the surface. the x/y offsets are handled by the X_Y tile reg for each crtc 5221 * Makes tiling MUCH easier. 5222 */ 5223 crtcxytile = x | (y << 16); 5224 Base &= ~0x7ff; 5225 } else { 5226 int byteshift = info->CurrentLayout.bitsPerPixel >> 4; 5227 /* crtc uses 256(bytes)x8 "half-tile" start addresses? */ 5228 int tile_addr = (((y >> 3) * info->CurrentLayout.displayWidth + x) >> (8 - byteshift)) << 11; 5229 Base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); 5230 crtcoffsetcntl = crtcoffsetcntl | (y % 16); 5231 } 5232 } 5233 else { 5234 int offset = y * info->CurrentLayout.displayWidth + x; 5235 switch (info->CurrentLayout.pixel_code) { 5236 case 15: 5237 case 16: offset *= 2; break; 5238 case 24: offset *= 3; break; 5239 case 32: offset *= 4; break; 5240 } 5241 Base += offset; 5242 } 5243 5244 Base &= ~7; /* 3 lower bits are always 0 */ 5245 5246#ifdef XF86DRI 5247 if (info->directRenderingInited) { 5248 /* note cannot use pScrn->pScreen since this is unitialized when called from 5249 RADEONScreenInit, and we need to call from there to get mergedfb + pageflip working */ 5250 /*** NOTE: r3/4xx will need sarea and drm pageflip updates to handle the xytile regs for 5251 *** pageflipping! 5252 ***/ 5253 pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]); 5254 /* can't get at sarea in a semi-sane way? */ 5255 pSAREA = (void *)((char*)pSAREAPriv - sizeof(XF86DRISAREARec)); 5256 5257 if (crtc2) { 5258 pSAREAPriv->crtc2_base = Base; 5259 } 5260 else { 5261 pSAREA->frame.x = (Base / info->CurrentLayout.pixel_bytes) 5262 % info->CurrentLayout.displayWidth; 5263 pSAREA->frame.y = (Base / info->CurrentLayout.pixel_bytes) 5264 / info->CurrentLayout.displayWidth; 5265 pSAREA->frame.width = pScrn->frameX1 - x + 1; 5266 pSAREA->frame.height = pScrn->frameY1 - y + 1; 5267 } 5268 5269 if (pSAREAPriv->pfCurrentPage == 1) { 5270 Base += info->backOffset - info->frontOffset; 5271 } 5272 } 5273#endif 5274 5275 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { 5276 OUTREG(xytilereg, crtcxytile); 5277 } else { 5278 OUTREG(regcntl, crtcoffsetcntl); 5279 } 5280 5281 OUTREG(reg, Base); 5282} 5283 5284void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags) 5285{ 5286 ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; 5287 RADEONInfoPtr info = RADEONPTR(pScrn); 5288 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 5289 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 5290 xf86OutputPtr output = config->output[config->compat_output]; 5291 xf86CrtcPtr crtc = output->crtc; 5292 5293#ifdef XF86DRI 5294 if (info->CPStarted && pScrn->pScreen) DRILock(pScrn->pScreen, 0); 5295#endif 5296 5297 if (info->accelOn) 5298 RADEON_SYNC(info, pScrn); 5299 5300 if (crtc && crtc->enabled) { 5301 if (crtc == pRADEONEnt->pCrtc[0]) 5302 RADEONDoAdjustFrame(pScrn, crtc->desiredX + x, crtc->desiredY + y, FALSE); 5303 else 5304 RADEONDoAdjustFrame(pScrn, crtc->desiredX + x, crtc->desiredY + y, TRUE); 5305 crtc->x = output->initial_x + x; 5306 crtc->y = output->initial_y + y; 5307 } 5308 5309 5310#ifdef XF86DRI 5311 if (info->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen); 5312#endif 5313} 5314 5315/* Called when VT switching back to the X server. Reinitialize the 5316 * video mode. 5317 */ 5318Bool RADEONEnterVT(int scrnIndex, int flags) 5319{ 5320 ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; 5321 RADEONInfoPtr info = RADEONPTR(pScrn); 5322 unsigned char *RADEONMMIO = info->MMIO; 5323 uint32_t mem_size; 5324 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 5325 int i; 5326 5327 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5328 "RADEONEnterVT\n"); 5329 5330 if (info->ChipFamily >= CHIP_FAMILY_R600) 5331 mem_size = INREG(R600_CONFIG_MEMSIZE); 5332 else 5333 mem_size = INREG(RADEON_CONFIG_MEMSIZE); 5334 5335 if (mem_size == 0) { /* Softboot V_BIOS */ 5336 if (info->IsAtomBios) { 5337 rhdAtomASICInit(info->atomBIOS); 5338 } else { 5339 xf86Int10InfoPtr pInt; 5340 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 5341 "zero MEMSIZE, probably at D3cold. Re-POSTing via int10.\n"); 5342 pInt = xf86InitInt10 (info->pEnt->index); 5343 if (pInt) { 5344 pInt->num = 0xe6; 5345 xf86ExecX86int10 (pInt); 5346 xf86FreeInt10 (pInt); 5347 } else { 5348 RADEONGetBIOSInitTableOffsets(pScrn); 5349 RADEONPostCardFromBIOSTables(pScrn); 5350 } 5351 } 5352 } 5353 5354 /* Makes sure the engine is idle before doing anything */ 5355 RADEONWaitForIdleMMIO(pScrn); 5356 5357 if (info->IsMobility && !IS_AVIVO_VARIANT) { 5358 if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) { 5359 RADEONSetDynamicClock(pScrn, 1); 5360 } else { 5361 RADEONSetDynamicClock(pScrn, 0); 5362 } 5363 } else if (IS_AVIVO_VARIANT) { 5364 if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) { 5365 atombios_static_pwrmgt_setup(pScrn, 1); 5366 atombios_dyn_clk_setup(pScrn, 1); 5367 } 5368 } 5369 5370 if (IS_R300_VARIANT || IS_RV100_VARIANT) 5371 RADEONForceSomeClocks(pScrn); 5372 5373 for (i = 0; i < config->num_crtc; i++) 5374 radeon_crtc_modeset_ioctl(config->crtc[i], TRUE); 5375 5376 pScrn->vtSema = TRUE; 5377 5378 if (!xf86SetDesiredModes(pScrn)) 5379 return FALSE; 5380 5381 if (info->ChipFamily < CHIP_FAMILY_R600) 5382 RADEONRestoreSurfaces(pScrn, info->ModeReg); 5383#ifdef XF86DRI 5384 if (info->directRenderingEnabled) { 5385 if (info->cardType == CARD_PCIE && 5386 info->pKernelDRMVersion->version_minor >= 19 && 5387 info->FbSecureSize) { 5388 /* we need to backup the PCIE GART TABLE from fb memory */ 5389 memcpy(info->FB + info->pciGartOffset, info->pciGartBackup, info->pciGartSize); 5390 } 5391 5392 /* get the DRI back into shape after resume */ 5393 RADEONDRISetVBlankInterrupt (pScrn, TRUE); 5394 RADEONDRIResume(pScrn->pScreen); 5395 RADEONAdjustMemMapRegisters(pScrn, info->ModeReg); 5396 5397 } 5398#endif 5399 /* this will get XVideo going again, but only if XVideo was initialised 5400 during server startup (hence the info->adaptor if). */ 5401 if (info->adaptor) 5402 RADEONResetVideo(pScrn); 5403 5404 if (info->accelOn) 5405 RADEONEngineRestore(pScrn); 5406 5407#ifdef XF86DRI 5408 if (info->directRenderingEnabled) { 5409 RADEONCP_START(pScrn, info); 5410 DRIUnlock(pScrn->pScreen); 5411 } 5412#endif 5413 5414 return TRUE; 5415} 5416 5417/* Called when VT switching away from the X server. Restore the 5418 * original text mode. 5419 */ 5420void RADEONLeaveVT(int scrnIndex, int flags) 5421{ 5422 ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; 5423 RADEONInfoPtr info = RADEONPTR(pScrn); 5424 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 5425 int i; 5426 5427 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5428 "RADEONLeaveVT\n"); 5429#ifdef XF86DRI 5430 if (RADEONPTR(pScrn)->directRenderingInited) { 5431 5432 RADEONDRISetVBlankInterrupt (pScrn, FALSE); 5433 DRILock(pScrn->pScreen, 0); 5434 RADEONCP_STOP(pScrn, info); 5435 5436 if (info->cardType == CARD_PCIE && 5437 info->pKernelDRMVersion->version_minor >= 19 && 5438 info->FbSecureSize) { 5439 /* we need to backup the PCIE GART TABLE from fb memory */ 5440 memcpy(info->pciGartBackup, (info->FB + info->pciGartOffset), info->pciGartSize); 5441 } 5442 5443 /* Make sure 3D clients will re-upload textures to video RAM */ 5444 if (info->textureSize) { 5445 RADEONSAREAPrivPtr pSAREAPriv = 5446 (RADEONSAREAPrivPtr)DRIGetSAREAPrivate(pScrn->pScreen); 5447 drmTextureRegionPtr list = pSAREAPriv->texList[0]; 5448 int age = ++pSAREAPriv->texAge[0]; 5449 5450 i = 0; 5451 5452 do { 5453 list[i].age = age; 5454 i = list[i].next; 5455 } while (i != 0); 5456 } 5457 } 5458#endif 5459 5460#ifndef HAVE_FREE_SHADOW 5461 for (i = 0; i < config->num_crtc; i++) { 5462 xf86CrtcPtr crtc = config->crtc[i]; 5463 5464 if (crtc->rotatedPixmap || crtc->rotatedData) { 5465 crtc->funcs->shadow_destroy(crtc, crtc->rotatedPixmap, 5466 crtc->rotatedData); 5467 crtc->rotatedPixmap = NULL; 5468 crtc->rotatedData = NULL; 5469 } 5470 } 5471#else 5472 xf86RotateFreeShadow(pScrn); 5473#endif 5474 5475 xf86_hide_cursors (pScrn); 5476 5477 RADEONRestore(pScrn); 5478 5479 for (i = 0; i < config->num_crtc; i++) 5480 radeon_crtc_modeset_ioctl(config->crtc[i], FALSE); 5481 5482 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5483 "Ok, leaving now...\n"); 5484} 5485 5486/* Called at the end of each server generation. Restore the original 5487 * text mode, unmap video memory, and unwrap and call the saved 5488 * CloseScreen function. 5489 */ 5490static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) 5491{ 5492 ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; 5493 RADEONInfoPtr info = RADEONPTR(pScrn); 5494 5495 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5496 "RADEONCloseScreen\n"); 5497 5498 /* Mark acceleration as stopped or we might try to access the engine at 5499 * wrong times, especially if we had DRI, after DRI has been stopped 5500 */ 5501 info->accelOn = FALSE; 5502 5503#ifdef XF86DRI 5504#ifdef DAMAGE 5505 if (info->pDamage) { 5506 PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen); 5507 5508 DamageUnregister(&pPix->drawable, info->pDamage); 5509 DamageDestroy(info->pDamage); 5510 info->pDamage = NULL; 5511 } 5512#endif 5513 5514 RADEONDRIStop(pScreen); 5515#endif 5516 5517#ifdef USE_XAA 5518 if(!info->useEXA && info->RenderTex) { 5519 xf86FreeOffscreenLinear(info->RenderTex); 5520 info->RenderTex = NULL; 5521 } 5522#endif /* USE_XAA */ 5523 5524 if (pScrn->vtSema) { 5525 RADEONRestore(pScrn); 5526 } 5527 5528 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5529 "Disposing accel...\n"); 5530#ifdef USE_EXA 5531 if (info->exa) { 5532 exaDriverFini(pScreen); 5533 xfree(info->exa); 5534 info->exa = NULL; 5535 } 5536#endif /* USE_EXA */ 5537#ifdef USE_XAA 5538 if (!info->useEXA) { 5539 if (info->accel) 5540 XAADestroyInfoRec(info->accel); 5541 info->accel = NULL; 5542 5543 if (info->scratch_save) 5544 xfree(info->scratch_save); 5545 info->scratch_save = NULL; 5546 } 5547#endif /* USE_XAA */ 5548 5549 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5550 "Disposing cursor info\n"); 5551 if (info->cursor) xf86DestroyCursorInfoRec(info->cursor); 5552 info->cursor = NULL; 5553 5554 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5555 "Disposing DGA\n"); 5556 if (info->DGAModes) xfree(info->DGAModes); 5557 info->DGAModes = NULL; 5558 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5559 "Unmapping memory\n"); 5560 RADEONUnmapMem(pScrn); 5561 5562 pScrn->vtSema = FALSE; 5563 5564 xf86ClearPrimInitDone(info->pEnt->index); 5565 5566 pScreen->BlockHandler = info->BlockHandler; 5567 pScreen->CloseScreen = info->CloseScreen; 5568 return (*pScreen->CloseScreen)(scrnIndex, pScreen); 5569} 5570 5571void RADEONFreeScreen(int scrnIndex, int flags) 5572{ 5573 ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; 5574 RADEONInfoPtr info = RADEONPTR(pScrn); 5575 5576 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5577 "RADEONFreeScreen\n"); 5578 5579 /* when server quits at PreInit, we don't need do this anymore*/ 5580 if (!info) return; 5581 5582#ifdef WITH_VGAHW 5583 if (info->VGAAccess && xf86LoaderCheckSymbol("vgaHWFreeHWRec")) 5584 vgaHWFreeHWRec(pScrn); 5585#endif 5586 RADEONFreeRec(pScrn); 5587} 5588 5589static void RADEONForceSomeClocks(ScrnInfoPtr pScrn) 5590{ 5591 /* It appears from r300 and rv100 may need some clocks forced-on */ 5592 uint32_t tmp; 5593 5594 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); 5595 tmp |= RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_VIP; 5596 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); 5597} 5598 5599static void RADEONSetDynamicClock(ScrnInfoPtr pScrn, int mode) 5600{ 5601 RADEONInfoPtr info = RADEONPTR(pScrn); 5602 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 5603 unsigned char *RADEONMMIO = info->MMIO; 5604 uint32_t tmp; 5605 switch(mode) { 5606 case 0: /* Turn everything OFF (ForceON to everything)*/ 5607 if ( !pRADEONEnt->HasCRTC2 ) { 5608 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); 5609 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP | 5610 RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_TOP | 5611 RADEON_SCLK_FORCE_E2 | RADEON_SCLK_FORCE_SE | 5612 RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_VIP | 5613 RADEON_SCLK_FORCE_RE | RADEON_SCLK_FORCE_PB | 5614 RADEON_SCLK_FORCE_TAM | RADEON_SCLK_FORCE_TDM | 5615 RADEON_SCLK_FORCE_RB); 5616 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); 5617 } else if (info->ChipFamily == CHIP_FAMILY_RV350) { 5618 /* for RV350/M10, no delays are required. */ 5619 tmp = INPLL(pScrn, R300_SCLK_CNTL2); 5620 tmp |= (R300_SCLK_FORCE_TCL | 5621 R300_SCLK_FORCE_GA | 5622 R300_SCLK_FORCE_CBA); 5623 OUTPLL(pScrn, R300_SCLK_CNTL2, tmp); 5624 5625 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); 5626 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | 5627 RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 | 5628 RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 | 5629 R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT | 5630 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR | 5631 R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX | 5632 R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK | 5633 R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0); 5634 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); 5635 5636 tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL); 5637 tmp |= RADEON_SCLK_MORE_FORCEON; 5638 OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp); 5639 5640 tmp = INPLL(pScrn, RADEON_MCLK_CNTL); 5641 tmp |= (RADEON_FORCEON_MCLKA | 5642 RADEON_FORCEON_MCLKB | 5643 RADEON_FORCEON_YCLKA | 5644 RADEON_FORCEON_YCLKB | 5645 RADEON_FORCEON_MC); 5646 OUTPLL(pScrn, RADEON_MCLK_CNTL, tmp); 5647 5648 tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); 5649 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | 5650 RADEON_PIXCLK_DAC_ALWAYS_ONb | 5651 R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF); 5652 OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp); 5653 5654 tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL); 5655 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | 5656 RADEON_PIX2CLK_DAC_ALWAYS_ONb | 5657 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | 5658 R300_DVOCLK_ALWAYS_ONb | 5659 RADEON_PIXCLK_BLEND_ALWAYS_ONb | 5660 RADEON_PIXCLK_GV_ALWAYS_ONb | 5661 R300_PIXCLK_DVO_ALWAYS_ONb | 5662 RADEON_PIXCLK_LVDS_ALWAYS_ONb | 5663 RADEON_PIXCLK_TMDS_ALWAYS_ONb | 5664 R300_PIXCLK_TRANS_ALWAYS_ONb | 5665 R300_PIXCLK_TVO_ALWAYS_ONb | 5666 R300_P2G2CLK_ALWAYS_ONb | 5667 R300_P2G2CLK_ALWAYS_ONb | 5668 R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF); 5669 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp); 5670 } else { 5671 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); 5672 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2); 5673 tmp |= RADEON_SCLK_FORCE_SE; 5674 5675 if ( !pRADEONEnt->HasCRTC2 ) { 5676 tmp |= ( RADEON_SCLK_FORCE_RB | 5677 RADEON_SCLK_FORCE_TDM | 5678 RADEON_SCLK_FORCE_TAM | 5679 RADEON_SCLK_FORCE_PB | 5680 RADEON_SCLK_FORCE_RE | 5681 RADEON_SCLK_FORCE_VIP | 5682 RADEON_SCLK_FORCE_IDCT | 5683 RADEON_SCLK_FORCE_TOP | 5684 RADEON_SCLK_FORCE_DISP1 | 5685 RADEON_SCLK_FORCE_DISP2 | 5686 RADEON_SCLK_FORCE_HDP ); 5687 } else if ((info->ChipFamily == CHIP_FAMILY_R300) || 5688 (info->ChipFamily == CHIP_FAMILY_R350)) { 5689 tmp |= ( RADEON_SCLK_FORCE_HDP | 5690 RADEON_SCLK_FORCE_DISP1 | 5691 RADEON_SCLK_FORCE_DISP2 | 5692 RADEON_SCLK_FORCE_TOP | 5693 RADEON_SCLK_FORCE_IDCT | 5694 RADEON_SCLK_FORCE_VIP); 5695 } 5696 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); 5697 5698 usleep(16000); 5699 5700 if ((info->ChipFamily == CHIP_FAMILY_R300) || 5701 (info->ChipFamily == CHIP_FAMILY_R350)) { 5702 tmp = INPLL(pScrn, R300_SCLK_CNTL2); 5703 tmp |= ( R300_SCLK_FORCE_TCL | 5704 R300_SCLK_FORCE_GA | 5705 R300_SCLK_FORCE_CBA); 5706 OUTPLL(pScrn, R300_SCLK_CNTL2, tmp); 5707 usleep(16000); 5708 } 5709 5710 if (info->IsIGP) { 5711 tmp = INPLL(pScrn, RADEON_MCLK_CNTL); 5712 tmp &= ~(RADEON_FORCEON_MCLKA | 5713 RADEON_FORCEON_YCLKA); 5714 OUTPLL(pScrn, RADEON_MCLK_CNTL, tmp); 5715 usleep(16000); 5716 } 5717 5718 if ((info->ChipFamily == CHIP_FAMILY_RV200) || 5719 (info->ChipFamily == CHIP_FAMILY_RV250) || 5720 (info->ChipFamily == CHIP_FAMILY_RV280)) { 5721 tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL); 5722 tmp |= RADEON_SCLK_MORE_FORCEON; 5723 OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp); 5724 usleep(16000); 5725 } 5726 5727 tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL); 5728 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | 5729 RADEON_PIX2CLK_DAC_ALWAYS_ONb | 5730 RADEON_PIXCLK_BLEND_ALWAYS_ONb | 5731 RADEON_PIXCLK_GV_ALWAYS_ONb | 5732 RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb | 5733 RADEON_PIXCLK_LVDS_ALWAYS_ONb | 5734 RADEON_PIXCLK_TMDS_ALWAYS_ONb); 5735 5736 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp); 5737 usleep(16000); 5738 5739 tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); 5740 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | 5741 RADEON_PIXCLK_DAC_ALWAYS_ONb); 5742 OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp); 5743 } 5744 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Dynamic Clock Scaling Disabled\n"); 5745 break; 5746 case 1: 5747 if (!pRADEONEnt->HasCRTC2) { 5748 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); 5749 if ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) > 5750 RADEON_CFG_ATI_REV_A13) { 5751 tmp &= ~(RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_RB); 5752 } 5753 tmp &= ~(RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 | 5754 RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_SE | 5755 RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_RE | 5756 RADEON_SCLK_FORCE_PB | RADEON_SCLK_FORCE_TAM | 5757 RADEON_SCLK_FORCE_TDM); 5758 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); 5759 } else if ((info->ChipFamily == CHIP_FAMILY_R300) || 5760 (info->ChipFamily == CHIP_FAMILY_R350) || 5761 (info->ChipFamily == CHIP_FAMILY_RV350)) { 5762 if (info->ChipFamily == CHIP_FAMILY_RV350) { 5763 tmp = INPLL(pScrn, R300_SCLK_CNTL2); 5764 tmp &= ~(R300_SCLK_FORCE_TCL | 5765 R300_SCLK_FORCE_GA | 5766 R300_SCLK_FORCE_CBA); 5767 tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT | 5768 R300_SCLK_GA_MAX_DYN_STOP_LAT | 5769 R300_SCLK_CBA_MAX_DYN_STOP_LAT); 5770 OUTPLL(pScrn, R300_SCLK_CNTL2, tmp); 5771 5772 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); 5773 tmp &= ~(RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | 5774 RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 | 5775 RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 | 5776 R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT | 5777 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR | 5778 R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX | 5779 R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK | 5780 R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0); 5781 tmp |= RADEON_DYN_STOP_LAT_MASK; 5782 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); 5783 5784 tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL); 5785 tmp &= ~RADEON_SCLK_MORE_FORCEON; 5786 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT; 5787 OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp); 5788 5789 tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); 5790 tmp |= (RADEON_PIXCLK_ALWAYS_ONb | 5791 RADEON_PIXCLK_DAC_ALWAYS_ONb); 5792 OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp); 5793 5794 tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL); 5795 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | 5796 RADEON_PIX2CLK_DAC_ALWAYS_ONb | 5797 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | 5798 R300_DVOCLK_ALWAYS_ONb | 5799 RADEON_PIXCLK_BLEND_ALWAYS_ONb | 5800 RADEON_PIXCLK_GV_ALWAYS_ONb | 5801 R300_PIXCLK_DVO_ALWAYS_ONb | 5802 RADEON_PIXCLK_LVDS_ALWAYS_ONb | 5803 RADEON_PIXCLK_TMDS_ALWAYS_ONb | 5804 R300_PIXCLK_TRANS_ALWAYS_ONb | 5805 R300_PIXCLK_TVO_ALWAYS_ONb | 5806 R300_P2G2CLK_ALWAYS_ONb | 5807 R300_P2G2CLK_ALWAYS_ONb); 5808 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp); 5809 5810 tmp = INPLL(pScrn, RADEON_MCLK_MISC); 5811 tmp |= (RADEON_MC_MCLK_DYN_ENABLE | 5812 RADEON_IO_MCLK_DYN_ENABLE); 5813 OUTPLL(pScrn, RADEON_MCLK_MISC, tmp); 5814 5815 tmp = INPLL(pScrn, RADEON_MCLK_CNTL); 5816 tmp |= (RADEON_FORCEON_MCLKA | 5817 RADEON_FORCEON_MCLKB); 5818 5819 tmp &= ~(RADEON_FORCEON_YCLKA | 5820 RADEON_FORCEON_YCLKB | 5821 RADEON_FORCEON_MC); 5822 5823 /* Some releases of vbios have set DISABLE_MC_MCLKA 5824 and DISABLE_MC_MCLKB bits in the vbios table. Setting these 5825 bits will cause H/W hang when reading video memory with dynamic clocking 5826 enabled. */ 5827 if ((tmp & R300_DISABLE_MC_MCLKA) && 5828 (tmp & R300_DISABLE_MC_MCLKB)) { 5829 /* If both bits are set, then check the active channels */ 5830 tmp = INPLL(pScrn, RADEON_MCLK_CNTL); 5831 if (info->RamWidth == 64) { 5832 if (INREG(RADEON_MEM_CNTL) & R300_MEM_USE_CD_CH_ONLY) 5833 tmp &= ~R300_DISABLE_MC_MCLKB; 5834 else 5835 tmp &= ~R300_DISABLE_MC_MCLKA; 5836 } else { 5837 tmp &= ~(R300_DISABLE_MC_MCLKA | 5838 R300_DISABLE_MC_MCLKB); 5839 } 5840 } 5841 5842 OUTPLL(pScrn, RADEON_MCLK_CNTL, tmp); 5843 } else { 5844 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); 5845 tmp &= ~(R300_SCLK_FORCE_VAP); 5846 tmp |= RADEON_SCLK_FORCE_CP; 5847 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); 5848 usleep(15000); 5849 5850 tmp = INPLL(pScrn, R300_SCLK_CNTL2); 5851 tmp &= ~(R300_SCLK_FORCE_TCL | 5852 R300_SCLK_FORCE_GA | 5853 R300_SCLK_FORCE_CBA); 5854 OUTPLL(pScrn, R300_SCLK_CNTL2, tmp); 5855 } 5856 } else { 5857 tmp = INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL); 5858 5859 tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK | 5860 RADEON_DISP_DYN_STOP_LAT_MASK | 5861 RADEON_DYN_STOP_MODE_MASK); 5862 5863 tmp |= (RADEON_ENGIN_DYNCLK_MODE | 5864 (0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT)); 5865 OUTPLL(pScrn, RADEON_CLK_PWRMGT_CNTL, tmp); 5866 usleep(15000); 5867 5868 tmp = INPLL(pScrn, RADEON_CLK_PIN_CNTL); 5869 tmp |= RADEON_SCLK_DYN_START_CNTL; 5870 OUTPLL(pScrn, RADEON_CLK_PIN_CNTL, tmp); 5871 usleep(15000); 5872 5873 /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200 5874 to lockup randomly, leave them as set by BIOS. 5875 */ 5876 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); 5877 /*tmp &= RADEON_SCLK_SRC_SEL_MASK;*/ 5878 tmp &= ~RADEON_SCLK_FORCEON_MASK; 5879 5880 /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300*/ 5881 if (((info->ChipFamily == CHIP_FAMILY_RV250) && 5882 ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) < 5883 RADEON_CFG_ATI_REV_A13)) || 5884 ((info->ChipFamily == CHIP_FAMILY_RV100) && 5885 ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <= 5886 RADEON_CFG_ATI_REV_A13))){ 5887 tmp |= RADEON_SCLK_FORCE_CP; 5888 tmp |= RADEON_SCLK_FORCE_VIP; 5889 } 5890 5891 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); 5892 5893 if ((info->ChipFamily == CHIP_FAMILY_RV200) || 5894 (info->ChipFamily == CHIP_FAMILY_RV250) || 5895 (info->ChipFamily == CHIP_FAMILY_RV280)) { 5896 tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL); 5897 tmp &= ~RADEON_SCLK_MORE_FORCEON; 5898 5899 /* RV200::A11 A12 RV250::A11 A12 */ 5900 if (((info->ChipFamily == CHIP_FAMILY_RV200) || 5901 (info->ChipFamily == CHIP_FAMILY_RV250)) && 5902 ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) < 5903 RADEON_CFG_ATI_REV_A13)) { 5904 tmp |= RADEON_SCLK_MORE_FORCEON; 5905 } 5906 OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp); 5907 usleep(15000); 5908 } 5909 5910 /* RV200::A11 A12, RV250::A11 A12 */ 5911 if (((info->ChipFamily == CHIP_FAMILY_RV200) || 5912 (info->ChipFamily == CHIP_FAMILY_RV250)) && 5913 ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) < 5914 RADEON_CFG_ATI_REV_A13)) { 5915 tmp = INPLL(pScrn, RADEON_PLL_PWRMGT_CNTL); 5916 tmp |= RADEON_TCL_BYPASS_DISABLE; 5917 OUTPLL(pScrn, RADEON_PLL_PWRMGT_CNTL, tmp); 5918 } 5919 usleep(15000); 5920 5921 /*enable dynamic mode for display clocks (PIXCLK and PIX2CLK)*/ 5922 tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL); 5923 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | 5924 RADEON_PIX2CLK_DAC_ALWAYS_ONb | 5925 RADEON_PIXCLK_BLEND_ALWAYS_ONb | 5926 RADEON_PIXCLK_GV_ALWAYS_ONb | 5927 RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb | 5928 RADEON_PIXCLK_LVDS_ALWAYS_ONb | 5929 RADEON_PIXCLK_TMDS_ALWAYS_ONb); 5930 5931 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp); 5932 usleep(15000); 5933 5934 tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); 5935 tmp |= (RADEON_PIXCLK_ALWAYS_ONb | 5936 RADEON_PIXCLK_DAC_ALWAYS_ONb); 5937 5938 OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp); 5939 usleep(15000); 5940 } 5941 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Dynamic Clock Scaling Enabled\n"); 5942 break; 5943 default: 5944 break; 5945 } 5946} 5947