radeon_kms.c revision 0974d292 
1/*
2 * Copyright © 2009 Red Hat, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 *    Dave Airlie <airlied@redhat.com>
25 *
26 */
27#ifdef HAVE_CONFIG_H
28#include "config.h"
29#endif
30
31#include <errno.h>
32#include <sys/ioctl.h>
33/* Driver data structures */
34#include "radeon.h"
35#include "radeon_reg.h"
36#include "radeon_probe.h"
37#include "micmap.h"
38
39#include "shadow.h"
40
41#include "atipciids.h"
42
43
44#ifdef XF86DRM_MODE
45
46#include "radeon_chipset_gen.h"
47#include "radeon_chipinfo_gen.h"
48
49#define CURSOR_WIDTH	64
50#define CURSOR_HEIGHT	64
51
52#include "radeon_bo_gem.h"
53#include "radeon_cs_gem.h"
54#include "radeon_vbo.h"
55
56static Bool radeon_setup_kernel_mem(ScreenPtr pScreen);
57
58const OptionInfoRec RADEONOptions_KMS[] = {
59    { OPTION_NOACCEL,        "NoAccel",          OPTV_BOOLEAN, {0}, FALSE },
60    { OPTION_SW_CURSOR,      "SWcursor",         OPTV_BOOLEAN, {0}, FALSE },
61    { OPTION_PAGE_FLIP,      "EnablePageFlip",   OPTV_BOOLEAN, {0}, FALSE },
62    { OPTION_ACCEL_DFS,      "AccelDFS",         OPTV_BOOLEAN, {0}, FALSE },
63    { OPTION_IGNORE_EDID,    "IgnoreEDID",       OPTV_BOOLEAN, {0}, FALSE },
64    { OPTION_COLOR_TILING,   "ColorTiling",      OPTV_BOOLEAN, {0}, FALSE },
65    { OPTION_RENDER_ACCEL,   "RenderAccel",      OPTV_BOOLEAN, {0}, FALSE },
66    { OPTION_SUBPIXEL_ORDER, "SubPixelOrder",    OPTV_ANYSTR,  {0}, FALSE },
67    { OPTION_ACCELMETHOD,    "AccelMethod",      OPTV_STRING,  {0}, FALSE },
68    { OPTION_DRI,            "DRI",       	 OPTV_BOOLEAN, {0}, FALSE },
69    { OPTION_TVSTD,          "TVStandard",       OPTV_STRING,  {0}, FALSE },
70    { OPTION_EXA_VSYNC,      "EXAVSync",         OPTV_BOOLEAN, {0}, FALSE },
71    { OPTION_EXA_PIXMAPS,    "EXAPixmaps",	 OPTV_BOOLEAN,   {0}, FALSE },
72    { OPTION_ZAPHOD_HEADS,   "ZaphodHeads",      OPTV_STRING,  {0}, FALSE },
73    { -1,                    NULL,               OPTV_NONE,    {0}, FALSE }
74};
75
76void radeon_cs_flush_indirect(ScrnInfoPtr pScrn)
77{
78    RADEONInfoPtr  info = RADEONPTR(pScrn);
79    struct radeon_accel_state *accel_state = info->accel_state;
80    int ret;
81
82    if (!info->cs->cdw)
83	return;
84
85    /* release the current VBO so we don't block on mapping it later */
86    if (info->accel_state->vb_offset && info->accel_state->vb_bo) {
87        radeon_vbo_put(pScrn);
88        info->accel_state->vb_start_op = -1;
89    }
90
91    radeon_cs_emit(info->cs);
92    radeon_cs_erase(info->cs);
93
94    if (accel_state->use_vbos)
95        radeon_vbo_flush_bos(pScrn);
96
97    ret = radeon_cs_space_check_with_bo(info->cs,
98					accel_state->vb_bo,
99					RADEON_GEM_DOMAIN_GTT, 0);
100    if (ret)
101      ErrorF("space check failed in flush\n");
102
103    if (info->reemit_current2d && info->state_2d.op)
104        info->reemit_current2d(pScrn, info->state_2d.op);
105
106    if (info->dri2.enabled) {
107        info->accel_state->XInited3D = FALSE;
108        info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
109    }
110
111}
112
113void radeon_ddx_cs_start(ScrnInfoPtr pScrn,
114			 int n, const char *file,
115			 const char *func, int line)
116{
117    RADEONInfoPtr  info = RADEONPTR(pScrn);
118
119    if (info->cs->cdw + n > info->cs->ndw) {
120	radeon_cs_flush_indirect(pScrn);
121
122    }
123    radeon_cs_begin(info->cs, n, file, func, line);
124}
125
126
127extern _X_EXPORT int gRADEONEntityIndex;
128
129static int getRADEONEntityIndex(void)
130{
131    return gRADEONEntityIndex;
132}
133
134static void *
135radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode,
136		   CARD32 *size, void *closure)
137{
138    ScrnInfoPtr pScrn = xf86Screens[screen->myNum];
139    RADEONInfoPtr  info   = RADEONPTR(pScrn);
140    int stride;
141
142    stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8;
143    *size = stride;
144
145    return ((uint8_t *)info->front_bo->ptr + row * stride + offset);
146}
147
148static Bool RADEONCreateScreenResources_KMS(ScreenPtr pScreen)
149{
150    ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
151    RADEONInfoPtr  info   = RADEONPTR(pScrn);
152    PixmapPtr pixmap;
153
154    pScreen->CreateScreenResources = info->CreateScreenResources;
155    if (!(*pScreen->CreateScreenResources)(pScreen))
156	return FALSE;
157    pScreen->CreateScreenResources = RADEONCreateScreenResources_KMS;
158
159    if (!drmmode_set_desired_modes(pScrn, &info->drmmode))
160	return FALSE;
161
162    drmmode_uevent_init(pScrn, &info->drmmode);
163
164    if (info->r600_shadow_fb) {
165	pixmap = pScreen->GetScreenPixmap(pScreen);
166
167	if (!shadowAdd(pScreen, pixmap, shadowUpdatePackedWeak(),
168		       radeonShadowWindow, 0, NULL))
169	    return FALSE;
170    }
171
172    if (info->dri2.enabled) {
173	if (info->front_bo) {
174	    PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen);
175	    radeon_set_pixmap_bo(pPix, info->front_bo);
176	}
177    }
178    return TRUE;
179}
180
181static void RADEONBlockHandler_KMS(int i, pointer blockData,
182				   pointer pTimeout, pointer pReadmask)
183{
184    ScreenPtr      pScreen = screenInfo.screens[i];
185    ScrnInfoPtr    pScrn   = xf86Screens[i];
186    RADEONInfoPtr  info    = RADEONPTR(pScrn);
187
188    pScreen->BlockHandler = info->BlockHandler;
189    (*pScreen->BlockHandler) (i, blockData, pTimeout, pReadmask);
190    pScreen->BlockHandler = RADEONBlockHandler_KMS;
191
192    if (info->VideoTimerCallback)
193	(*info->VideoTimerCallback)(pScrn, currentTime.milliseconds);
194}
195
196static void
197radeon_flush_callback(CallbackListPtr *list,
198		      pointer user_data, pointer call_data)
199{
200    ScrnInfoPtr pScrn = user_data;
201
202    if (pScrn->vtSema) {
203        radeon_cs_flush_indirect(pScrn);
204    }
205}
206
207static Bool RADEONIsAccelWorking(ScrnInfoPtr pScrn)
208{
209    RADEONInfoPtr info = RADEONPTR(pScrn);
210    struct drm_radeon_info ginfo;
211    int r;
212    uint32_t tmp;
213
214    memset(&ginfo, 0, sizeof(ginfo));
215    ginfo.request = 0x3;
216    ginfo.value = (uintptr_t)&tmp;
217    r = drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INFO, &ginfo, sizeof(ginfo));
218    if (r) {
219        /* If kernel is too old before 2.6.32 than assume accel is working */
220        if (r == -EINVAL) {
221            xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Kernel too old missing accel "
222                       "information, assuming accel is working\n");
223            return TRUE;
224        }
225        return FALSE;
226    }
227    if (tmp)
228        return TRUE;
229    return FALSE;
230}
231
232static Bool RADEONPreInitAccel_KMS(ScrnInfoPtr pScrn)
233{
234    RADEONInfoPtr  info = RADEONPTR(pScrn);
235
236    if (!(info->accel_state = calloc(1, sizeof(struct radeon_accel_state)))) {
237	xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to allocate accel_state rec!\n");
238	return FALSE;
239    }
240
241    if (xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE) ||
242	(info->ChipFamily >= CHIP_FAMILY_CEDAR) ||
243	(!RADEONIsAccelWorking(pScrn))) {
244	xf86DrvMsg(pScrn->scrnIndex, X_INFO,
245		   "GPU accel disabled or not working, using shadowfb for KMS\n");
246	info->r600_shadow_fb = TRUE;
247	if (!xf86LoadSubModule(pScrn, "shadow"))
248	    info->r600_shadow_fb = FALSE;
249	return TRUE;
250    }
251
252    if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
253	(info->ChipFamily == CHIP_FAMILY_RS200) ||
254	(info->ChipFamily == CHIP_FAMILY_RS300) ||
255	(info->ChipFamily == CHIP_FAMILY_RS400) ||
256	(info->ChipFamily == CHIP_FAMILY_RS480) ||
257	(info->ChipFamily == CHIP_FAMILY_RS600) ||
258	(info->ChipFamily == CHIP_FAMILY_RS690) ||
259	(info->ChipFamily == CHIP_FAMILY_RS740))
260	info->accel_state->has_tcl = FALSE;
261    else {
262	info->accel_state->has_tcl = TRUE;
263    }
264
265    info->useEXA = TRUE;
266
267    if (info->useEXA) {
268	int errmaj = 0, errmin = 0;
269	info->exaReq.majorversion = EXA_VERSION_MAJOR;
270	info->exaReq.minorversion = EXA_VERSION_MINOR;
271	if (!LoadSubModule(pScrn->module, "exa", NULL, NULL, NULL,
272			   &info->exaReq, &errmaj, &errmin)) {
273	    LoaderErrorMsg(NULL, "exa", errmaj, errmin);
274	    return FALSE;
275	}
276    }
277
278    return TRUE;
279}
280
281static Bool RADEONPreInitChipType_KMS(ScrnInfoPtr pScrn)
282{
283    RADEONInfoPtr  info   = RADEONPTR(pScrn);
284    uint32_t cmd_stat;
285    int i;
286
287    info->Chipset = PCI_DEV_DEVICE_ID(info->PciInfo);
288    pScrn->chipset = (char *)xf86TokenToString(RADEONChipsets, info->Chipset);
289    if (!pScrn->chipset) {
290	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
291		   "ChipID 0x%04x is not recognized\n", info->Chipset);
292	return FALSE;
293    }
294
295    if (info->Chipset < 0) {
296	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
297		   "Chipset \"%s\" is not recognized\n", pScrn->chipset);
298	return FALSE;
299    }
300    xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
301	       "Chipset: \"%s\" (ChipID = 0x%04x)\n",
302	       pScrn->chipset,
303	       info->Chipset);
304
305    for (i = 0; i < sizeof(RADEONCards) / sizeof(RADEONCardInfo); i++) {
306	if (info->Chipset == RADEONCards[i].pci_device_id) {
307	    RADEONCardInfo *card = &RADEONCards[i];
308	    info->ChipFamily = card->chip_family;
309	    info->IsMobility = card->mobility;
310	    info->IsIGP = card->igp;
311	    break;
312	}
313    }
314
315    info->cardType = CARD_PCI;
316
317    PCI_READ_LONG(info->PciInfo, &cmd_stat, PCI_CMD_STAT_REG);
318    if (cmd_stat & RADEON_CAP_LIST) {
319	uint32_t cap_ptr, cap_id;
320
321	PCI_READ_LONG(info->PciInfo, &cap_ptr, RADEON_CAPABILITIES_PTR_PCI_CONFIG);
322	cap_ptr &= RADEON_CAP_PTR_MASK;
323
324	while(cap_ptr != RADEON_CAP_ID_NULL) {
325	    PCI_READ_LONG(info->PciInfo, &cap_id, cap_ptr);
326	    if ((cap_id & 0xff)== RADEON_CAP_ID_AGP) {
327		info->cardType = CARD_AGP;
328		break;
329	    }
330	    if ((cap_id & 0xff)== RADEON_CAP_ID_EXP) {
331		info->cardType = CARD_PCIE;
332		break;
333	    }
334	    cap_ptr = (cap_id >> 8) & RADEON_CAP_PTR_MASK;
335	}
336    }
337
338
339    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s card detected\n",
340	       (info->cardType==CARD_PCI) ? "PCI" :
341		(info->cardType==CARD_PCIE) ? "PCIE" : "AGP");
342
343    /* treat PCIE IGP cards as PCI */
344    if (info->cardType == CARD_PCIE && info->IsIGP)
345	info->cardType = CARD_PCI;
346
347    if ((info->ChipFamily >= CHIP_FAMILY_R600) && info->IsIGP)
348	info->cardType = CARD_PCIE;
349
350    /* not sure about gart table requirements */
351    if ((info->ChipFamily == CHIP_FAMILY_RS600) && info->IsIGP)
352	info->cardType = CARD_PCIE;
353
354#ifdef RENDER
355    info->RenderAccel = xf86ReturnOptValBool(info->Options, OPTION_RENDER_ACCEL,
356					     info->Chipset != PCI_CHIP_RN50_515E &&
357					     info->Chipset != PCI_CHIP_RN50_5969);
358#endif
359    return TRUE;
360}
361
362static Bool radeon_alloc_dri(ScrnInfoPtr pScrn)
363{
364    RADEONInfoPtr  info   = RADEONPTR(pScrn);
365    if (!(info->dri = calloc(1, sizeof(struct radeon_dri)))) {
366	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate dri rec!\n");
367	return FALSE;
368    }
369
370    if (!(info->cp = calloc(1, sizeof(struct radeon_cp)))) {
371	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate cp rec!\n");
372	return FALSE;
373    }
374    return TRUE;
375}
376
377static Bool radeon_open_drm_master(ScrnInfoPtr pScrn)
378{
379    RADEONInfoPtr  info   = RADEONPTR(pScrn);
380    RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
381    struct pci_device *dev = info->PciInfo;
382    char *busid;
383    drmSetVersion sv;
384    int err;
385
386    if (pRADEONEnt->fd) {
387	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
388		   " reusing fd for second head\n");
389
390	info->dri2.drm_fd = pRADEONEnt->fd;
391	goto out;
392    }
393
394    busid = XNFprintf("pci:%04x:%02x:%02x.%d",
395		      dev->domain, dev->bus, dev->dev, dev->func);
396
397    info->dri2.drm_fd = drmOpen("radeon", busid);
398    if (info->dri2.drm_fd == -1) {
399
400	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
401		   "[drm] Failed to open DRM device for %s: %s\n",
402		   busid, strerror(errno));
403	free(busid);
404	return FALSE;
405    }
406    free(busid);
407
408    /* Check that what we opened was a master or a master-capable FD,
409     * by setting the version of the interface we'll use to talk to it.
410     * (see DRIOpenDRMMaster() in DRI1)
411     */
412    sv.drm_di_major = 1;
413    sv.drm_di_minor = 1;
414    sv.drm_dd_major = -1;
415    sv.drm_dd_minor = -1;
416    err = drmSetInterfaceVersion(info->dri2.drm_fd, &sv);
417    if (err != 0) {
418	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
419		   "[drm] failed to set drm interface version.\n");
420	drmClose(info->dri2.drm_fd);
421	info->dri2.drm_fd = -1;
422
423	return FALSE;
424    }
425
426    pRADEONEnt->fd = info->dri2.drm_fd;
427 out:
428    info->drmmode.fd = info->dri2.drm_fd;
429    info->dri->drmFD = info->dri2.drm_fd;
430    return TRUE;
431}
432
433static Bool r600_get_tile_config(ScrnInfoPtr pScrn)
434{
435    RADEONInfoPtr  info   = RADEONPTR(pScrn);
436    struct drm_radeon_info ginfo;
437    int r;
438    uint32_t tmp;
439
440    if (info->ChipFamily < CHIP_FAMILY_R600)
441	return FALSE;
442
443#ifndef RADEON_INFO_TILING_CONFIG
444#define RADEON_INFO_TILING_CONFIG 0x6
445#endif
446
447    memset(&ginfo, 0, sizeof(ginfo));
448    ginfo.request = RADEON_INFO_TILING_CONFIG;
449    ginfo.value = (uintptr_t)&tmp;
450    r = drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INFO, &ginfo, sizeof(ginfo));
451    if (r)
452	return FALSE;
453
454    info->tile_config = tmp;
455    info->r7xx_bank_op = 0;
456    if (info->ChipFamily >= CHIP_FAMILY_CEDAR) {
457	/* for now */
458	return FALSE;
459    } else {
460	switch((info->tile_config & 0xe) >> 1) {
461	case 0:
462	    info->num_channels = 1;
463	    break;
464	case 1:
465	    info->num_channels = 2;
466	    break;
467	case 2:
468	    info->num_channels = 4;
469	    break;
470	case 3:
471	    info->num_channels = 8;
472	    break;
473	default:
474	    return FALSE;
475	}
476	switch((info->tile_config & 0x30) >> 4) {
477	case 0:
478	    info->num_banks = 4;
479	    break;
480	case 1:
481	    info->num_banks = 8;
482	    break;
483	default:
484	    return FALSE;
485	}
486	switch((info->tile_config & 0xc0) >> 6) {
487	case 0:
488	    info->group_bytes = 256;
489	    break;
490	case 1:
491	    info->group_bytes = 512;
492	    break;
493	default:
494	    return FALSE;
495	}
496    }
497
498    return TRUE;
499}
500
501Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
502{
503    RADEONInfoPtr     info;
504    RADEONEntPtr pRADEONEnt;
505    DevUnion* pPriv;
506    Gamma  zeros = { 0.0, 0.0, 0.0 };
507    Bool colorTilingDefault;
508
509    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
510		   "RADEONPreInit_KMS\n");
511    if (pScrn->numEntities != 1) return FALSE;
512    if (!RADEONGetRec(pScrn)) return FALSE;
513
514    info               = RADEONPTR(pScrn);
515    info->MMIO         = NULL;
516    info->IsSecondary  = FALSE;
517    info->IsPrimary = FALSE;
518    info->kms_enabled = TRUE;
519    info->pEnt         = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]);
520    if (info->pEnt->location.type != BUS_PCI) goto fail;
521
522    pPriv = xf86GetEntityPrivate(pScrn->entityList[0],
523				 getRADEONEntityIndex());
524    pRADEONEnt = pPriv->ptr;
525
526    if(xf86IsEntityShared(pScrn->entityList[0]))
527    {
528        if(xf86IsPrimInitDone(pScrn->entityList[0]))
529        {
530            info->IsSecondary = TRUE;
531            pRADEONEnt->pSecondaryScrn = pScrn;
532        }
533        else
534        {
535	    info->IsPrimary = TRUE;
536            xf86SetPrimInitDone(pScrn->entityList[0]);
537            pRADEONEnt->pPrimaryScrn = pScrn;
538            pRADEONEnt->HasSecondary = FALSE;
539        }
540    }
541
542    info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index);
543    pScrn->monitor     = pScrn->confScreen->monitor;
544
545    if (!RADEONPreInitVisual(pScrn))
546	goto fail;
547
548    xf86CollectOptions(pScrn, NULL);
549    if (!(info->Options = malloc(sizeof(RADEONOptions_KMS))))
550	goto fail;
551
552    memcpy(info->Options, RADEONOptions_KMS, sizeof(RADEONOptions_KMS));
553    xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options);
554
555    if (!RADEONPreInitWeight(pScrn))
556	goto fail;
557
558    if (!RADEONPreInitChipType_KMS(pScrn))
559        goto fail;
560
561    if (!radeon_alloc_dri(pScrn))
562	return FALSE;
563
564    if (radeon_open_drm_master(pScrn) == FALSE) {
565	xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Kernel modesetting setup failed\n");
566	goto fail;
567    }
568
569    info->dri2.enabled = FALSE;
570    info->dri->pKernelDRMVersion = drmGetVersion(info->dri->drmFD);
571    if (info->dri->pKernelDRMVersion == NULL) {
572	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
573		   "RADEONDRIGetVersion failed to get the DRM version\n");
574	goto fail;
575    }
576
577    colorTilingDefault = info->ChipFamily >= CHIP_FAMILY_R300 &&
578                         info->ChipFamily <= CHIP_FAMILY_RS740;
579
580    if (info->ChipFamily >= CHIP_FAMILY_R600) {
581	if (info->dri->pKernelDRMVersion->version_minor >= 6) {
582	    info->allowColorTiling = xf86ReturnOptValBool(info->Options,
583							  OPTION_COLOR_TILING, colorTilingDefault);
584	    if (info->allowColorTiling)
585		info->allowColorTiling = r600_get_tile_config(pScrn);
586	} else
587	    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
588		       "R6xx+ KMS Color Tiling requires radeon drm 2.6.0 or newer\n");
589    } else
590	info->allowColorTiling = xf86ReturnOptValBool(info->Options,
591						      OPTION_COLOR_TILING, colorTilingDefault);
592
593    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
594	 "KMS Color Tiling: %sabled\n", info->allowColorTiling ? "en" : "dis");
595
596    if (drmmode_pre_init(pScrn, &info->drmmode, pScrn->bitsPerPixel / 8) == FALSE) {
597	xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Kernel modesetting setup failed\n");
598	goto fail;
599    }
600
601    if (info->drmmode.mode_res->count_crtcs == 1)
602        pRADEONEnt->HasCRTC2 = FALSE;
603    else
604        pRADEONEnt->HasCRTC2 = TRUE;
605
606
607    /* fix up cloning on rn50 cards
608     * since they only have one crtc sometimes the xserver doesn't assign
609     * a crtc to one of the outputs even though both outputs have common modes
610     * which results in only one monitor being enabled.  Assign a crtc here so
611     * that both outputs light up.
612     */
613    if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) {
614	xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
615	int i;
616
617	for (i = 0; i < xf86_config->num_output; i++) {
618	    xf86OutputPtr output = xf86_config->output[i];
619
620	    /* XXX: double check crtc mode */
621	    if ((output->probed_modes != NULL) && (output->crtc == NULL))
622		output->crtc = xf86_config->crtc[0];
623	}
624    }
625
626    {
627	struct drm_radeon_gem_info mminfo;
628
629	if (!drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo)))
630	{
631	    info->vram_size = mminfo.vram_visible;
632	    info->gart_size = mminfo.gart_size;
633	    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
634		       "mem size init: gart size :%llx vram size: s:%llx visible:%llx\n",
635		       (unsigned long long)mminfo.gart_size,
636		       (unsigned long long)mminfo.vram_size,
637		       (unsigned long long)mminfo.vram_visible);
638	}
639    }
640
641    info->exa_pixmaps = xf86ReturnOptValBool(info->Options,
642                                             OPTION_EXA_PIXMAPS,
643					     ((info->vram_size > (32 * 1024 * 1024) &&
644					      info->RenderAccel)));
645    if (info->exa_pixmaps)
646    	xf86DrvMsg(pScrn->scrnIndex, X_INFO,
647		"EXA: Driver will allow EXA pixmaps in VRAM\n");
648    else
649    	xf86DrvMsg(pScrn->scrnIndex, X_INFO,
650		"EXA: Driver will not allow EXA pixmaps in VRAM\n");
651    RADEONSetPitch(pScrn);
652
653    /* Set display resolution */
654    xf86SetDpi(pScrn, 0, 0);
655
656	/* Get ScreenInit function */
657    if (!xf86LoadSubModule(pScrn, "fb")) return FALSE;
658
659    if (!xf86SetGamma(pScrn, zeros)) return FALSE;
660
661    if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) {
662	if (!xf86LoadSubModule(pScrn, "ramdac")) return FALSE;
663    }
664
665    if (!RADEONPreInitAccel_KMS(pScrn))              goto fail;
666
667    if (pScrn->modes == NULL) {
668      xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No modes.\n");
669      goto fail;
670   }
671
672    return TRUE;
673 fail:
674    RADEONFreeRec(pScrn);
675    return FALSE;
676
677}
678
679static Bool RADEONCursorInit_KMS(ScreenPtr pScreen)
680{
681    return xf86_cursors_init (pScreen, CURSOR_WIDTH, CURSOR_HEIGHT,
682			      (HARDWARE_CURSOR_TRUECOLOR_AT_8BPP |
683			       HARDWARE_CURSOR_AND_SOURCE_WITH_MASK |
684			       HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_1 |
685			       HARDWARE_CURSOR_UPDATE_UNHIDDEN |
686			       HARDWARE_CURSOR_ARGB));
687}
688
689static Bool RADEONSaveScreen_KMS(ScreenPtr pScreen, int mode)
690{
691    ScrnInfoPtr  pScrn = xf86Screens[pScreen->myNum];
692    Bool         unblank;
693
694    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
695		   "RADEONSaveScreen(%d)\n", mode);
696
697    unblank = xf86IsUnblank(mode);
698    if (unblank) SetTimeSinceLastInputEvent();
699
700    if ((pScrn != NULL) && pScrn->vtSema) {
701	if (unblank)
702	    RADEONUnblank(pScrn);
703	else
704	    RADEONBlank(pScrn);
705    }
706    return TRUE;
707}
708
709/* Called at the end of each server generation.  Restore the original
710 * text mode, unmap video memory, and unwrap and call the saved
711 * CloseScreen function.
712 */
713static Bool RADEONCloseScreen_KMS(int scrnIndex, ScreenPtr pScreen)
714{
715    ScrnInfoPtr    pScrn = xf86Screens[scrnIndex];
716    RADEONInfoPtr  info  = RADEONPTR(pScrn);
717
718    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
719		   "RADEONCloseScreen\n");
720
721    drmmode_uevent_fini(pScrn, &info->drmmode);
722    if (info->cs)
723      radeon_cs_flush_indirect(pScrn);
724
725    DeleteCallback(&FlushCallback, radeon_flush_callback, pScrn);
726
727    if (info->accel_state->exa) {
728	exaDriverFini(pScreen);
729	free(info->accel_state->exa);
730	info->accel_state->exa = NULL;
731    }
732
733    if (info->accel_state->use_vbos)
734        radeon_vbo_free_lists(pScrn);
735
736    drmDropMaster(info->dri->drmFD);
737
738    if (info->cursor) xf86DestroyCursorInfoRec(info->cursor);
739    info->cursor = NULL;
740
741    radeon_dri2_close_screen(pScreen);
742
743    pScrn->vtSema = FALSE;
744    xf86ClearPrimInitDone(info->pEnt->index);
745    pScreen->BlockHandler = info->BlockHandler;
746    pScreen->CloseScreen = info->CloseScreen;
747    return (*pScreen->CloseScreen)(scrnIndex, pScreen);
748}
749
750
751void RADEONFreeScreen_KMS(int scrnIndex, int flags)
752{
753    ScrnInfoPtr  pScrn = xf86Screens[scrnIndex];
754    RADEONInfoPtr  info  = RADEONPTR(pScrn);
755
756    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
757		   "RADEONFreeScreen\n");
758
759    /* when server quits at PreInit, we don't need do this anymore*/
760    if (!info) return;
761
762    RADEONFreeRec(pScrn);
763}
764
765Bool RADEONScreenInit_KMS(int scrnIndex, ScreenPtr pScreen,
766			  int argc, char **argv)
767{
768    ScrnInfoPtr    pScrn = xf86Screens[pScreen->myNum];
769    RADEONInfoPtr  info  = RADEONPTR(pScrn);
770    int            subPixelOrder = SubPixelUnknown;
771    char*          s;
772    void *front_ptr;
773    int ret;
774
775    pScrn->fbOffset = 0;
776
777    miClearVisualTypes();
778    if (!miSetVisualTypes(pScrn->depth,
779			  miGetDefaultVisualMask(pScrn->depth),
780			  pScrn->rgbBits,
781			  pScrn->defaultVisual)) return FALSE;
782    miSetPixmapDepths ();
783
784    ret = drmSetMaster(info->dri->drmFD);
785    if (ret) {
786        ErrorF("Unable to retrieve master\n");
787        return FALSE;
788    }
789    info->directRenderingEnabled = FALSE;
790    if (info->r600_shadow_fb == FALSE)
791        info->directRenderingEnabled = radeon_dri2_screen_init(pScreen);
792
793    front_ptr = info->FB;
794
795    if (!info->bufmgr)
796        info->bufmgr = radeon_bo_manager_gem_ctor(info->dri->drmFD);
797    if (!info->bufmgr) {
798	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
799		   "failed to initialise GEM buffer manager");
800	return FALSE;
801    }
802    drmmode_set_bufmgr(pScrn, &info->drmmode, info->bufmgr);
803
804    if (!info->csm)
805        info->csm = radeon_cs_manager_gem_ctor(info->dri->drmFD);
806    if (!info->csm) {
807	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
808		   "failed to initialise command submission manager");
809	return FALSE;
810    }
811
812    if (!info->cs)
813        info->cs = radeon_cs_create(info->csm, RADEON_BUFFER_SIZE/4);
814    if (!info->cs) {
815	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
816		   "failed to initialise command submission buffer");
817	return FALSE;
818    }
819
820    radeon_cs_set_limit(info->cs, RADEON_GEM_DOMAIN_GTT, info->gart_size);
821    radeon_cs_space_set_flush(info->cs, (void(*)(void *))radeon_cs_flush_indirect, pScrn);
822
823    radeon_setup_kernel_mem(pScreen);
824    front_ptr = info->front_bo->ptr;
825
826    if (info->r600_shadow_fb) {
827	info->fb_shadow = calloc(1,
828				 pScrn->displayWidth * pScrn->virtualY *
829				 ((pScrn->bitsPerPixel + 7) >> 3));
830	if (info->fb_shadow == NULL) {
831	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
832                       "Failed to allocate shadow framebuffer\n");
833	    info->r600_shadow_fb = FALSE;
834	} else {
835	    if (!fbScreenInit(pScreen, info->fb_shadow,
836			      pScrn->virtualX, pScrn->virtualY,
837			      pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth,
838			      pScrn->bitsPerPixel))
839		return FALSE;
840	}
841    }
842
843    if (info->r600_shadow_fb == FALSE) {
844	/* Init fb layer */
845	if (!fbScreenInit(pScreen, front_ptr,
846			  pScrn->virtualX, pScrn->virtualY,
847			  pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth,
848			  pScrn->bitsPerPixel))
849	    return FALSE;
850    }
851
852    xf86SetBlackWhitePixels(pScreen);
853
854    if (pScrn->bitsPerPixel > 8) {
855	VisualPtr  visual;
856
857	visual = pScreen->visuals + pScreen->numVisuals;
858	while (--visual >= pScreen->visuals) {
859	    if ((visual->class | DynamicClass) == DirectColor) {
860		visual->offsetRed   = pScrn->offset.red;
861		visual->offsetGreen = pScrn->offset.green;
862		visual->offsetBlue  = pScrn->offset.blue;
863		visual->redMask     = pScrn->mask.red;
864		visual->greenMask   = pScrn->mask.green;
865		visual->blueMask    = pScrn->mask.blue;
866	    }
867	}
868    }
869
870    /* Must be after RGB order fixed */
871    fbPictureInit (pScreen, 0, 0);
872
873#ifdef RENDER
874    if ((s = xf86GetOptValString(info->Options, OPTION_SUBPIXEL_ORDER))) {
875	if (strcmp(s, "RGB") == 0) subPixelOrder = SubPixelHorizontalRGB;
876	else if (strcmp(s, "BGR") == 0) subPixelOrder = SubPixelHorizontalBGR;
877	else if (strcmp(s, "NONE") == 0) subPixelOrder = SubPixelNone;
878	PictureSetSubpixelOrder (pScreen, subPixelOrder);
879    }
880#endif
881
882    pScrn->vtSema = TRUE;
883    /* Backing store setup */
884    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
885		   "Initializing backing store\n");
886    miInitializeBackingStore(pScreen);
887    xf86SetBackingStore(pScreen);
888
889
890    if (info->directRenderingEnabled) {
891	xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n");
892    } else {
893	xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
894		   "Direct rendering disabled\n");
895    }
896
897    if (info->r600_shadow_fb) {
898	xf86DrvMsg(scrnIndex, X_INFO, "Acceleration disabled\n");
899	info->accelOn = FALSE;
900    } else {
901	xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
902		       "Initializing Acceleration\n");
903	if (RADEONAccelInit(pScreen)) {
904	    xf86DrvMsg(scrnIndex, X_INFO, "Acceleration enabled\n");
905	    info->accelOn = TRUE;
906	} else {
907	    xf86DrvMsg(scrnIndex, X_ERROR,
908		       "Acceleration initialization failed\n");
909	    xf86DrvMsg(scrnIndex, X_INFO, "Acceleration disabled\n");
910	    info->accelOn = FALSE;
911	}
912    }
913
914    /* Init DPMS */
915    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
916		   "Initializing DPMS\n");
917    xf86DPMSInit(pScreen, xf86DPMSSet, 0);
918
919    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
920		   "Initializing Cursor\n");
921
922    /* Set Silken Mouse */
923    xf86SetSilkenMouse(pScreen);
924
925    /* Cursor setup */
926    miDCInitialize(pScreen, xf86GetPointerScreenFuncs());
927
928    if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) {
929	if (RADEONCursorInit_KMS(pScreen)) {
930	}
931    }
932
933    /* DGA setup */
934#ifdef XFreeXDGA
935    /* DGA is dangerous on kms as the base and framebuffer location may change:
936     * http://lists.freedesktop.org/archives/xorg-devel/2009-September/002113.html
937     */
938    /* xf86DiDGAInit(pScreen, info->LinearAddr + pScrn->fbOffset); */
939#endif
940    if (info->r600_shadow_fb == FALSE) {
941        /* Init Xv */
942        xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
943                       "Initializing Xv\n");
944        RADEONInitVideo(pScreen);
945    }
946
947    if (info->r600_shadow_fb == TRUE) {
948        if (!shadowSetup(pScreen)) {
949	    xf86DrvMsg(scrnIndex, X_ERROR,
950		       "Shadowfb initialization failed\n");
951            return FALSE;
952        }
953    }
954    pScrn->pScreen = pScreen;
955
956    /* Provide SaveScreen & wrap BlockHandler and CloseScreen */
957    /* Wrap CloseScreen */
958    info->CloseScreen    = pScreen->CloseScreen;
959    pScreen->CloseScreen = RADEONCloseScreen_KMS;
960    pScreen->SaveScreen  = RADEONSaveScreen_KMS;
961    info->BlockHandler = pScreen->BlockHandler;
962    pScreen->BlockHandler = RADEONBlockHandler_KMS;
963
964    if (!AddCallback(&FlushCallback, radeon_flush_callback, pScrn))
965        return FALSE;
966
967    info->CreateScreenResources = pScreen->CreateScreenResources;
968    pScreen->CreateScreenResources = RADEONCreateScreenResources_KMS;
969
970   if (!xf86CrtcScreenInit (pScreen))
971       return FALSE;
972
973   /* Wrap pointer motion to flip touch screen around */
974//    info->PointerMoved = pScrn->PointerMoved;
975//    pScrn->PointerMoved = RADEONPointerMoved;
976
977    if (!drmmode_setup_colormap(pScreen, pScrn))
978	return FALSE;
979
980   /* Note unused options */
981    if (serverGeneration == 1)
982	xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options);
983
984    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
985		   "RADEONScreenInit finished\n");
986
987    info->accel_state->XInited3D = FALSE;
988    info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
989
990    return TRUE;
991}
992
993Bool RADEONEnterVT_KMS(int scrnIndex, int flags)
994{
995    ScrnInfoPtr    pScrn = xf86Screens[scrnIndex];
996    RADEONInfoPtr  info  = RADEONPTR(pScrn);
997    int ret;
998
999    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1000		   "RADEONEnterVT_KMS\n");
1001
1002
1003    ret = drmSetMaster(info->dri->drmFD);
1004    if (ret)
1005	ErrorF("Unable to retrieve master\n");
1006    info->accel_state->XInited3D = FALSE;
1007    info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
1008
1009    pScrn->vtSema = TRUE;
1010
1011    if (!drmmode_set_desired_modes(pScrn, &info->drmmode))
1012	return FALSE;
1013
1014    if (info->adaptor)
1015	RADEONResetVideo(pScrn);
1016
1017    return TRUE;
1018}
1019
1020
1021void RADEONLeaveVT_KMS(int scrnIndex, int flags)
1022{
1023    ScrnInfoPtr    pScrn = xf86Screens[scrnIndex];
1024    RADEONInfoPtr  info  = RADEONPTR(pScrn);
1025
1026    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1027		   "RADEONLeaveVT_KMS\n");
1028
1029    drmDropMaster(info->dri->drmFD);
1030
1031#ifdef HAVE_FREE_SHADOW
1032    xf86RotateFreeShadow(pScrn);
1033#endif
1034
1035    xf86_hide_cursors (pScrn);
1036    info->accel_state->XInited3D = FALSE;
1037    info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
1038
1039    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1040		   "Ok, leaving now...\n");
1041}
1042
1043
1044Bool RADEONSwitchMode_KMS(int scrnIndex, DisplayModePtr mode, int flags)
1045{
1046    ScrnInfoPtr    pScrn       = xf86Screens[scrnIndex];
1047    Bool ret;
1048    ret = xf86SetSingleMode (pScrn, mode, RR_Rotate_0);
1049    return ret;
1050
1051}
1052
1053void RADEONAdjustFrame_KMS(int scrnIndex, int x, int y, int flags)
1054{
1055    ScrnInfoPtr    pScrn       = xf86Screens[scrnIndex];
1056    RADEONInfoPtr  info        = RADEONPTR(pScrn);
1057    drmmode_adjust_frame(pScrn, &info->drmmode, x, y, flags);
1058    return;
1059}
1060
1061static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
1062{
1063    ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
1064    RADEONInfoPtr info = RADEONPTR(pScrn);
1065    xf86CrtcConfigPtr   xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
1066    int cpp = info->CurrentLayout.pixel_bytes;
1067    int screen_size;
1068    int stride = pScrn->displayWidth * cpp;
1069    int total_size_bytes = 0, remain_size_bytes;
1070
1071    if (info->accel_state->exa != NULL) {
1072	xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map already initialized\n");
1073	return FALSE;
1074    }
1075    if (info->r600_shadow_fb == FALSE) {
1076        info->accel_state->exa = exaDriverAlloc();
1077        if (info->accel_state->exa == NULL)
1078	    return FALSE;
1079    }
1080
1081    screen_size = RADEON_ALIGN(pScrn->virtualY, 16) * stride;
1082    {
1083	int cursor_size = 64 * 4 * 64;
1084	int c;
1085
1086	cursor_size = RADEON_ALIGN(cursor_size, RADEON_GPU_PAGE_SIZE);
1087	for (c = 0; c < xf86_config->num_crtc; c++) {
1088	    /* cursor objects */
1089            if (info->cursor_bo[c] == NULL) {
1090                info->cursor_bo[c] = radeon_bo_open(info->bufmgr, 0,
1091                                                    cursor_size, 0,
1092                                                    RADEON_GEM_DOMAIN_VRAM, 0);
1093                if (!info->cursor_bo[c]) {
1094                    return FALSE;
1095                }
1096
1097#if X_BYTE_ORDER == X_BIG_ENDIAN
1098		radeon_bo_set_tiling(info->cursor_bo[c], RADEON_TILING_SWAP_32BIT |
1099				     RADEON_TILING_SURFACE, CURSOR_WIDTH);
1100#endif
1101
1102                if (radeon_bo_map(info->cursor_bo[c], 1)) {
1103                    ErrorF("Failed to map cursor buffer memory\n");
1104                }
1105
1106                drmmode_set_cursor(pScrn, &info->drmmode, c, info->cursor_bo[c]);
1107                total_size_bytes += cursor_size;
1108            }
1109        }
1110    }
1111
1112    screen_size = RADEON_ALIGN(screen_size, RADEON_GPU_PAGE_SIZE);
1113    /* keep area front front buffer - but don't allocate it yet */
1114    total_size_bytes += screen_size;
1115
1116    /* work out from the mm size what the exa / tex sizes need to be */
1117    remain_size_bytes = info->vram_size - total_size_bytes;
1118
1119    info->dri->textureSize = 0;
1120
1121    if (info->front_bo == NULL) {
1122	uint32_t tiling_flags = 0;
1123
1124        info->front_bo = radeon_bo_open(info->bufmgr, 0, screen_size,
1125                                        0, RADEON_GEM_DOMAIN_VRAM, 0);
1126        if (info->r600_shadow_fb == TRUE) {
1127            if (radeon_bo_map(info->front_bo, 1)) {
1128                ErrorF("Failed to map cursor buffer memory\n");
1129            }
1130        }
1131	/* no tiled scanout on r6xx+ yet */
1132        if (info->allowColorTiling) {
1133	    if (info->ChipFamily < CHIP_FAMILY_R600)
1134		tiling_flags |= RADEON_TILING_MACRO;
1135        }
1136#if X_BYTE_ORDER == X_BIG_ENDIAN
1137	switch (cpp) {
1138	case 4:
1139	    tiling_flags |= RADEON_TILING_SWAP_32BIT;
1140	    break;
1141	case 2:
1142	    tiling_flags |= RADEON_TILING_SWAP_16BIT;
1143	    break;
1144	}
1145#endif
1146	if (tiling_flags) {
1147            radeon_bo_set_tiling(info->front_bo,
1148				 tiling_flags | RADEON_TILING_SURFACE, stride);
1149	}
1150    }
1151
1152    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Front buffer size: %dK\n", info->front_bo->size/1024);
1153    radeon_kms_update_vram_limit(pScrn, screen_size);
1154    return TRUE;
1155}
1156
1157void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, int new_fb_size)
1158{
1159    xf86CrtcConfigPtr   xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
1160    RADEONInfoPtr info = RADEONPTR(pScrn);
1161    int remain_size_bytes;
1162    int total_size_bytes;
1163    int c;
1164
1165    for (c = 0; c < xf86_config->num_crtc; c++) {
1166	if (info->cursor_bo[c] != NULL) {
1167	    total_size_bytes += (64 * 4 * 64);
1168	}
1169    }
1170
1171    total_size_bytes += new_fb_size;
1172    remain_size_bytes = info->vram_size - new_fb_size;
1173    remain_size_bytes = (remain_size_bytes / 10) * 9;
1174    radeon_cs_set_limit(info->cs, RADEON_GEM_DOMAIN_VRAM, remain_size_bytes);
1175
1176    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VRAM usage limit set to %dK\n", remain_size_bytes / 1024);
1177}
1178
1179
1180#endif
1181