radeon_macros.h revision 209ff23f 
1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 *                VA Linux Systems Inc., Fremont, California.
4 *
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation on the rights to use, copy, modify, merge,
11 * publish, distribute, sublicense, and/or sell copies of the Software,
12 * and to permit persons to whom the Software is furnished to do so,
13 * subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial
17 * portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
22 * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 */
28
29/*
30 * Authors:
31 *   Kevin E. Martin <martin@xfree86.org>
32 *   Rickard E. Faith <faith@valinux.com>
33 *   Alan Hourihane <alanh@fairlite.demon.co.uk>
34 *
35 * References:
36 *
37 * !!!! FIXME !!!!
38 *   RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
39 *   Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
40 *   1999.
41 *
42 * !!!! FIXME !!!!
43 *   RAGE 128 Software Development Manual (Technical Reference Manual P/N
44 *   SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
45 *
46 */
47
48
49#ifndef _RADEON_MACROS_H_
50#define _RADEON_MACROS_H_
51
52#include "compiler.h"
53
54#if HAVE_BYTESWAP_H
55#include <byteswap.h>
56#elif defined(USE_SYS_ENDIAN_H)
57#include <sys/endian.h>
58#else
59#define	bswap_16(value)  \
60 	((((value) & 0xff) << 8) | ((value) >> 8))
61
62#define	bswap_32(value)	\
63 	(((uint32_t)bswap_16((uint16_t)((value) & 0xffff)) << 16) | \
64 	(uint32_t)bswap_16((uint16_t)((value) >> 16)))
65
66#define	bswap_64(value)	\
67 	(((uint64_t)bswap_32((uint32_t)((value) & 0xffffffff)) \
68 	    << 32) | \
69 	(uint64_t)bswap_32((uint32_t)((value) >> 32)))
70#endif
71
72#if X_BYTE_ORDER == X_BIG_ENDIAN
73#define le32_to_cpu(x) bswap_32(x)
74#define le16_to_cpu(x) bswap_16(x)
75#else
76#define le32_to_cpu(x) (x)
77#define le16_to_cpu(x) (x)
78#endif
79
80#define RADEON_BIOS8(v)  (info->VBIOS[v])
81#define RADEON_BIOS16(v) (info->VBIOS[v] | \
82                          (info->VBIOS[(v) + 1] << 8))
83#define RADEON_BIOS32(v) (info->VBIOS[v] | \
84                          (info->VBIOS[(v) + 1] << 8) | \
85                          (info->VBIOS[(v) + 2] << 16) | \
86                          (info->VBIOS[(v) + 3] << 24))
87
88				/* Memory mapped register access macros */
89#define INREG8(addr)        MMIO_IN8(RADEONMMIO, addr)
90#define INREG16(addr)       MMIO_IN16(RADEONMMIO, addr)
91#define INREG(addr)         MMIO_IN32(RADEONMMIO, addr)
92#define OUTREG8(addr, val)  MMIO_OUT8(RADEONMMIO, addr, val)
93#define OUTREG16(addr, val) MMIO_OUT16(RADEONMMIO, addr, val)
94#define OUTREG(addr, val)   MMIO_OUT32(RADEONMMIO, addr, val)
95
96#define ADDRREG(addr)       ((volatile uint32_t *)(pointer)(RADEONMMIO + (addr)))
97
98
99#define OUTREGP(addr, val, mask)					\
100do {									\
101    uint32_t tmp = INREG(addr);						\
102    tmp &= (mask);							\
103    tmp |= ((val) & ~(mask));						\
104    OUTREG(addr, tmp);							\
105} while (0)
106
107#define INPLL(pScrn, addr) RADEONINPLL(pScrn, addr)
108
109#define OUTPLL(pScrn, addr, val) RADEONOUTPLL(pScrn, addr, val)
110
111#define OUTPLLP(pScrn, addr, val, mask)					\
112do {									\
113    uint32_t tmp_ = INPLL(pScrn, addr);					\
114    tmp_ &= (mask);							\
115    tmp_ |= ((val) & ~(mask));						\
116    OUTPLL(pScrn, addr, tmp_);						\
117} while (0)
118
119#define OUTPAL_START(idx)						\
120do {									\
121    if (IS_AVIVO_VARIANT) {                                             \
122        OUTREG8(AVIVO_DC_LUT_RW_INDEX, (idx));				\
123    } else {                                                            \
124        OUTREG8(RADEON_PALETTE_INDEX, (idx));				\
125    }								        \
126} while (0)
127
128#define OUTPAL_NEXT(r, g, b)						\
129do {									\
130    if (IS_AVIVO_VARIANT) {                                             \
131        OUTREG(AVIVO_DC_LUT_30_COLOR, ((r) << 22) | ((g) << 12) | ((b) << 2));	\
132    } else {                                                               \
133        OUTREG(RADEON_PALETTE_DATA, ((r) << 16) | ((g) << 8) | (b));	\
134    }								        \
135} while (0)
136
137#define OUTPAL_NEXT_uint32_t(v)						\
138do {									\
139    OUTREG(RADEON_PALETTE_DATA, (v & 0x00ffffff));			\
140} while (0)
141
142#define OUTPAL(idx, r, g, b)						\
143do {									\
144    OUTPAL_START((idx));						\
145    OUTPAL_NEXT((r), (g), (b));						\
146} while (0)
147
148#define INPAL_START(idx)						\
149do {									\
150    if (IS_AVIVO_VARIANT) {                                             \
151        OUTREG8(AVIVO_DC_LUT_RW_INDEX, (idx));				\
152    } else {                                                            \
153        OUTREG(RADEON_PALETTE_INDEX, (idx) << 16);			\
154    }								        \
155} while (0)
156
157#define INPAL_NEXT()                                                    \
158do {									\
159    if (IS_AVIVO_VARIANT) {                                             \
160        INREG(AVIVO_DC_LUT_30_COLOR);                                   \
161    } else {                                                            \
162        INREG(RADEON_PALETTE_DATA);                                     \
163    }								        \
164} while (0)
165
166#define PAL_SELECT(idx)							\
167do {									\
168    if (IS_AVIVO_VARIANT) {                                             \
169        if (!idx) {							\
170	    OUTREG(AVIVO_DC_LUT_RW_SELECT, 0);                          \
171        } else {						        \
172	    OUTREG(AVIVO_DC_LUT_RW_SELECT, 1);                          \
173        }								\
174    } else {                                                            \
175        if (!idx) {							\
176	    OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) &		\
177	           (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL);		\
178        } else {							\
179	    OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) |		\
180	           RADEON_DAC2_PALETTE_ACC_CTL);			\
181        }								\
182    }								        \
183} while (0)
184
185#define INMC(pScrn, addr) RADEONINMC(pScrn, addr)
186
187#define OUTMC(pScrn, addr, val) RADEONOUTMC(pScrn, addr, val)
188
189#endif
190