1 Information for Chips and Technologies Users
2 David Bateman ( <mailto:dbateman@club-internet.fr>), Egbert
3 Eich ( <mailto:eich@freedesktop.org>)
4 1st January 2001
5 ____________________________________________________________
6
7 Table of Contents
8
9
10 1. Introduction
11 2. Supported Chips
12 2.1 Basic architecture
13 2.2 WinGine architecture
14 2.3 HiQV Architecture
15
16 3. xorg.conf Options
17 4. Modelines
18 5. Dual Display Channel
19 6. The Full Story on Clock Limitations
20 7. Troubleshooting
21 8. Disclaimer
22 9. Acknowledgement
23 10. Authors
24
25
26 ______________________________________________________________________
27
28 1. Introduction
29
30
31 The Chips and Technologies driver release in X11R7.5 came from XFree86
32 4.4 rc2; this document was originally included in that release and has
33 been updated modestly to reflect differences between X11R7.5 and
34 XFree86 4.4 rc2.
35
36 With the release of XFree86 version 4.0, the Chips and Technologies
37 driver has been extensively rewritten and contains many new features.
38 This driver must be considered work in progress, and those users
39 wanting stability are encouraged to use the older XFree86 3.3.x
40 versions. However this version of the Chips and Technologies driver
41 has many new features and bug fixes that might make users prefer to
42 use this version. These features include
43
44
45 o The long standing black/blue screen problem that some people have
46 had should be fixed.
47
48 o Hardware/Software cursor switching on the fly, that should fix many
49 of the known hardware cursor problems.
50
51 o Gamma correction at all depths and DirectColor visuals for depths
52 of 15 or greater with the HiQV series of chipsets.
53
54 o Supports PseudoColor overlays on 16bpp TrueColor screens for HiQV.
55
56 o Supports YUV colour space conversion with the XVideo extension.
57
58 o 32bpp pixmaps while using a framebuffer in 24bpp packed pixel mode.
59
60 o Heaps more acceleration.
61
62 o 1/4bpp support.
63
64 o Multihead
65
66
67 o Much more...
68
69 This document attempts to discuss the features of this driver, the
70 options useful in configuring it and the known problems. Most of the
71 Chips and Technologies chipsets are supported by this driver to some
72 degree.
73
74
75 2. Supported Chips
76
77
78 The Chips and Technologies chipsets supported by this driver have one
79 of three basic architectures. A basic architecture, the WinGine
80 architecture which is a modification on this basic architecture and a
81 completely new HiQV architecture.
82
83
84 2.1. Basic architecture
85
86
87 ct65520
88 (Max Ram: 1Mb, Max Dclk: 68MHz@5V)
89
90 ct65525
91 This chip is basically identical to the 65530. It has the same
92 ID and is identified as a 65530 when probed. See ct65530 for
93 details.
94
95 ct65530
96 This is a very similar chip to the 65520. However it
97 additionally has the ability for mixed 5V and 3.3V operation and
98 linear addressing of the video memory. (Max Ram: 1Mb, Max Dclk:
99 56MHz@3.3V, 68MHz@5V)
100
101 ct65535
102 This is the first chip of the ct655xx series to support fully
103 programmable clocks. Otherwise it has the the same properties as
104 the 65530.
105
106 ct65540
107 This is the first version of the of the ct655xx that was capable
108 of supporting Hi-Color and True-Color. It also includes a fully
109 programmable dot clock and supports all types of flat panels.
110 (Max Ram: 1Mb, Max Dclk: 56MHz@3.3V, 68MHz@5V)
111
112 ct65545
113 The chip is very similar to the 65540, with the addition of H/W
114 cursor, pop-menu acceleration, BitBLT and support of PCI Buses.
115 PCI version also allow all the BitBLT and H/W cursor registers
116 to be memory mapped 2Mb above the Base Address. (Max Ram: 1Mb,
117 Max Dclk: 56MHz@3.3V,68MHz@5V)
118
119 ct65546
120 This chip is specially manufactured for Toshiba, and so
121 documentation is not widely available. It is believed that this
122 is really just a 65545 with a higher maximum dot-clock of 80MHz.
123 (Max Ram: 1Mb?, Max Dclk: 80MHz?)
124
125 ct65548
126 This chip is similar to the 65545, but it also includes XRAM
127 support and supports the higher dot clocks of the 65546. (Max
128 Ram: 1Mb, Max Dclk: 80MHz)
129
130
131
132 2.2. WinGine architecture
133
134
135 ct64200
136 This chip, also known as the WinGine, is used in video cards for
137 desktop systems. It often uses external DAC's and programmable
138 clock chips to supply additional functionally. None of these are
139 currently supported within the driver itself, so many cards will
140 only have limited support. Linear addressing is not supported
141 for this card in the driver. (Max Ram: 2Mb, Max Dclk: 80MHz)
142
143 ct64300
144 This is a more advanced version of the WinGine chip, with
145 specification very similar to the 6554x series of chips. However
146 there are many differences at a register level. A similar level
147 of acceleration to the 65545 is included for this driver. (Max
148 Ram: 2Mb, Max Dclk: 80MHz)
149
150
151 2.3. HiQV Architecture
152
153
154 ct65550
155 This chip includes many new features, including improved BitBLT
156 support (24bpp colour expansion, wider maximum pitch, etc),
157 Multimedia unit (video capture, zoom video port, etc) and 24bpp
158 uncompressed true colour (i.e 32bpp mode). Also memory mapped
159 I/O is possible on all bus configurations. (Max Ram: 2Mb, Max
160 Dclk: 80MHz@3.3V,100MHz@5V)
161
162 ct65554
163 This chip is similar to the 65550 but has a 64bit memory bus as
164 opposed to a 32bit bus. It also has higher limits on the maximum
165 memory and pixel clocks (Max Ram: 4Mb, Max Dclk: 100MHz@3.3V)
166
167 ct65555
168 Similar to the 65554 but has yet higher maximum memory and pixel
169 clocks. It also includes a new DSTN dithering scheme that
170 improves the performance of DSTN screens. (Max Ram: 4Mb, Max
171 Dclk: 110MHz@3.3V)
172
173 ct68554
174 Similar to the 65555 but also incorporates "PanelLink" drivers.
175 This serial link allows an LCD screens to be located up to 100m
176 from the video processor. Expect to see this chip soon in LCD
177 desktop machines (Max Ram: 4Mb, Max Dclk: 110MHz@3.3V)
178
179 ct69000
180 Similar to the 65555 but incorporates 2Mbytes of SGRAM on chip.
181 It is the first Chips and Technologies chipset where all of the
182 registers are accessible through MMIO, rather than just the
183 BitBlt registers. (Max Ram: 2Mb Only, Max Dclk: 130MHz@3.3V)
184
185 ct69030
186 Similar to the 69000 but incorporates 4Mbytes of SGRAM on chip
187 and has faster memory and pixel clock limits. Also includes a
188 second display channel so that the CRT can display independently
189 of the LCD. (Max Ram: 4Mb Only, Max Dclk: 170MHz@3.3V)
190
191
192
193 3. xorg.conf Options
194
195
196 The following options are of particular interest to the Chips and
197 Technologies driver. It should be noted that the options are case
198 insensitive, and that white space and "_" characters are ignored.
199 There are therefore a wide variety of possible forms for all options.
200 The forms given below are the preferred forms.
201
202 Options related to drivers can be present in the Screen, Device and
203 Monitor sections and the Display subsections. The order of precedence
204 is Display, Screen, Monitor, Device.
205
206
207 Option
208 This option will disable the use of any accelerated functions.
209 This is likely to help with some problems related to DRAM
210 timing, high dot clocks, and bugs in accelerated functions, at
211 the cost of performance (which will still be reasonable on
212 VLB/PCI).
213
214 VideoRam 1024 (or another value)
215 This option will override the detected amount of video memory,
216 and pretend the given amount of memory is present on the card.
217
218 Option
219 By default linear addressing is used on all chips where it can
220 be set up automatically. The exception is for depths of 1 or
221 4bpp where linear addressing is turned off by default. It is
222 possible to turn the linear addressing off with this option.
223 Note that H/W acceleration is only supported with linear
224 addressing.
225
226 Option
227 When the chipset is capable of linear addressing and it has been
228 turned off by default, this option can be used to turn it back
229 on. This is useful for the 65530 chipset where the base address
230 of the linear framebuffer must be supplied by the user, or at
231 depths 1 and 4bpp. Note that linear addressing at 1 and 4bpp is
232 not guaranteed to work correctly.
233
234 MemBase 0x03b00000 (or a different address)
235 This sets the physical memory base address of the linear
236 framebuffer. Typically this is probed correctly, but if you
237 believe it to be mis-probed, this option might help. Also for
238 non PCI machines specifying this force the linear base address
239 to be this value, reprogramming the video processor to suit.
240 Note that for the 65530 this is required as the base address
241 can't be correctly probed.
242
243 Option
244 For chipsets that support hardware cursors, this option enforces
245 their use, even for cases that are known to cause problems on
246 some machines. Note that it is overridden by the "SWcursor"
247 option. Hardware cursors effectively speeds all graphics
248 operations as the job of ensuring that the cursor remains on top
249 is now given to the hardware. It also reduces the effect of
250 cursor flashing during graphics operations.
251
252 Option
253 This disables use of the hardware cursor provided by the chip.
254 Try this if the cursor seems to have problems.
255
256 Option
257 The server is unable to differentiate between SS STN and TFT
258 displays. This forces it to identify the display as a SS STN
259 rather than a TFT.
260
261 Option
262 The flat panel timings are related to the panel size and not the
263 size of the mode specified in xorg.conf. For this reason the
264 default behaviour of the server is to use the panel timings
265 already installed in the chip. The user can force the panel
266 timings to be recalculated from the modeline with this option.
267 However the panel size will still be probed.
268
269 Option
270 For some machines the LCD panel size is incorrectly probed from
271 the registers. This option forces the LCD panel size to be
272 overridden by the modeline display sizes. This will prevent the
273 use of a mode that is a different size than the panel. Before
274 using this check that the server reports an incorrect panel
275 size. This option can be used in conjunction with the option
276 "UseModeline" to program all the panel timings using the
277 modeline values.
278
279 Option
280 When the size of the mode used is less than the panel size, the
281 default behaviour of the server is to stretch the mode in an
282 attempt to fill the screen. A "letterbox" effect with no
283 stretching can be achieved using this option.
284
285 Option
286 When the size of the mode used is less than the panel size, the
287 default behaviour of the server is to align the left hand edge
288 of the display with the left hand edge of the screen. Using this
289 option the mode can be centered in the screen. This option is
290 reported to have problems with some machines at 16/24/32bpp, the
291 effect of which is that the right-hand edge of the mode will be
292 pushed off the screen.
293
294 Option
295 For the chips either using the WinGine or basic architectures,
296 the chips generates a number of fixed clocks internally. With
297 the chips 65535 and later or the 64300, the default is to use
298 the programmable clock for all clocks. It is possible to use the
299 fixed clocks supported by the chip instead by using this option.
300 Typically this will give you some or all of the clocks 25.175,
301 28.322, 31.000 and 36.000MHz. The current programmable clock
302 will be given as the last clock in the list. On a cold-booted
303 system this might be the appropriate value to use at the text
304 console (see the "TextClockFreq" option), as many flat panels
305 will need a dot clock different than the default to synchronise.
306 The programmable clock makes this option obsolete and so it's
307 use isn't recommended. It is completely ignored for HiQV
308 chipsets.
309
310 TextClockFreq 25.175
311 Except for the HiQV chipsets, it is impossible for the server to
312 read the value of the currently used frequency for the text
313 console when using programmable clocks. Therefore the server
314 uses a default value of 25.175MHz as the text console clock. For
315 some LCDs, in particular DSTN screens, this clock will be wrong.
316 This allows the user to select a different clock for the server
317 to use when returning to the text console.
318
319 Option
320 Option "FPClock16" "65.0MHz" Option "FPClock24" "65.0MHz" Option
321 "FPClock32" "65.0MHz"" In general the LCD panel clock should be
322 set independently of the modelines supplied. Normally the chips
323 BIOS set the flat panel clock correctly and so the default
324 behaviour with HiQV chipset is to leave the flat panel clock
325 alone, or force it to be 90% of the maximum allowable clock if
326 the current panel clock exceeds the dotclock limitation due to a
327 depth change. This option allows the user to force the server
328 the reprogram the flat panel clock independently of the modeline
329 with HiQV chipset. The four options are for 8bpp or less, 16, 24
330 or 32bpp LCD panel clocks, where the options above set the
331 clocks to 65MHz.
332
333 Option
334 Option "FPClkIndx" "1"" The HiQV series of chips have three
335 programmable clocks. The first two are usually loaded with
336 25.175 and 28.322MHz for VGA backward compatibility, and the
337 third is used as a fully programmable clock. On at least one
338 system (the Inside 686 LCD/S single board computer) the third
339 clock is unusable. These options can be used to force a
340 particular clock index to be used
341
342 Option
343 This has a different effect depending on the hardware on which
344 it is used. For the 6554x machines MMIO is only used to talk to
345 the BitBLT engine and is only usable with PCI buses. It is
346 enabled by default for 65545 machines since the blitter can not
347 be used otherwise. The HiQV series of chipsets must use MMIO
348 with their BitBLT engines, and so this is enabled by default.
349
350 Option
351 The 690xx chipsets can use MMIO for all communications with the
352 video processor. So using this option on a 690xx chipset forces
353 them to use MMIO for all communications. This only makes sense
354 when the 690xx is on a PCI bus so that normal PIO can be
355 disabled.
356
357 Option
358 This option sets the centering and stretching to the BIOS
359 default values. This can fix suspend/resume problems on some
360 machines. It overrides the options "LcdCenter" and "NoStretch".
361
362 Option For 24bpp on TFT screens, the server assumes that
363 a 24bit bus is being used. This can result in a
364 reddish tint to 24bpp mode. This option, selects
365 an 18 bit TFT bus. For other depths this option
366 has no effect.
367
368 Chipset It is possible that the chip could be
369 misidentified, particular due to interactions
370 with other drivers in the server. It is possible
371 to force the server to identify a particular chip
372 with this option.
373
374 Option Composite sync on green. Possibly useful if you
375 wish to use an old workstation monitor. The HiQV
376 internal RAMDAC's supports this mode of
377 operation, but whether a particular machine does
378 depends on the manufacturer.
379
380 DacSpeed 80.000 The server will limit the maximum dotclock to a
381 value as specified by the manufacturer. This
382 might make certain modes impossible to obtain
383 with a reasonable refresh rate. Using this option
384 the user can override the maximum dot-clock and
385 specify any value they prefer. Use caution with
386 this option, as driving the video processor
387 beyond its specifications might cause damage.
388
389 Option Option "SetMClk" "38000kHz"" This option sets the
390 internal memory clock (MCLK) registers of HiQV
391 chipsets to 38MHz or some other value. Use
392 caution as excess heat generated by the video
393 processor if its specifications are exceeded
394 might cause damage. However careful use of this
395 option might boost performance. This option might
396 also be used to reduce the speed of the memory
397 clock to preserve power in modes that don't need
398 the full speed of the memory to work correctly.
399 This option might also be needed to reduce the
400 speed of the memory clock with the "Overlay"
401 option.
402
403 Option By default it is assumed that there are 6
404 significant bits in the RGB representation of the
405 colours in 4bpp and above. If the colours seem
406 darker than they should be, perhaps your ramdac
407 is has 8 significant bits. This option forces the
408 server to assume that there are 8 significant
409 bits.
410
411 Option This is a debugging option and general users have
412 no need of it. Using this option, when the
413 virtual desktop is scrolled away from the zero
414 position, the pixmap cache becomes visible. This
415 is useful to see that pixmaps, tiles, etc have
416 been properly cached.
417
418 Option This option is only useful when acceleration
419 can't be used and linear addressing can be used.
420 With this option all of the graphics are rendered
421 into a copy of the framebuffer that is keep in
422 the main memory of the computer, and the screen
423 is updated from this copy. In this way the
424 expensive operation of reading back to contents
425 of the screen is never performed and the
426 performance is improved. Because the rendering is
427 all done into a virtual framebuffer acceleration
428 can not be used.
429
430 Option The new TMED DSTN dithering scheme available on
431 recent HiQV chipsets gives improved performance.
432 However, some machines appear to have this
433 feature incorrectly setup. If you have snow on
434 your DSTN LCD, try using this option. This option
435 is only relevant for chipsets more recent than
436 the ct65555 and only when used with a DSTN LCD.
437
438 Option The HiQV chipsets contain a multimedia engine
439 that allow a 16bpp window to be overlaid on the
440 screen. This driver uses this capability to
441 include a 16bpp framebuffer on top of an 8bpp
442 framebuffer. In this way PseudoColor and
443 TrueColor visuals can be used on the same screen.
444 XFree86 believes that the 8bpp framebuffer is
445 overlaid on the 16bpp framebuffer. Therefore to
446 use this option the server must be started in
447 either 15 or 16bpp depth. Also the maximum size
448 of the desktop with this option is 1024x1024, as
449 this is the largest window that the HiQV
450 multimedia engine can display. Note that this
451 option using the multimedia engine to its limit,
452 and some manufacturers have set a default memory
453 clock that will cause pixel errors with this
454 option. If you get pixel error with this option
455 try using the "SetMClk" option to slow the memory
456 clock. It should also be noted that the XVideo
457 extension uses the same capabilities of the HiQV
458 chipsets as the Overlays. So using this option
459 disables the XVideo extension.
460
461
462 Option Normally the colour transparency key for the
463 overlay is the 8bpp lookup table entry 255. This
464 might cause troubles with some applications, and
465 so this option allows the colour transparency key
466 to be set to some other value. Legal values are 2
467 to 255 inclusive.
468
469 Option This sets the default pixel value for the YUV
470 video overlay key. Legal values for this key are
471 depth dependent. That is from 0 to 255 for 8bit
472 depth, 0 to 32,767 for 15bit depth, etc. This
473 option might be used if the default video overlay
474 key causes problems.
475
476 Option The 69030 chipset has independent display
477 channels, that can be configured to support
478 independent refresh rates on the flat panel and
479 on the CRT. The default behaviour is to have both
480 the flat panel and the CRT use the same display
481 channel and thus the same refresh rate. This
482 option forces the two display channels to be
483 used, giving independent refresh rates.
484
485 Option The ct69030 supports dual-head display. By
486 default the two display share equally the
487 available memory. This option forces the second
488 display to take a particular amount of memory.
489 Please read the section below about dual-head
490 display.
491
492 Option Option "XaaNoSolidFillRect", Option "XaaNoSolid-
493 HorVertLine", Option "XaaNoMono8x8PatternFill-
494 Rect", Option "XaaNoColor8x8PatternFillRect",
495 Option "XaaNoCPUToScreenColorExpandFill", Option
496 "XaaNoScreenToScreenColorExpandFill", Option
497 "XaaNoImageWriteRect", Option "XaaNoImageRead-
498 Rect", Option "XaaNoPixmapCache", Option
499 "XaaNoOffscreenPixmaps" " These option
500 individually disable the features of the XAA
501 acceleration code that the Chips and Technologies
502 driver uses. If you have a problem with the
503 acceleration and these options will allow you to
504 isolation the problem. This information will be
505 invaluable in debugging any problems.
506
507
508 4. Modelines
509
510
511 When constructing a modeline for use with the Chips and Technologies
512 driver you'll needed to considered several points
513
514
515 * Virtual Screen Size
516 It is the virtual screen size that determines the amount of
517 memory used by a mode. So if you have a virtual screen size set
518 to 1024x768 using a 800x600 at 8bpp, you use 768kB for the mode.
519 Further to this some of the XAA acceleration requires that the
520 display pitch is a multiple of 64 pixels. So the driver will
521 attempt to round-up the virtual X dimension to a multiple of 64,
522 but leave the virtual resolution untouched. This might further
523 reduce the available memory.
524
525 * 16/24/32 Bits Per Pixel
526 Hi-Color and True-Color modes are implemented in the server. The
527 clocks in the 6554x series of chips are internally divided by 2
528 for 16bpp and 3 for 24bpp, allowing one modeline to be used at
529 all depths. The effect of this is that the maximum dot clock
530 visible to the user is a half or a third of the value at 8bpp.
531 The HiQV series of chips doesn't need to use additional clock
532 cycles to display higher depths, and so the same modeline can be
533 used at all depths, without needing to divide the clocks. Also
534 16/24/32 bpp modes will need 2 , 3 or 4 times respectively more
535 video ram.
536
537 * Frame Acceleration
538 Many DSTN screens use frame acceleration to improve the
539 performance of the screen. This can be done by using an external
540 frame buffer, or incorporating the framebuffer at the top of
541 video ram depending on the particular implementation. The
542 Xserver assumes that the framebuffer, if used, will be at the
543 top of video ram. The amount of ram required for the
544 framebuffer will vary depending on the size of the screen, and
545 will reduce the amount of video ram available to the modes.
546 Typical values for the size of the framebuffer will be 61440
547 bytes (640x480 panel), 96000 bytes (800x600 panel) and 157287
548 bytes (1024x768 panel).
549
550 * H/W Acceleration
551 The H/W cursor will need 1kB for the 6554x and 4kb for the
552 65550. On the 64300 chips the H/W cursor is stored in registers
553 and so no allowance is needed for the H/W cursor. In addition to
554 this many graphics operations are speeded up using a "pixmap
555 cache". Leaving too little memory available for the cache will
556 only have a detrimental effect on the graphics performance.
557
558 * PseudoColor Overlay
559 If you use the "overlay" option, then there are actually two
560 framebuffers in the video memory. An 8bpp one and a 16bpp one.
561 The total memory requirements in this mode of operation is
562 therefore similar to a 24bpp mode. The overlay consumes memory
563 bandwidth, so that the maximum dotclock will be similar to a
564 24bpp mode.
565
566 * XVideo extension*
567 Like the overlays, the Xvideo extension uses a part of the video
568 memory for a second framebuffer. In this case enough memory
569 needs to be left for the largest unscaled video window that will
570 be displayed.
571
572 * VESA like modes
573 We recommend that you try and pick a mode that is similar to a
574 standard VESA mode. If you don't a suspend/resume or LCD/CRT
575 switch might mess up the screen. This is a problem with the
576 video BIOS not knowing about all the funny modes that might be
577 selected.
578
579 * Dot Clock
580 For LCD screens, the lowest clock that gives acceptable contrast
581 and flicker is usually the best one. This also gives more memory
582 bandwidth for use in the drawing operations. Some users prefer
583 to use clocks that are defined by their BIOS. This has the
584 advantage that the BIOS will probably restore the clock they
585 specified after a suspend/resume or LCD/CRT switch. For a
586 complete discussion on the dot clock limitations, see the next
587 section.
588
589 * Dual-head display
590 Dual-head display has two effects on the modelines. Firstly, the
591 memory requirements of both heads must fit in the available
592 memory. Secondly, the memory bandwidth of the video processor is
593 shared between the two heads. Hence the maximum dot-clock might
594 need to be limited.
595
596 The driver is capable of driving both a CRT and a flat panel display.
597 In fact the timing for the flat panel are dependent on the
598 specification of the panel itself and are independent of the
599 particular mode chosen. For this reason it is recommended to use one
600 of the programs that automatically generate xorg.conf files, such as
601 "xorgconfig".
602
603 However there are many older machines, particularly those with 800x600
604 screen or larger, that need to reprogram the panel timings. The reason
605 for this is that the manufacturer has used the panel timings to get a
606 standard EGA mode to work on flat panel, and these same timings don't
607 work for an SVGA mode. For these machines the "UseModeline" and/or
608 possibly the "FixPanelSize" option might be needed. Some machines that
609 are known to need these options include.
610
611
612
613 Modeline "640x480@8bpp" 25.175 640 672 728 816 480 489 501 526
614 Modeline "640x480@16bpp" 25.175 640 672 728 816 480 489 501 526
615 Options: "UseModeline"
616 Tested on a Prostar 8200, (640x480, 65548, 1Mbyte)
617
618
619
620 Modeline "800x600@8bpp" 28.322 800 808 848 936 600 600 604 628
621 Options: "FixPanelSize", "UseModeline"
622 Tested on a HP OmniBook 5000CTS (800x600 TFT, 65548, 1Mbyte)
623
624
625
626 Modeline "800x600@8bpp" 30.150 800 896 960 1056 600 600 604 628
627 Options: "FixPanelSize", "UseModeline"
628 Tested on a Zeos Meridan 850c (800x600 DSTN, 65545, 1Mbyte)
629
630
631
632 The IBM PC110 works best with a 15MHz clock (Thanks to Alan Cox):
633
634
635 Modeline "640x480" 15.00 640 672 728 816 480 489 496 526
636 Options: "TextClockFreq" "15.00"
637 IBM PC110 (65535, Citizen L6481L-FF DSTN)
638
639
640
641 The NEC Versa 4080 just needs the "FixPanelSize" option. To the best
642 of my knowledge no machine with a HiQV needs the "UseModeline" or
643 "FixPanelSize" options.
644
645
646 5. Dual Display Channel
647
648
649 XFree86 releases later than 4.1.0 and X.Org releases later than 6.7.0
650 support dual-channel display on the ct69030. This support can be used
651 to give a single display image on two screen with different refresh
652 rates, or entirely different images on the two displays.
653
654 Dual refresh rate display can be selected with the "DualRefresh"
655 option described above. However to use the dual-head support is
656 slightly more complex. Firstly, the ct69030 chipset must be installed
657 on a PCI bus. This is a driver limitation that might be relaxed in the
658 future. In addition the device, screen and layout sections of the
659 "xorg.conf" must be correctly configured. A sample of an incomplete
660 "xorg.conf" is given below
661
662
663
664 Section "Device"
665 Identifier "Chips and Technologies - Pipe A"
666 Driver "chips"
667 BusID "PCI:0:20:0"
668 Screen 0
669 EndSection
670
671 Section "Device"
672 Identifier "Chips and Technologies - Pipe B"
673 Driver "chips"
674 BusID "PCI:0:20:0"
675 Screen 1
676 EndSection
677
678 Section "Screen"
679 Identifier "Screen 0"
680 Device "Chips and Technologies - Pipe A"
681 Monitor "generic LCD"
682
683 SubSection "Display"
684 Depth 16
685 Modes "1024x768"
686 EndSubsection
687 EndSection
688
689 Section "Screen"
690 Identifier "Screen 1"
691 Device "Chips and Technologies - Pipe B"
692 Monitor "generic CRT"
693
694 SubSection "Display"
695 Depth 16
696 Modes "1024x768"
697 EndSubsection
698 EndSection
699
700 Section "ServerLayout"
701 Identifier "Main Layout"
702 Screen "Screen 0"
703 Screen "Screen 1" RightOf "Screen 0"
704 InputDevice "Mouse1" "CorePointer"
705 InputDevice "Keyboard1" "CoreKeyboard"
706 EndSection
707
708
709
710 The device section must include the PCI BusID. This can be found from
711 the log file of a working single-head installation. For instance, the
712 line
713
714
715
716 (--) PCI:*(0:20:0) C&T 69030 rev 97, Mem @ 0xed000000/24
717
718
719
720 appears for the case above. Additionally, the "Screen" option must
721 appear in the device section. It should be noted that if a flat panel
722 is used, this it must be allocated to "Screen 0".
723
724 The server can then be started with the "+xinerama" option as follows
725
726
727
728 startx -- +xinerama
729
730
731
732 For more information, read the Xinerama documentation.
733
734 It should be noted that the dual channel display options of the 69030
735 require the use of additional memory bandwidth, as each display
736 channel independently accesses the video memory. For this reason, the
737 maximum colour depth and resolution that can be supported in a dual
738 channel mode will be reduced compared to a single display channel
739 mode. However, as the driver does not prevent you from using a mode
740 that will exceed the memory bandwidth of the 69030, but a warning like
741
742
743
744 (WW) Memory bandwidth requirements exceeded by dual-channel
745 (WW) mode. Display might be corrupted!!!
746
747
748
749 If you see such display corruption, and you have this warning, your
750 choices are to reduce the refresh rate, colour depth or resolution, or
751 increase the speed of the memory clock with the the "SetMClk" option
752 described above. Note that increasing the memory clock also has its
753 own problems as described above.
754
755
756 6. The Full Story on Clock Limitations
757
758
759 There has been much confusion about exactly what the clock limitations
760 of the Chips and Technologies chipsets are. Hence I hope that this
761 section will clear up the misunderstandings.
762
763 In general there are two factors determining the maximum dotclock.
764 There is the limit of the maximum dotclock the video processor can
765 handle, and there is another limitation of the available memory
766 bandwidth. The memory bandwidth is determined by the clock used for
767 the video memory. For chipsets incapable of colour depths greater
768 that 8bpp like the 65535, the dotclock limit is solely determined by
769 the highest dotclock the video processor is capable of handling. So
770 this limit will be either 56MHz or 68MHz for the 655xx chipsets,
771 depending on what voltage they are driven with, or 80MHz for the 64200
772 WinGine machines.
773
774 The 6554x and 64300 WinGine chipsets are capable of colour depths of
775 16 or 24bpp. However there is no reliable way of probing the memory
776 clock used in these chipsets, and so a conservative limit must be
777 taken for the dotclock limit. In this case the driver divides the
778 video processors dotclock limitation by the number of bytes per pixel,
779 so that the limitations for the various colour depths are
780
781
782 8bpp 16bpp 24bpp
783 64300 85 42.5 28.33
784 65540/65545 3.3v 56 28 18.67
785 65540/65545 5v 68 34 22.67
786 65546/65548 80 40 26.67
787
788
789
790 For a CRT or TFT screen these limitations are conservative and the
791 user might safely override them with the "DacSpeed" option to some
792 extent. However these numbers take no account of the extra bandwidth
793 needed for DSTN screens.
794
795 For the HiQV series of chips, the memory clock can be successfully
796 probed. Hence you will see a line like
797
798
799 (--) CHIPS(0): Probed memory clock of 40.090 MHz
800
801
802
803 in your startx log file. Note that many chips are capable of higher
804 memory clocks than actually set by BIOS. You can use the "SetMClk"
805 option in your xorg.conf file to get a higher MClk. However some video
806 ram, particularly EDO, might not be fast enough to handle this,
807 resulting in drawing errors on the screen. The formula to determine
808 the maximum usable dotclock on the HiQV series of chips is
809
810
811 Max dotclock = min(MaxDClk, 0.70 * 8 * MemoryClk / (BytesPerPixel +
812 (isDSTN == TRUE ? 1 : 0)))
813
814
815
816 if you chips is a 69030 or 69000 or
817
818
819 Max dotclock = min(MaxDClk, 0.70 * 4 * MemoryClk / (BytesPerPixel +
820 (isDSTN == TRUE ? 1 : 0)))
821
822
823
824 otherwise. This effectively means that there are two limits on the
825 dotclock. One the overall maximum, and another due to the available
826 memory bandwidth of the chip. The 69030 and 69000 have a 64bit memory
827 bus and thus transfer 8 bytes every clock thus (hence the 8), while
828 the other HiQV chipsets are 32bit and transfer 4 bytes per clock cycle
829 (hence the 4). However, after accounting for the RAS/CAS signaling
830 only about 70% of the bandwidth is available. The whole thing is
831 divided by the bytes per pixel, plus an extra byte if you are using a
832 DSTN. The extra byte with DSTN screens is used for the frame
833 buffering/acceleration in these screens. So for the various Chips and
834 Technologies chips the maximum specifications are
835
836
837
838 Max DClk MHz Max Mem Clk MHz
839 65550 rev A 3.3v 80 38
840 65550 rev A 5v 110 38
841 65550 rev B 95 50
842 65554 94.5 55
843 65555 110 55
844 68554 110 55
845 69000 135 83
846 69030 170 100
847
848
849
850 Note that all of the chips except the 65550 rev A are 3.3v only. Which
851 is the reason for the drop in the dot clock. Now the maximum memory
852 clock is just the maximum supported by the video processor, not the
853 maximum supported by the video memory. So the value actually used for
854 the memory clock might be significantly less than this maximum value.
855 But assuming your memory clock is programmed to these maximum values
856 the various maximum dot clocks for the chips are
857
858
859 ------CRT/TFT------- --------DSTN--------
860 8bpp 16bpp 24bpp 8bpp 16bpp 24bpp
861 65550 rev A 3.3v 80 53.2 35.47 53.2 35.47 26.6
862 65550 rev A 5v 106.2 53.2 35.47 53.2 35.47 26.6
863 65550 rev B 95 70 46.67 70 46.67 35.0
864 65554 94.5 77 51.33 77 51.33 38.5
865 65555 110 77 51.33 77 51.33 38.5
866 68554 110 77 51.33 77 51.33 38.5
867 69000 135 135 135 135 135 116.2
868 69030 170 170 170 170 170 140
869
870
871
872 If you exceed the maximum set by the memory clock, you'll get
873 corruption on the screen during graphics operations, as you will be
874 starving the HW BitBlt engine of clock cycles. If you are driving the
875 video memory too fast (too high a MemClk) you'll get pixel corruption
876 as the data actually written to the video memory is corrupted by
877 driving the memory too fast. You can probably get away with exceeding
878 the Max DClk at 8bpp on TFT's or CRT's by up to 10% or so without
879 problems, it will just generate more heat, since the 8bpp clocks
880 aren't limited by the available memory bandwidth.
881
882 If you find you truly can't achieve the mode you are after with the
883 default clock limitations, look at the options "DacSpeed" and
884 "SetMClk". Using these should give you all the capabilities you'll
885 need in the server to get a particular mode to work. However use
886 caution with these options, because there is no guarantee that driving
887 the video processor beyond it capabilities won't cause damage.
888
889
890 7. Troubleshooting
891
892
893
894 The cursor appears as a white box, after switching modes
895 There is a known bug in the H/W cursor, that sometimes causes
896 the cursor to be redrawn as a white box, when the mode is
897 changed. This can be fixed by moving the cursor to a different
898 region, switching to the console and back again, or if it is too
899 annoying the H/W cursor can be disabled by removing the
900 "HWcursor" option.
901
902 The cursor hot-spot isn't at the same point as the cursor
903 With modes on the 6555x machines that are stretched to fill the
904 flat panel, the H/W cursor is not correspondingly stretched.
905 This is a small and long-standing bug in the current server. You
906 can avoid this by either using the "NoStretch" option or
907 removing the HWcursor" option.
908
909 The lower part of the screen is corrupted
910 Many DSTN screens use the top of video ram to implement a frame
911 accelerator. This reduces the amount of video ram available to
912 the modes. The server doesn't prevent the user from specifying a
913 mode that will use this memory, it prints a warning on the
914 console. The effect of this problem will be that the lower part
915 of the screen will reside in the same memory as the frame
916 accelerator and will therefore be corrupt. Try reducing the
917 amount of memory consumed by the mode.
918
919 There is a video signal, but the screen doesn't sync.
920 You are using a mode that your screen cannot handle. If it is a
921 non-standard mode, maybe you need to tweak the timings a bit. If
922 it is a standard mode and frequency that your screen should be
923 able to handle, try to find different timings for a similar mode
924 and frequency combination. For LCD modes, it is possible that
925 your LCD panel requires different panel timings at the text
926 console than with a graphics mode. In this case you will need
927 the "UseModeline" and perhaps also the "FixPanelSize" options to
928 reprogram the LCD panel timings to sensible values.
929
930 `Wavy' screen.
931 Horizontal waving or jittering of the whole screen, continuously
932 (independent from drawing operations). You are probably using a
933 dot clock that is too high (or too low); it is also possible
934 that there is interference with a close MCLK. Try a lower dot
935 clock. For CRT's you can also try to tweak the mode timings;
936 try increasing the second horizontal value somewhat.
937
938 Crash or hang after start-up (probably with a black screen).
939 Try the "NoAccel" or one of the XAA acceleration options
940 discussed above. Check that the BIOS settings are OK; in
941 particular, disable caching of 0xa0000-0xaffff. Disabling hidden
942 DRAM refresh may also help.
943
944 Hang as the first text is appearing on the screen on SVR4
945 machines.
946 This problem has been reported under UnixWare 1.x, but not
947 tracked down. It doesn't occur under UnixWare 2.x and only
948 occurs on the HiQV series of chips. It might affect some other
949 SVR4 operating systems as well. The workaround is to turn off
950 the use of CPU to screen acceleration with the
951 "XaaNoCPUToScreenColorExapndFill" option.
952
953 Crash, hang, or trash on the screen after a graphics operation.
954 This may be related to a bug in one of the accelerated
955 functions, or a problem with the BitBLT engine. Try the
956 "NoAccel" or one of the XAA acceleration options discussed
957 above. Also check the BIOS settings. It is also possible that
958 with a high dot clock and depth on a large screen there is very
959 little bandwidth left for using the BitBLT engine. Try reducing
960 the clock.
961
962 Chipset is not detected.
963 Try forcing the chipset to a type that is most similar to what
964 you have.
965
966 The screen is blank when starting X
967 One possible cause of this problem with older linux kernels is
968 that the "APM_DISPLAY_BLANK" option didn't work correct. Either
969 upgrade your kernel or rebuild it with the "APM_DISPLAY_BLANK"
970 option disabled. If the problem remains, or you aren't using
971 linux, a CRT/LCD or switch to and from the virtual console will
972 often fix it.
973
974 Textmode is not properly restored
975 This has been reported on some configurations. Many laptops use
976 the programmable clock of the 6554x chips at the console. It is
977 not always possible to find out the setting that is used for
978 this clock if BIOS has written the MClk after the VClk. Hence
979 the server assumes a 25.175MHz clock at the console. This is
980 correct for most modes, but can cause some problems. Usually
981 this is fixed by switching between the LCD and CRT.
982 Alternatively the user can use the "TextClockFreq" option
983 described above to select a different clock for the text
984 console. Another possible cause of this problem is if linux
985 kernels are compiled with the "APM_DISPLAY_BLANK" option. As
986 mentioned before, try disabling this option.
987
988 I can't display 640x480 on my 800x600 LCD
989 The problem here is that the flat panel needs timings that are
990 related to the panel size, and not the mode size. There is no
991 facility in the current Xservers to specify these values, and so
992 the server attempts to read the panel size from the chip. If the
993 user has used the "UseModeline" or "FixPanelSize" options the
994 panel timings are derived from the mode, which can be different
995 than the panel size. Try deleting these options from xorg.conf
996 or using an LCD/CRT switch.
997
998 I can't get a 320x240 mode to occupy the whole 640x480 LCD
999 There is a bug in the 6554x's H/W cursor for modes that are
1000 doubled vertically. The lower half of the screen is not
1001 accessible. The servers solution to this problem is not to do
1002 doubling vertically. Which results in the 320x240 mode only
1003 expanded to 640x360. If this is a problem, a work around is to
1004 remove the "HWcursor" option. The server will then allow the
1005 mode to occupy the whole 640x480 LCD.
1006
1007 After a suspend/resume my screen is messed up
1008 During a suspend/resume, the BIOS controls what is read and
1009 written back to the registers. If the screen is using a mode
1010 that BIOS doesn't know about, then there is no guarantee that it
1011 will be resumed correctly. For this reason a mode that is as
1012 close to VESA like as possible should be selected. It is also
1013 possible that the VGA palette can be affected by a
1014 suspend/resume. Using an 8bpp, the colour will then be
1015 displayed incorrectly. This shouldn't affect higher depths, and
1016 is fixable with a switch to the virtual console and back.
1017
1018 The right hand edge of the mode isn't visible on the LCD
1019 This is usually due to a problem with the "LcdCenter" option. If
1020 this option is removed form xorg.conf, then the problem might go
1021 away. Alternatively the manufacturer could have incorrectly
1022 programmed the panel size in the EGA console mode. The
1023 "FixPanelSize" can be used to force the modeline values into the
1024 panel size registers. Two machines that are known to have this
1025 problem are the "HP OmniBook 5000" and the "NEC Versa 4080".
1026
1027 My TFT screen has a reddish tint in 24bpp mode
1028 For 6554x chipsets the server assumes that the TFT bus width is
1029 24bits. If this is not true then the screen will appear to have
1030 a reddish tint. This can be fixed by using the "18BitBus"
1031 option. Note that the reverse is also true. If the "18BitBus" is
1032 used and the TFT bus width is 24bpp, then the screen will appear
1033 reddish. Note that this option only has an effect on TFT
1034 screens.
1035
1036 SuperProbe won't work with my chipset
1037 At least one non-PCI bus system with a HiQV chipset has been
1038 found to require the "-no_bios" option for SuperProbe to
1039 correctly detect the chipset with the factory default BIOS
1040 settings. The server itself can correctly detect the chip in the
1041 same situation.
1042
1043 My 690xx machine lockups when using the
1044 The 690xx MMIO mode has been implemented entirely from the
1045 manual as I don't have the hardware to test it on. At this point
1046 no testing has been done and it is entirely possible that the
1047 "MMIO option will lockup your machine. You have been warned!
1048 However if you do try this option and are willing to debug it,
1049 I'd like to hear from you.
1050
1051 My TrueColor windows are corrupted when using the
1052 Chips and Technologies specify that the memory clock used with
1053 the multimedia engine running should be lower than that used
1054 without. As use of the HiQV chipsets multimedia engine was
1055 supposed to be for things like zoomed video overlays, its use
1056 was supposed to be occasional and so most machines have their
1057 memory clock set to a value that is too high for use with the
1058 "Overlay" option. So with the "Overlay" option, using the
1059 "SetMClk" option to reduce the speed of the memory clock is
1060 recommended.
1061
1062 The mpeg video playing with the XVideo extension has corrupted
1063 colours
1064 The XVideo extension has only recently been added to the chips
1065 driver. Some YUV to RGB colour have been noted at 15 and 16 bit
1066 colour depths. However, 8 and 24 bit colour depths seem to work
1067 fine.
1068
1069 My ct69030 machine locks up when starting X
1070 The ct69030 chipset introduced a new dual channel architecture.
1071 In its current form, X can not take advantage of this second
1072 display channel. In fact if the video BIOS on the machine sets
1073 the ct69030 to a dual channel mode by default, X will lockup
1074 hard at this point. The solution is to use the BIOS setup to
1075 change to a single display channel mode, ensuring that both the
1076 IOSS and MSS registers are set to a single channel mode. Work is
1077 underway to fix this.
1078
1079 I can't start X-windows with 16, 24 or 32bpp
1080 Firstly, is your machine capable of 16/24/32bpp with the mode
1081 specified. Many LCD displays are incapable of using a 24bpp
1082 mode. Also you need at least a 65540 to use 16/24bpp and at
1083 least a 65550 for 32bpp. The amount of memory used by the mode
1084 will be doubled/tripled/quadrupled. The correct options to start
1085 the server with these modes are
1086
1087
1088 startx -- -depth 16 5-6-5 RGB ('64K color', XGA)
1089 startx -- -depth 15 5-5-5 RGB ('Hicolor')
1090 startx -- -depth 24 8-8-8 RGB truecolor
1091
1092
1093 or with the HiQV series of chips you might try
1094
1095 startx -- -depth 24 -fbbpp 32 8-8-8 RGB truecolor
1096
1097
1098 however as X11R7.5 allows 32bpp pixmaps to be used with frame-
1099 buffers operating in 24bpp, this mode of operating will cost per-
1100 formance for no gain in functionality.
1101
1102 Note that the "-bpp" option has been removed and replaced with a
1103 "-depth" and "-fbbpp" option because of the confusion between the
1104 depth and number of bits per pixel used to represent to framebuffer
1105 and the pixmaps in the screens memory.
1106
1107 A general problem with the server that can manifested in many way such
1108 as drawing errors, wavy screens, etc is related to the programmable
1109 clock. Many potential programmable clock register setting are
1110 unstable. However luckily there are many different clock register
1111 setting that can give the same or very similar clocks. The clock code
1112 can be fooled into giving a different and perhaps more stable clock by
1113 simply changing the clock value slightly. For example 65.00MHz might
1114 be unstable while 65.10MHz is not. So for unexplained problems not
1115 addressed above, please try to alter the clock you are using slightly,
1116 say in steps of 0.05MHz and see if the problem goes away.
1117 Alternatively, using the "CRTClkIndx" or "FPClkIndx" option with HiQV
1118 chips might also help.
1119
1120
1121 For other screen drawing related problems, try the "NoAccel" or one of
1122 the XAA acceleration options discussed above. A useful trick for all
1123 laptop computers is to switch between LCD/CRT (usually with something
1124 like Fn-F5), if the screen is having problems.
1125
1126 If you are having driver-related problems that are not addressed by
1127 this document, or if you have found bugs in accelerated functions, you
1128 can try contacting the Xorg team (the current driver maintainer can be
1129 reached at <mailto:eich@freedesktop.org>).
1130
1131
1132 8. Disclaimer
1133
1134
1135 The Xorg X server, allows the user to do damage to their hardware with
1136 software with old monitors which may not tolerate bad display
1137 settings. Although the authors of this software have tried to prevent
1138 this, they disclaim all responsibility for any damage caused by the
1139 software. Use caution, if you think the X server is frying your
1140 screen, TURN THE COMPUTER OFF!!
1141
1142
1143 9. Acknowledgement
1144
1145
1146 The authors of this software wish to acknowledge the support supplied
1147 by Chips and Technologies during the development of this software.
1148
1149
1150 10. Authors
1151
1152
1153 Major Contributors (In no particular order)
1154
1155 o Nozomi Ytow
1156
1157 o Egbert Eich
1158
1159 o David Bateman
1160
1161 o Xavier Ducoin
1162
1163 Contributors (In no particular order)
1164
1165 o Ken Raeburn
1166
1167
1168 o Shigehiro Nomura
1169
1170 o Marc de Courville
1171
1172 o Adam Sulmicki
1173
1174 o Jens Maurer
1175
1176 We also thank the many people on the net who have contributed by
1177 reporting bugs and extensively testing this server.
1178
1179
1180
1181