1c06b6b69Smrg 2c06b6b69Smrg 3c06b6b69Smrg 4c06b6b69Smrg 5c06b6b69Smrg 6c06b6b69Smrg 7c06b6b69Smrg/* Definitions for the Chips and Technology BitBLT engine communication. */ 8c06b6b69Smrg/* These are done using Memory Mapped IO, of the registers */ 9c06b6b69Smrg/* BitBLT modes for register 93D0. */ 10c06b6b69Smrg 11c06b6b69Smrg#define ctPATCOPY 0xF0 12c06b6b69Smrg#define ctTOP2BOTTOM 0x100 13c06b6b69Smrg#define ctBOTTOM2TOP 0x000 14c06b6b69Smrg#define ctLEFT2RIGHT 0x200 15c06b6b69Smrg#define ctRIGHT2LEFT 0x000 16c06b6b69Smrg#define ctSRCFG 0x400 17c06b6b69Smrg#define ctSRCMONO 0x800 18c06b6b69Smrg#define ctPATMONO 0x1000 19c06b6b69Smrg#define ctBGTRANSPARENT 0x2000 20c06b6b69Smrg#define ctSRCSYSTEM 0x4000 21c06b6b69Smrg#define ctPATSOLID 0x80000L 22c06b6b69Smrg#define ctPATSTART0 0x00000L 23c06b6b69Smrg#define ctPATSTART1 0x10000L 24c06b6b69Smrg#define ctPATSTART2 0x20000L 25c06b6b69Smrg#define ctPATSTART3 0x30000L 26c06b6b69Smrg#define ctPATSTART4 0x40000L 27c06b6b69Smrg#define ctPATSTART5 0x50000L 28c06b6b69Smrg#define ctPATSTART6 0x60000L 29c06b6b69Smrg#define ctPATSTART7 0x70000L 30c06b6b69Smrg 31c06b6b69Smrg/* Macros to do useful things with the C&T BitBLT engine */ 32c06b6b69Smrg#define ctBLTWAIT \ 33c06b6b69Smrg {HW_DEBUG(0x4); \ 34c06b6b69Smrg while(MMIO_IN32(cPtr->MMIOBase, MR(0x4)) & 0x00100000){};} 35c06b6b69Smrg 36c06b6b69Smrg#define ctSETROP(op) \ 37c06b6b69Smrg {HW_DEBUG(0x4); MMIO_OUT32(cPtr->MMIOBase, MR(0x4), op);} 38c06b6b69Smrg 39c06b6b69Smrg#define ctSETSRCADDR(srcAddr) \ 40c06b6b69Smrg {HW_DEBUG(0x5); \ 41c06b6b69Smrg MMIO_OUT32(cPtr->MMIOBase, MR(0x5),(srcAddr)&0x7FFFFFL);} 42c06b6b69Smrg 43c06b6b69Smrg#define ctSETDSTADDR(dstAddr) \ 44c06b6b69Smrg{HW_DEBUG(0x6); \ 45c06b6b69Smrg MMIO_OUT32(cPtr->MMIOBase, MR(0x6), (dstAddr)&0x7FFFFFL);} 46c06b6b69Smrg 47c06b6b69Smrg#define ctSETPITCH(srcPitch,dstPitch) \ 48c06b6b69Smrg{HW_DEBUG(0x0); \ 49c06b6b69Smrg MMIO_OUT32(cPtr->MMIOBase, MR(0x0),(((dstPitch)&0xFFFF)<<16)| \ 50c06b6b69Smrg ((srcPitch)&0xFFFF));} 51c06b6b69Smrg 52c06b6b69Smrg#define ctSETHEIGHTWIDTHGO(Height,Width)\ 53c06b6b69Smrg{HW_DEBUG(0x7); \ 54c06b6b69Smrg MMIO_OUT32(cPtr->MMIOBase, MR(0x7), (((Height)&0xFFFF)<<16)| \ 55c06b6b69Smrg ((Width)&0xFFFF));} 56c06b6b69Smrg 57c06b6b69Smrg#define ctSETPATSRCADDR(srcAddr)\ 58c06b6b69Smrg{HW_DEBUG(0x1); \ 59c06b6b69Smrg MMIO_OUT32(cPtr->MMIOBase, MR(0x1),(srcAddr)&0x1FFFFFL);} 60c06b6b69Smrg 61c06b6b69Smrg#define ctSETBGCOLOR8(c) {\ 62c06b6b69Smrg HW_DEBUG(0x2); \ 63c06b6b69Smrg if ((cAcl->bgColor != (c)) || (cAcl->bgColor == -1)) { \ 64c06b6b69Smrg cAcl->bgColor = (c); \ 65c06b6b69Smrg MMIO_OUT32(cPtr->MMIOBase, MR(0x2),\ 66c06b6b69Smrg ((((((c)&0xFF)<<8)|((c)&0xFF))<<16) | \ 67c06b6b69Smrg ((((c)&0xFF)<<8)|((c)&0xFF)))); \ 68c06b6b69Smrg } \ 69c06b6b69Smrg} 70c06b6b69Smrg 71c06b6b69Smrg#define ctSETBGCOLOR16(c) {\ 72c06b6b69Smrg HW_DEBUG(0x2); \ 73c06b6b69Smrg if ((cAcl->bgColor != (c)) || (cAcl->bgColor == -1)) { \ 74c06b6b69Smrg cAcl->bgColor = (c); \ 75c06b6b69Smrg MMIO_OUT32(cPtr->MMIOBase, MR(0x2), \ 76c06b6b69Smrg ((((c)&0xFFFF)<<16)|((c)&0xFFFF))); \ 77c06b6b69Smrg } \ 78c06b6b69Smrg} 79c06b6b69Smrg 80c06b6b69Smrg/* As the 6554x doesn't support 24bpp colour expansion this doesn't work, 81c06b6b69Smrg * It is here only for later use with the 65550 */ 82c06b6b69Smrg#define ctSETBGCOLOR24(c) {\ 83c06b6b69Smrg HW_DEBUG(0x2); \ 84c06b6b69Smrg if ((cAcl->bgColor != (c)) || (cAcl->bgColor == -1)) { \ 85c06b6b69Smrg cAcl->bgColor = (c); \ 86c06b6b69Smrg MMIO_OUT32(cPtr->MMIOBase, MR(0x2),((c)&0xFFFFFF)); \ 87c06b6b69Smrg } \ 88c06b6b69Smrg} 89c06b6b69Smrg 90c06b6b69Smrg#define ctSETFGCOLOR8(c) {\ 91c06b6b69Smrg HW_DEBUG(0x3); \ 92c06b6b69Smrg if ((cAcl->fgColor != (c)) || (cAcl->fgColor == -1)) { \ 93c06b6b69Smrg cAcl->fgColor = (c); \ 94c06b6b69Smrg MMIO_OUT32(cPtr->MMIOBase, MR(0x3), \ 95c06b6b69Smrg ((((((c)&0xFF)<<8)|((c)&0xFF))<<16) | \ 96c06b6b69Smrg ((((c)&0xFF)<<8)|((c)&0xFF)))); \ 97c06b6b69Smrg } \ 98c06b6b69Smrg} 99c06b6b69Smrg 100c06b6b69Smrg#define ctSETFGCOLOR16(c) {\ 101c06b6b69Smrg HW_DEBUG(0x3); \ 102c06b6b69Smrg if ((cAcl->fgColor != (c)) || (cAcl->fgColor == -1)) { \ 103c06b6b69Smrg cAcl->fgColor = (c); \ 104c06b6b69Smrg MMIO_OUT32(cPtr->MMIOBase, MR(0x3), \ 105c06b6b69Smrg ((((c)&0xFFFF)<<16)|((c)&0xFFFF))); \ 106c06b6b69Smrg } \ 107c06b6b69Smrg} 108c06b6b69Smrg 109c06b6b69Smrg/* As the 6554x doesn't support 24bpp colour expansion this doesn't work, 110c06b6b69Smrg * It is here only for later use with the 65550 */ 111c06b6b69Smrg#define ctSETFGCOLOR24(c) {\ 112c06b6b69Smrg HW_DEBUG(0x3); \ 113c06b6b69Smrg if ((cAcl->fgColor != (c)) || (cAcl->fgColor == -1)) { \ 114c06b6b69Smrg cAcl->fgColor = (c); \ 115c06b6b69Smrg MMIO_OUT32(cPtr->MMIOBase, MR(0x3),((c)&0xFFFFFF)); \ 116c06b6b69Smrg } \ 117c06b6b69Smrg} 118c06b6b69Smrg 119c06b6b69Smrg/* Define a Macro to replicate a planemask 64 times and write to address 120c06b6b69Smrg * allocated for planemask pattern */ 121c06b6b69Smrg#define ctWRITEPLANEMASK8(mask,addr) { \ 122c06b6b69Smrg if (cAcl->planemask != (mask&0xFF)) { \ 123c06b6b69Smrg cAcl->planemask = (mask&0xFF); \ 124c06b6b69Smrg memset((unsigned char *)cPtr->FbBase + addr, (mask&0xFF), 64); \ 125c06b6b69Smrg } \ 126c06b6b69Smrg} 127c06b6b69Smrg 128c06b6b69Smrg#define ctWRITEPLANEMASK16(mask,addr) { \ 129c06b6b69Smrg if (cAcl->planemask != (mask&0xFFFF)) { \ 130c06b6b69Smrg cAcl->planemask = (mask&0xFFFF); \ 131c06b6b69Smrg { int i; \ 132c06b6b69Smrg for (i = 0; i < 64; i++) { \ 133c06b6b69Smrg memcpy((unsigned char *)cPtr->FbBase + addr \ 134c06b6b69Smrg + i * 2, &mask, 2); \ 135c06b6b69Smrg } \ 136c06b6b69Smrg } \ 137c06b6b69Smrg } \ 138c06b6b69Smrg} 139