ct_regs.c revision 9f4658d1 
1/*
2 * Created 1998 by David Bateman <dbateman@eng.uts.edu.au>
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that
7 * copyright notice and this permission notice appear in supporting
8 * documentation, and that the name of the authors not be used in
9 * advertising or publicity pertaining to distribution of the software without
10 * specific, written prior permission.  The authors makes no representations
11 * about the suitability of this software for any purpose.  It is provided
12 * "as is" without express or implied warranty.
13 *
14 * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
20 * PERFORMANCE OF THIS SOFTWARE.
21 */
22
23#ifdef HAVE_CONFIG_H
24#include "config.h"
25#endif
26
27/*
28 * The functions in this file are used to read/write the C&T extension register
29 * and supply MMIO replacements of the VGA register access functions in
30 * vgaHW.c for chips that support MMIO access (eg 69000). Unlike the MGA
31 * chips, for instance, the C&T chipsets don't have a direct mapping between
32 * the MMIO mapped vga registers and the PIO versions.
33 *
34 * In General, these are the ONLY supported way of access the video processors
35 * registers. Exception are
36 *
37 * 1) chipsFindIsaDevice, where we don't know the chipset and so we don't know
38 *    if the chipset supports MMIO access to its VGA registers, and we don't
39 *    know the chips MemBase address and so can't map the VGA registers even
40 *    if the chip did support MMIO. This effectively limits the use of non-PCI
41 *    MMIO and multihead to a single card accessing 0x3D6/0x3D7. I.E. You can
42 *    only have a single C&T card in a non-PCI multihead arrangement. Also as
43 *    ISA has no method to disable I/O access to a card ISA multihead will
44 *    never be supported.
45 *
46 * 2) ct_Blitter.h, ct_BlitMM.h and ct_BltHiQV.h, where speed is crucial and
47 *    we know exactly whether we are using MMIO or PIO.
48 *
49 * 3) The 6554x 32bit DRxx in ct_cursor.c where the choice between MMIO and
50 *    PIO is made explicitly
51 */
52
53
54/* All drivers should typically include these */
55#include "xf86.h"
56#include "xf86_OSproc.h"
57
58/* Everything using inb/outb, etc needs "compiler.h" */
59#include "compiler.h"
60
61/* Drivers for PCI hardware need this */
62#include "xf86PciInfo.h"
63
64/* Drivers that need to access the PCI config space directly need this */
65#include "xf86Pci.h"
66
67/* Driver specific headers */
68#include "ct_driver.h"
69
70#define CHIPS_MONO_STAT_1		0x3BA
71#define CHIPS_STAT_0			0x3BA
72#define CHIPS_MSS			0x3CB
73#define CHIPS_IOSS			0x3CD
74#define CHIPS_FR_INDEX			0x3D0
75#define CHIPS_FR_DATA			0x3D1
76#define CHIPS_MR_INDEX			0x3D2
77#define CHIPS_MR_DATA			0x3D3
78#define CHIPS_XR_INDEX			0x3D6
79#define CHIPS_XR_DATA			0x3D7
80#define CHIPS_COLOR_STAT_1		0x3DA
81
82#define CHIPS_MMIO_MONO_CRTC_INDEX	0x768
83#define CHIPS_MMIO_MONO_CRTC_DATA	0x769
84#define CHIPS_MMIO_MONO_STAT_1		0x774
85#define CHIPS_MMIO_ATTR_INDEX		0x780
86#define CHIPS_MMIO_ATTR_DATA_W		0x780
87#define CHIPS_MMIO_ATTR_DATA_R		0x781
88#define CHIPS_MMIO_STAT_0		0x784
89#define CHIPS_MMIO_MISC_OUT_W		0x784
90#define CHIPS_MMIO_SEQ_INDEX		0x788
91#define CHIPS_MMIO_SEQ_DATA		0x789
92#define CHIPS_MMIO_DAC_MASK		0x78C
93#define CHIPS_MMIO_DAC_READ_ADDR	0x78D
94#define CHIPS_MMIO_DAC_WRITE_ADDR	0x790
95#define CHIPS_MMIO_DAC_DATA		0x791
96#define CHIPS_MMIO_FEATURE_R		0x794
97#define CHIPS_MMIO_MSS			0x795
98#define CHIPS_MMIO_MISC_OUT_R		0x798
99#define CHIPS_MMIO_IOSS			0x799
100#define CHIPS_MMIO_GRAPH_INDEX		0x79C
101#define CHIPS_MMIO_GRAPH_DATA		0x79D
102#define CHIPS_MMIO_FR_INDEX		0x7A0
103#define CHIPS_MMIO_FR_DATA		0x7A1
104#define CHIPS_MMIO_MR_INDEX		0x7A4
105#define CHIPS_MMIO_MR_DATA		0x7A5
106#define CHIPS_MMIO_COLOR_CRTC_INDEX	0x7A8
107#define CHIPS_MMIO_COLOR_CRTC_DATA	0x7A9
108#define CHIPS_MMIO_XR_INDEX		0x7AC
109#define CHIPS_MMIO_XR_DATA		0x7AD
110#define CHIPS_MMIO_COLOR_STAT_1		0x7B4
111
112/*
113 * PIO Access to the C&T extension registers
114 */
115void
116chipsStdWriteXR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
117{
118    outb(cPtr->PIOBase + CHIPS_XR_INDEX, index);
119    outb(cPtr->PIOBase + CHIPS_XR_DATA, value);
120}
121
122static CARD8
123chipsStdReadXR(CHIPSPtr cPtr, CARD8 index)
124{
125    outb(cPtr->PIOBase + CHIPS_XR_INDEX, index);
126    return inb(cPtr->PIOBase + CHIPS_XR_DATA);
127}
128
129static void
130chipsStdWriteFR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
131{
132    outb(cPtr->PIOBase + CHIPS_FR_INDEX, index);
133    outb(cPtr->PIOBase + CHIPS_FR_DATA, value);
134}
135
136static CARD8
137chipsStdReadFR(CHIPSPtr cPtr, CARD8 index)
138{
139    outb(cPtr->PIOBase + CHIPS_FR_INDEX, index);
140    return inb(cPtr->PIOBase + CHIPS_FR_DATA);
141}
142
143static void
144chipsStdWriteMR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
145{
146    outb(cPtr->PIOBase + CHIPS_MR_INDEX, index);
147    outb(cPtr->PIOBase + CHIPS_MR_DATA, value);
148}
149
150static CARD8
151chipsStdReadMR(CHIPSPtr cPtr, CARD8 index)
152{
153    outb(cPtr->PIOBase + CHIPS_MR_INDEX, index);
154    return inb(cPtr->PIOBase + CHIPS_MR_DATA);
155}
156
157static void
158chipsStdWriteMSS(CHIPSPtr cPtr, vgaHWPtr hwp, CARD8 value)
159{
160    outb(cPtr->PIOBase + CHIPS_MSS, value);
161}
162
163static CARD8
164chipsStdReadMSS(CHIPSPtr cPtr)
165{
166    return inb(cPtr->PIOBase + CHIPS_MSS);
167}
168
169static void
170chipsStdWriteIOSS(CHIPSPtr cPtr, CARD8 value)
171{
172    outb(cPtr->PIOBase + CHIPS_IOSS, value);
173}
174
175static CARD8
176chipsStdReadIOSS(CHIPSPtr cPtr)
177{
178    return inb(cPtr->PIOBase + CHIPS_IOSS);
179}
180
181void
182CHIPSSetStdExtFuncs(CHIPSPtr cPtr)
183{
184    cPtr->writeFR		= chipsStdWriteFR;
185    cPtr->readFR		= chipsStdReadFR;
186    cPtr->writeMR		= chipsStdWriteMR;
187    cPtr->readMR		= chipsStdReadMR;
188    cPtr->writeXR		= chipsStdWriteXR;
189    cPtr->readXR		= chipsStdReadXR;
190    cPtr->writeMSS		= chipsStdWriteMSS;
191    cPtr->readMSS		= chipsStdReadMSS;
192    cPtr->writeIOSS		= chipsStdWriteIOSS;
193    cPtr->readIOSS		= chipsStdReadIOSS;
194}
195
196/*
197 * MMIO Access to the C&T extension registers
198 */
199
200#define chipsminb(p) MMIO_IN8(cPtr->MMIOBaseVGA, (p))
201#define chipsmoutb(p,v) MMIO_OUT8(cPtr->MMIOBaseVGA, (p),(v))
202
203static void
204chipsMmioWriteXR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
205{
206    chipsmoutb(CHIPS_MMIO_XR_INDEX, index);
207    chipsmoutb(CHIPS_MMIO_XR_DATA, value);
208}
209
210static CARD8
211chipsMmioReadXR(CHIPSPtr cPtr, CARD8 index)
212{
213    chipsmoutb(CHIPS_MMIO_XR_INDEX, index);
214    return chipsminb(CHIPS_MMIO_XR_DATA);
215}
216
217static void
218chipsMmioWriteFR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
219{
220    chipsmoutb(CHIPS_MMIO_FR_INDEX, index);
221    chipsmoutb(CHIPS_MMIO_FR_DATA, value);
222}
223
224static CARD8
225chipsMmioReadFR(CHIPSPtr cPtr, CARD8 index)
226{
227    chipsmoutb(CHIPS_MMIO_FR_INDEX, index);
228    return chipsminb(CHIPS_MMIO_FR_DATA);
229}
230
231static void
232chipsMmioWriteMR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
233{
234    chipsmoutb(CHIPS_MMIO_MR_INDEX, index);
235    chipsmoutb(CHIPS_MMIO_MR_DATA, value);
236}
237
238static CARD8
239chipsMmioReadMR(CHIPSPtr cPtr, CARD8 index)
240{
241    chipsmoutb(CHIPS_MMIO_MR_INDEX, index);
242    return chipsminb(CHIPS_MMIO_MR_DATA);
243}
244
245static void
246chipsMmioWriteMSS(CHIPSPtr cPtr, vgaHWPtr hwp, CARD8 value)
247{
248    /* 69030 MMIO Fix.
249     *
250     * <value> determines which MMIOBase to use; either
251     * Pipe A or Pipe B. -GHB
252     */
253    if ((value & MSS_SHADOW) == MSS_PIPE_B)
254	cPtr->MMIOBaseVGA = cPtr->MMIOBasePipeB;
255    else
256	cPtr->MMIOBaseVGA = cPtr->MMIOBasePipeA;
257
258    hwp->MMIOBase = cPtr->MMIOBaseVGA;
259
260    /* Since our Pipe constants don't set bit 3 of MSS, the value
261     * written here has no effect on the hardware's behavior. It
262     * does allow us to use the value returned by readMSS() to key
263     * the above logic, though. -GHB
264     */
265    chipsmoutb(CHIPS_MMIO_MSS, value);
266}
267
268static CARD8
269chipsMmioReadMSS(CHIPSPtr cPtr)
270{
271    return chipsminb(CHIPS_MMIO_MSS);
272}
273
274static void
275chipsMmioWriteIOSS(CHIPSPtr cPtr, CARD8 value)
276{
277    chipsmoutb(CHIPS_MMIO_IOSS, value);
278}
279
280static CARD8
281chipsMmioReadIOSS(CHIPSPtr cPtr)
282{
283    return chipsminb(CHIPS_MMIO_IOSS);
284}
285
286void
287CHIPSSetMmioExtFuncs(CHIPSPtr cPtr)
288{
289    cPtr->writeFR		= chipsMmioWriteFR;
290    cPtr->readFR		= chipsMmioReadFR;
291    cPtr->writeMR		= chipsMmioWriteMR;
292    cPtr->readMR		= chipsMmioReadMR;
293    cPtr->writeXR		= chipsMmioWriteXR;
294    cPtr->readXR		= chipsMmioReadXR;
295    cPtr->writeMSS		= chipsMmioWriteMSS;
296    cPtr->readMSS		= chipsMmioReadMSS;
297    cPtr->writeIOSS		= chipsMmioWriteIOSS;
298    cPtr->readIOSS		= chipsMmioReadIOSS;
299}
300
301/*
302 * MMIO versions of the VGA register access functions.
303 */
304
305#define minb(p) MMIO_IN8(hwp->MMIOBase, (p))
306#define moutb(p,v) MMIO_OUT8(hwp->MMIOBase, (p),(v))
307
308static void
309chipsMmioWriteCrtc(vgaHWPtr hwp, CARD8 index, CARD8 value)
310{
311    if (hwp->IOBase == VGA_IOBASE_MONO) {
312	moutb(CHIPS_MMIO_MONO_CRTC_INDEX, index);
313    	moutb(CHIPS_MMIO_MONO_CRTC_DATA, value);
314    } else {
315	moutb(CHIPS_MMIO_COLOR_CRTC_INDEX, index);
316    	moutb(CHIPS_MMIO_COLOR_CRTC_DATA, value);
317    }
318}
319
320static CARD8
321chipsMmioReadCrtc(vgaHWPtr hwp, CARD8 index)
322{
323    if (hwp->IOBase == VGA_IOBASE_MONO) {
324	moutb(CHIPS_MMIO_MONO_CRTC_INDEX, index);
325    	return minb(CHIPS_MMIO_MONO_CRTC_DATA);
326    } else {
327	moutb(CHIPS_MMIO_COLOR_CRTC_INDEX, index);
328    	return minb(CHIPS_MMIO_COLOR_CRTC_DATA);
329    }
330}
331
332static void
333chipsMmioWriteGr(vgaHWPtr hwp, CARD8 index, CARD8 value)
334{
335    moutb(CHIPS_MMIO_GRAPH_INDEX, index);
336    moutb(CHIPS_MMIO_GRAPH_DATA, value);
337}
338
339static CARD8
340chipsMmioReadGr(vgaHWPtr hwp, CARD8 index)
341{
342    moutb(CHIPS_MMIO_GRAPH_INDEX, index);
343    return minb(CHIPS_MMIO_GRAPH_DATA);
344}
345
346static void
347chipsMmioWriteSeq(vgaHWPtr hwp, CARD8 index, CARD8 value)
348{
349    moutb(CHIPS_MMIO_SEQ_INDEX, index);
350    moutb(CHIPS_MMIO_SEQ_DATA, value);
351}
352
353static CARD8
354chipsMmioReadSeq(vgaHWPtr hwp, CARD8 index)
355{
356    moutb(CHIPS_MMIO_SEQ_INDEX, index);
357    return minb(CHIPS_MMIO_SEQ_DATA);
358}
359
360static void
361chipsMmioWriteAttr(vgaHWPtr hwp, CARD8 index, CARD8 value)
362{
363    if (hwp->paletteEnabled)
364	index &= ~0x20;
365    else
366	index |= 0x20;
367
368    if (hwp->IOBase == VGA_IOBASE_MONO)
369	(void) minb(CHIPS_MMIO_MONO_STAT_1);
370    else
371	(void) minb(CHIPS_MMIO_COLOR_STAT_1);
372    moutb(CHIPS_MMIO_ATTR_INDEX, index);
373    moutb(CHIPS_MMIO_ATTR_DATA_W, value);
374}
375
376static CARD8
377chipsMmioReadAttr(vgaHWPtr hwp, CARD8 index)
378{
379    if (hwp->paletteEnabled)
380	index &= ~0x20;
381    else
382	index |= 0x20;
383
384    if (hwp->IOBase == VGA_IOBASE_MONO)
385	(void) minb(CHIPS_MMIO_MONO_STAT_1);
386    else
387	(void) minb(CHIPS_MMIO_COLOR_STAT_1);
388    moutb(CHIPS_MMIO_ATTR_INDEX, index);
389    return minb(CHIPS_MMIO_ATTR_DATA_R);
390}
391
392static void
393chipsMmioWriteMiscOut(vgaHWPtr hwp, CARD8 value)
394{
395    moutb(CHIPS_MMIO_MISC_OUT_W, value);
396}
397
398static CARD8
399chipsMmioReadMiscOut(vgaHWPtr hwp)
400{
401    return minb(CHIPS_MMIO_MISC_OUT_R);
402}
403
404static void
405chipsMmioEnablePalette(vgaHWPtr hwp)
406{
407    if (hwp->IOBase == VGA_IOBASE_MONO)
408	(void) minb(CHIPS_MMIO_MONO_STAT_1);
409    else
410	(void) minb(CHIPS_MMIO_COLOR_STAT_1);
411    moutb(CHIPS_MMIO_ATTR_INDEX, 0x00);
412    hwp->paletteEnabled = TRUE;
413}
414
415static void
416chipsMmioDisablePalette(vgaHWPtr hwp)
417{
418    if (hwp->IOBase == VGA_IOBASE_MONO)
419	(void) minb(CHIPS_MMIO_MONO_STAT_1);
420    else
421	(void) minb(CHIPS_MMIO_COLOR_STAT_1);
422    moutb(CHIPS_MMIO_ATTR_INDEX, 0x20);
423    hwp->paletteEnabled = FALSE;
424}
425
426static void
427chipsMmioWriteDacMask(vgaHWPtr hwp, CARD8 value)
428{
429    moutb(CHIPS_MMIO_DAC_MASK, value);
430}
431
432static CARD8
433chipsMmioReadDacMask(vgaHWPtr hwp)
434{
435    return minb(CHIPS_MMIO_DAC_MASK);
436}
437
438static void
439chipsMmioWriteDacReadAddr(vgaHWPtr hwp, CARD8 value)
440{
441    moutb(CHIPS_MMIO_DAC_READ_ADDR, value);
442}
443
444static void
445chipsMmioWriteDacWriteAddr(vgaHWPtr hwp, CARD8 value)
446{
447    moutb(CHIPS_MMIO_DAC_WRITE_ADDR, value);
448}
449
450static void
451chipsMmioWriteDacData(vgaHWPtr hwp, CARD8 value)
452{
453    moutb(CHIPS_MMIO_DAC_DATA, value);
454}
455
456static CARD8
457chipsMmioReadDacData(vgaHWPtr hwp)
458{
459    return minb(CHIPS_MMIO_DAC_DATA);
460}
461
462static CARD8
463chipsMmioReadST00(vgaHWPtr hwp)
464{
465    return minb(CHIPS_MMIO_STAT_0);
466}
467
468static CARD8
469chipsMmioReadST01(vgaHWPtr hwp)
470{
471    if (hwp->IOBase == VGA_IOBASE_MONO)
472	return minb(CHIPS_MMIO_MONO_STAT_1);
473    else
474	return minb(CHIPS_MMIO_COLOR_STAT_1);
475}
476
477static CARD8
478chipsMmioReadFCR(vgaHWPtr hwp)
479{
480    return minb(CHIPS_MMIO_FEATURE_R);
481}
482
483static void
484chipsMmioWriteFCR(vgaHWPtr hwp, CARD8 value)
485{
486    if (hwp->IOBase == VGA_IOBASE_MONO) {
487    	moutb(CHIPS_MMIO_MONO_STAT_1, value);
488    } else {
489    	moutb(CHIPS_MMIO_COLOR_STAT_1, value);
490    }
491}
492
493void
494CHIPSHWSetMmioFuncs(ScrnInfoPtr pScrn, CARD8 *base, int offset)
495{
496    vgaHWPtr hwp = VGAHWPTR(pScrn);
497
498    hwp->writeCrtc		= chipsMmioWriteCrtc;
499    hwp->readCrtc		= chipsMmioReadCrtc;
500    hwp->writeGr		= chipsMmioWriteGr;
501    hwp->readGr			= chipsMmioReadGr;
502    hwp->writeAttr		= chipsMmioWriteAttr;
503    hwp->readAttr		= chipsMmioReadAttr;
504    hwp->writeSeq		= chipsMmioWriteSeq;
505    hwp->readSeq		= chipsMmioReadSeq;
506    hwp->writeMiscOut		= chipsMmioWriteMiscOut;
507    hwp->readMiscOut		= chipsMmioReadMiscOut;
508    hwp->enablePalette		= chipsMmioEnablePalette;
509    hwp->disablePalette		= chipsMmioDisablePalette;
510    hwp->writeDacMask		= chipsMmioWriteDacMask;
511    hwp->readDacMask		= chipsMmioReadDacMask;
512    hwp->writeDacWriteAddr	= chipsMmioWriteDacWriteAddr;
513    hwp->writeDacReadAddr	= chipsMmioWriteDacReadAddr;
514    hwp->writeDacData		= chipsMmioWriteDacData;
515    hwp->readDacData		= chipsMmioReadDacData;
516    hwp->readST00               = chipsMmioReadST00;
517    hwp->readST01               = chipsMmioReadST01;
518    hwp->readFCR               = chipsMmioReadFCR;
519    hwp->writeFCR              = chipsMmioWriteFCR;
520    hwp->MMIOBase		= base;
521    hwp->MMIOOffset		= offset;
522}
523
524
525
526
527