ct_regs.c revision c06b6b69 
1/*
2 * Created 1998 by David Bateman <dbateman@eng.uts.edu.au>
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that
7 * copyright notice and this permission notice appear in supporting
8 * documentation, and that the name of the authors not be used in
9 * advertising or publicity pertaining to distribution of the software without
10 * specific, written prior permission.  The authors makes no representations
11 * about the suitability of this software for any purpose.  It is provided
12 * "as is" without express or implied warranty.
13 *
14 * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
20 * PERFORMANCE OF THIS SOFTWARE.
21 */
22/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/chips/ct_regs.c,v 1.8tsi Exp $ */
23
24#ifdef HAVE_CONFIG_H
25#include "config.h"
26#endif
27
28/*
29 * The functions in this file are used to read/write the C&T extension register
30 * and supply MMIO replacements of the VGA register access functions in
31 * vgaHW.c for chips that support MMIO access (eg 69000). Unlike the MGA
32 * chips, for instance, the C&T chipsets don't have a direct mapping between
33 * the MMIO mapped vga registers and the PIO versions.
34 *
35 * In General, these are the ONLY supported way of access the video processors
36 * registers. Exception are
37 *
38 * 1) chipsFindIsaDevice, where we don't know the chipset and so we don't know
39 *    if the chipset supports MMIO access to its VGA registers, and we don't
40 *    know the chips MemBase address and so can't map the VGA registers even
41 *    if the chip did support MMIO. This effectively limits the use of non-PCI
42 *    MMIO and multihead to a single card accessing 0x3D6/0x3D7. I.E. You can
43 *    only have a single C&T card in a non-PCI multihead arrangement. Also as
44 *    ISA has no method to disable I/O access to a card ISA multihead will
45 *    never be supported.
46 *
47 * 2) ct_Blitter.h, ct_BlitMM.h and ct_BltHiQV.h, where speed is crucial and
48 *    we know exactly whether we are using MMIO or PIO.
49 *
50 * 3) The 6554x 32bit DRxx in ct_cursor.c where the choice between MMIO and
51 *    PIO is made explicitly
52 */
53
54
55/* All drivers should typically include these */
56#include "xf86.h"
57#include "xf86_OSproc.h"
58
59/* Everything using inb/outb, etc needs "compiler.h" */
60#include "compiler.h"
61
62/* Drivers for PCI hardware need this */
63#include "xf86PciInfo.h"
64
65/* Drivers that need to access the PCI config space directly need this */
66#include "xf86Pci.h"
67
68/* This is used for module versioning */
69#include "xf86Version.h"
70
71/* Driver specific headers */
72#include "ct_driver.h"
73
74#define CHIPS_MONO_STAT_1		0x3BA
75#define CHIPS_STAT_0			0x3BA
76#define CHIPS_MSS			0x3CB
77#define CHIPS_IOSS			0x3CD
78#define CHIPS_FR_INDEX			0x3D0
79#define CHIPS_FR_DATA			0x3D1
80#define CHIPS_MR_INDEX			0x3D2
81#define CHIPS_MR_DATA			0x3D3
82#define CHIPS_XR_INDEX			0x3D6
83#define CHIPS_XR_DATA			0x3D7
84#define CHIPS_COLOR_STAT_1		0x3DA
85
86#define CHIPS_MMIO_MONO_CRTC_INDEX	0x768
87#define CHIPS_MMIO_MONO_CRTC_DATA	0x769
88#define CHIPS_MMIO_MONO_STAT_1		0x774
89#define CHIPS_MMIO_ATTR_INDEX		0x780
90#define CHIPS_MMIO_ATTR_DATA_W		0x780
91#define CHIPS_MMIO_ATTR_DATA_R		0x781
92#define CHIPS_MMIO_STAT_0		0x784
93#define CHIPS_MMIO_MISC_OUT_W		0x784
94#define CHIPS_MMIO_SEQ_INDEX		0x788
95#define CHIPS_MMIO_SEQ_DATA		0x789
96#define CHIPS_MMIO_DAC_MASK		0x78C
97#define CHIPS_MMIO_DAC_READ_ADDR	0x78D
98#define CHIPS_MMIO_DAC_WRITE_ADDR	0x790
99#define CHIPS_MMIO_DAC_DATA		0x791
100#define CHIPS_MMIO_FEATURE_R		0x794
101#define CHIPS_MMIO_MSS			0x795
102#define CHIPS_MMIO_MISC_OUT_R		0x798
103#define CHIPS_MMIO_IOSS			0x799
104#define CHIPS_MMIO_GRAPH_INDEX		0x79C
105#define CHIPS_MMIO_GRAPH_DATA		0x79D
106#define CHIPS_MMIO_FR_INDEX		0x7A0
107#define CHIPS_MMIO_FR_DATA		0x7A1
108#define CHIPS_MMIO_MR_INDEX		0x7A4
109#define CHIPS_MMIO_MR_DATA		0x7A5
110#define CHIPS_MMIO_COLOR_CRTC_INDEX	0x7A8
111#define CHIPS_MMIO_COLOR_CRTC_DATA	0x7A9
112#define CHIPS_MMIO_XR_INDEX		0x7AC
113#define CHIPS_MMIO_XR_DATA		0x7AD
114#define CHIPS_MMIO_COLOR_STAT_1		0x7B4
115
116/*
117 * PIO Access to the C&T extension registers
118 */
119void
120chipsStdWriteXR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
121{
122    outb(cPtr->PIOBase + CHIPS_XR_INDEX, index);
123    outb(cPtr->PIOBase + CHIPS_XR_DATA, value);
124}
125
126static CARD8
127chipsStdReadXR(CHIPSPtr cPtr, CARD8 index)
128{
129    outb(cPtr->PIOBase + CHIPS_XR_INDEX, index);
130    return inb(cPtr->PIOBase + CHIPS_XR_DATA);
131}
132
133static void
134chipsStdWriteFR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
135{
136    outb(cPtr->PIOBase + CHIPS_FR_INDEX, index);
137    outb(cPtr->PIOBase + CHIPS_FR_DATA, value);
138}
139
140static CARD8
141chipsStdReadFR(CHIPSPtr cPtr, CARD8 index)
142{
143    outb(cPtr->PIOBase + CHIPS_FR_INDEX, index);
144    return inb(cPtr->PIOBase + CHIPS_FR_DATA);
145}
146
147static void
148chipsStdWriteMR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
149{
150    outb(cPtr->PIOBase + CHIPS_MR_INDEX, index);
151    outb(cPtr->PIOBase + CHIPS_MR_DATA, value);
152}
153
154static CARD8
155chipsStdReadMR(CHIPSPtr cPtr, CARD8 index)
156{
157    outb(cPtr->PIOBase + CHIPS_MR_INDEX, index);
158    return inb(cPtr->PIOBase + CHIPS_MR_DATA);
159}
160
161static void
162chipsStdWriteMSS(CHIPSPtr cPtr, vgaHWPtr hwp, CARD8 value)
163{
164    outb(cPtr->PIOBase + CHIPS_MSS, value);
165}
166
167static CARD8
168chipsStdReadMSS(CHIPSPtr cPtr)
169{
170    return inb(cPtr->PIOBase + CHIPS_MSS);
171}
172
173static void
174chipsStdWriteIOSS(CHIPSPtr cPtr, CARD8 value)
175{
176    outb(cPtr->PIOBase + CHIPS_IOSS, value);
177}
178
179static CARD8
180chipsStdReadIOSS(CHIPSPtr cPtr)
181{
182    return inb(cPtr->PIOBase + CHIPS_IOSS);
183}
184
185void
186CHIPSSetStdExtFuncs(CHIPSPtr cPtr)
187{
188    cPtr->writeFR		= chipsStdWriteFR;
189    cPtr->readFR		= chipsStdReadFR;
190    cPtr->writeMR		= chipsStdWriteMR;
191    cPtr->readMR		= chipsStdReadMR;
192    cPtr->writeXR		= chipsStdWriteXR;
193    cPtr->readXR		= chipsStdReadXR;
194    cPtr->writeMSS		= chipsStdWriteMSS;
195    cPtr->readMSS		= chipsStdReadMSS;
196    cPtr->writeIOSS		= chipsStdWriteIOSS;
197    cPtr->readIOSS		= chipsStdReadIOSS;
198}
199
200/*
201 * MMIO Access to the C&T extension registers
202 */
203
204#define chipsminb(p) MMIO_IN8(cPtr->MMIOBaseVGA, (p))
205#define chipsmoutb(p,v) MMIO_OUT8(cPtr->MMIOBaseVGA, (p),(v))
206
207static void
208chipsMmioWriteXR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
209{
210    chipsmoutb(CHIPS_MMIO_XR_INDEX, index);
211    chipsmoutb(CHIPS_MMIO_XR_DATA, value);
212}
213
214static CARD8
215chipsMmioReadXR(CHIPSPtr cPtr, CARD8 index)
216{
217    chipsmoutb(CHIPS_MMIO_XR_INDEX, index);
218    return chipsminb(CHIPS_MMIO_XR_DATA);
219}
220
221static void
222chipsMmioWriteFR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
223{
224    chipsmoutb(CHIPS_MMIO_FR_INDEX, index);
225    chipsmoutb(CHIPS_MMIO_FR_DATA, value);
226}
227
228static CARD8
229chipsMmioReadFR(CHIPSPtr cPtr, CARD8 index)
230{
231    chipsmoutb(CHIPS_MMIO_FR_INDEX, index);
232    return chipsminb(CHIPS_MMIO_FR_DATA);
233}
234
235static void
236chipsMmioWriteMR(CHIPSPtr cPtr, CARD8 index, CARD8 value)
237{
238    chipsmoutb(CHIPS_MMIO_MR_INDEX, index);
239    chipsmoutb(CHIPS_MMIO_MR_DATA, value);
240}
241
242static CARD8
243chipsMmioReadMR(CHIPSPtr cPtr, CARD8 index)
244{
245    chipsmoutb(CHIPS_MMIO_MR_INDEX, index);
246    return chipsminb(CHIPS_MMIO_MR_DATA);
247}
248
249static void
250chipsMmioWriteMSS(CHIPSPtr cPtr, vgaHWPtr hwp, CARD8 value)
251{
252    /* 69030 MMIO Fix.
253     *
254     * <value> determines which MMIOBase to use; either
255     * Pipe A or Pipe B. -GHB
256     */
257    if ((value & MSS_SHADOW) == MSS_PIPE_B)
258	cPtr->MMIOBaseVGA = cPtr->MMIOBasePipeB;
259    else
260	cPtr->MMIOBaseVGA = cPtr->MMIOBasePipeA;
261
262    hwp->MMIOBase = cPtr->MMIOBaseVGA;
263
264    /* Since our Pipe constants don't set bit 3 of MSS, the value
265     * written here has no effect on the hardware's behavior. It
266     * does allow us to use the value returned by readMSS() to key
267     * the above logic, though. -GHB
268     */
269    chipsmoutb(CHIPS_MMIO_MSS, value);
270}
271
272static CARD8
273chipsMmioReadMSS(CHIPSPtr cPtr)
274{
275    return chipsminb(CHIPS_MMIO_MSS);
276}
277
278static void
279chipsMmioWriteIOSS(CHIPSPtr cPtr, CARD8 value)
280{
281    chipsmoutb(CHIPS_MMIO_IOSS, value);
282}
283
284static CARD8
285chipsMmioReadIOSS(CHIPSPtr cPtr)
286{
287    return chipsminb(CHIPS_MMIO_IOSS);
288}
289
290void
291CHIPSSetMmioExtFuncs(CHIPSPtr cPtr)
292{
293    cPtr->writeFR		= chipsMmioWriteFR;
294    cPtr->readFR		= chipsMmioReadFR;
295    cPtr->writeMR		= chipsMmioWriteMR;
296    cPtr->readMR		= chipsMmioReadMR;
297    cPtr->writeXR		= chipsMmioWriteXR;
298    cPtr->readXR		= chipsMmioReadXR;
299    cPtr->writeMSS		= chipsMmioWriteMSS;
300    cPtr->readMSS		= chipsMmioReadMSS;
301    cPtr->writeIOSS		= chipsMmioWriteIOSS;
302    cPtr->readIOSS		= chipsMmioReadIOSS;
303}
304
305/*
306 * MMIO versions of the VGA register access functions.
307 */
308
309#define minb(p) MMIO_IN8(hwp->MMIOBase, (p))
310#define moutb(p,v) MMIO_OUT8(hwp->MMIOBase, (p),(v))
311
312static void
313chipsMmioWriteCrtc(vgaHWPtr hwp, CARD8 index, CARD8 value)
314{
315    if (hwp->IOBase == VGA_IOBASE_MONO) {
316	moutb(CHIPS_MMIO_MONO_CRTC_INDEX, index);
317    	moutb(CHIPS_MMIO_MONO_CRTC_DATA, value);
318    } else {
319	moutb(CHIPS_MMIO_COLOR_CRTC_INDEX, index);
320    	moutb(CHIPS_MMIO_COLOR_CRTC_DATA, value);
321    }
322}
323
324static CARD8
325chipsMmioReadCrtc(vgaHWPtr hwp, CARD8 index)
326{
327    if (hwp->IOBase == VGA_IOBASE_MONO) {
328	moutb(CHIPS_MMIO_MONO_CRTC_INDEX, index);
329    	return minb(CHIPS_MMIO_MONO_CRTC_DATA);
330    } else {
331	moutb(CHIPS_MMIO_COLOR_CRTC_INDEX, index);
332    	return minb(CHIPS_MMIO_COLOR_CRTC_DATA);
333    }
334}
335
336static void
337chipsMmioWriteGr(vgaHWPtr hwp, CARD8 index, CARD8 value)
338{
339    moutb(CHIPS_MMIO_GRAPH_INDEX, index);
340    moutb(CHIPS_MMIO_GRAPH_DATA, value);
341}
342
343static CARD8
344chipsMmioReadGr(vgaHWPtr hwp, CARD8 index)
345{
346    moutb(CHIPS_MMIO_GRAPH_INDEX, index);
347    return minb(CHIPS_MMIO_GRAPH_DATA);
348}
349
350static void
351chipsMmioWriteSeq(vgaHWPtr hwp, CARD8 index, CARD8 value)
352{
353    moutb(CHIPS_MMIO_SEQ_INDEX, index);
354    moutb(CHIPS_MMIO_SEQ_DATA, value);
355}
356
357static CARD8
358chipsMmioReadSeq(vgaHWPtr hwp, CARD8 index)
359{
360    moutb(CHIPS_MMIO_SEQ_INDEX, index);
361    return minb(CHIPS_MMIO_SEQ_DATA);
362}
363
364static void
365chipsMmioWriteAttr(vgaHWPtr hwp, CARD8 index, CARD8 value)
366{
367    if (hwp->paletteEnabled)
368	index &= ~0x20;
369    else
370	index |= 0x20;
371
372    if (hwp->IOBase == VGA_IOBASE_MONO)
373	(void) minb(CHIPS_MMIO_MONO_STAT_1);
374    else
375	(void) minb(CHIPS_MMIO_COLOR_STAT_1);
376    moutb(CHIPS_MMIO_ATTR_INDEX, index);
377    moutb(CHIPS_MMIO_ATTR_DATA_W, value);
378}
379
380static CARD8
381chipsMmioReadAttr(vgaHWPtr hwp, CARD8 index)
382{
383    if (hwp->paletteEnabled)
384	index &= ~0x20;
385    else
386	index |= 0x20;
387
388    if (hwp->IOBase == VGA_IOBASE_MONO)
389	(void) minb(CHIPS_MMIO_MONO_STAT_1);
390    else
391	(void) minb(CHIPS_MMIO_COLOR_STAT_1);
392    moutb(CHIPS_MMIO_ATTR_INDEX, index);
393    return minb(CHIPS_MMIO_ATTR_DATA_R);
394}
395
396static void
397chipsMmioWriteMiscOut(vgaHWPtr hwp, CARD8 value)
398{
399    moutb(CHIPS_MMIO_MISC_OUT_W, value);
400}
401
402static CARD8
403chipsMmioReadMiscOut(vgaHWPtr hwp)
404{
405    return minb(CHIPS_MMIO_MISC_OUT_R);
406}
407
408static void
409chipsMmioEnablePalette(vgaHWPtr hwp)
410{
411    if (hwp->IOBase == VGA_IOBASE_MONO)
412	(void) minb(CHIPS_MMIO_MONO_STAT_1);
413    else
414	(void) minb(CHIPS_MMIO_COLOR_STAT_1);
415    moutb(CHIPS_MMIO_ATTR_INDEX, 0x00);
416    hwp->paletteEnabled = TRUE;
417}
418
419static void
420chipsMmioDisablePalette(vgaHWPtr hwp)
421{
422    if (hwp->IOBase == VGA_IOBASE_MONO)
423	(void) minb(CHIPS_MMIO_MONO_STAT_1);
424    else
425	(void) minb(CHIPS_MMIO_COLOR_STAT_1);
426    moutb(CHIPS_MMIO_ATTR_INDEX, 0x20);
427    hwp->paletteEnabled = FALSE;
428}
429
430static void
431chipsMmioWriteDacMask(vgaHWPtr hwp, CARD8 value)
432{
433    moutb(CHIPS_MMIO_DAC_MASK, value);
434}
435
436static CARD8
437chipsMmioReadDacMask(vgaHWPtr hwp)
438{
439    return minb(CHIPS_MMIO_DAC_MASK);
440}
441
442static void
443chipsMmioWriteDacReadAddr(vgaHWPtr hwp, CARD8 value)
444{
445    moutb(CHIPS_MMIO_DAC_READ_ADDR, value);
446}
447
448static void
449chipsMmioWriteDacWriteAddr(vgaHWPtr hwp, CARD8 value)
450{
451    moutb(CHIPS_MMIO_DAC_WRITE_ADDR, value);
452}
453
454static void
455chipsMmioWriteDacData(vgaHWPtr hwp, CARD8 value)
456{
457    moutb(CHIPS_MMIO_DAC_DATA, value);
458}
459
460static CARD8
461chipsMmioReadDacData(vgaHWPtr hwp)
462{
463    return minb(CHIPS_MMIO_DAC_DATA);
464}
465
466static CARD8
467chipsMmioReadST00(vgaHWPtr hwp)
468{
469    return minb(CHIPS_MMIO_STAT_0);
470}
471
472static CARD8
473chipsMmioReadST01(vgaHWPtr hwp)
474{
475    if (hwp->IOBase == VGA_IOBASE_MONO)
476	return minb(CHIPS_MMIO_MONO_STAT_1);
477    else
478	return minb(CHIPS_MMIO_COLOR_STAT_1);
479}
480
481static CARD8
482chipsMmioReadFCR(vgaHWPtr hwp)
483{
484    return minb(CHIPS_MMIO_FEATURE_R);
485}
486
487static void
488chipsMmioWriteFCR(vgaHWPtr hwp, CARD8 value)
489{
490    if (hwp->IOBase == VGA_IOBASE_MONO) {
491    	moutb(CHIPS_MMIO_MONO_STAT_1, value);
492    } else {
493    	moutb(CHIPS_MMIO_COLOR_STAT_1, value);
494    }
495}
496
497void
498CHIPSHWSetMmioFuncs(ScrnInfoPtr pScrn, CARD8 *base, int offset)
499{
500    vgaHWPtr hwp = VGAHWPTR(pScrn);
501
502    hwp->writeCrtc		= chipsMmioWriteCrtc;
503    hwp->readCrtc		= chipsMmioReadCrtc;
504    hwp->writeGr		= chipsMmioWriteGr;
505    hwp->readGr			= chipsMmioReadGr;
506    hwp->writeAttr		= chipsMmioWriteAttr;
507    hwp->readAttr		= chipsMmioReadAttr;
508    hwp->writeSeq		= chipsMmioWriteSeq;
509    hwp->readSeq		= chipsMmioReadSeq;
510    hwp->writeMiscOut		= chipsMmioWriteMiscOut;
511    hwp->readMiscOut		= chipsMmioReadMiscOut;
512    hwp->enablePalette		= chipsMmioEnablePalette;
513    hwp->disablePalette		= chipsMmioDisablePalette;
514    hwp->writeDacMask		= chipsMmioWriteDacMask;
515    hwp->readDacMask		= chipsMmioReadDacMask;
516    hwp->writeDacWriteAddr	= chipsMmioWriteDacWriteAddr;
517    hwp->writeDacReadAddr	= chipsMmioWriteDacReadAddr;
518    hwp->writeDacData		= chipsMmioWriteDacData;
519    hwp->readDacData		= chipsMmioReadDacData;
520    hwp->readST00               = chipsMmioReadST00;
521    hwp->readST01               = chipsMmioReadST01;
522    hwp->readFCR               = chipsMmioReadFCR;
523    hwp->writeFCR              = chipsMmioWriteFCR;
524    hwp->MMIOBase		= base;
525    hwp->MMIOOffset		= offset;
526}
527
528
529
530
531