176888252Smrg/*
276888252Smrg * Common strutures and function for CL-GD546x -- The Laguna family
376888252Smrg *
476888252Smrg * lg.h
576888252Smrg *
676888252Smrg * (c) 1998 Corin Anderson.
776888252Smrg *          corina@the4cs.com
876888252Smrg *          Tukwila, WA
976888252Smrg *
1076888252Smrg *  Inspired by cir.h
1176888252Smrg */
1276888252Smrg
1376888252Smrg#ifndef LG_H
1476888252Smrg#define LG_H
1576888252Smrg#define LG_DEBUG
1676888252Smrg
1776888252Smrgextern ScrnInfoPtr LgProbe(int entity);
1876888252Smrgextern const OptionInfoRec *	LgAvailableOptions(int chipid);
1976888252Smrg
2076888252Smrg# ifdef _LG_PRIVATE_
2176888252Smrg
2276888252Smrg/* Saved registers that are not part of the core VGA */
2376888252Smrg/* CRTC >= 0x19; Sequencer >= 0x05; Graphics >= 0x09; Attribute >= 0x15 */
2476888252Smrg	/* CR regs */
2576888252Smrgenum {
2676888252Smrg	/* CR regs */
2776888252Smrg	CR1A,
2876888252Smrg	CR1B,
2976888252Smrg	CR1D,
3076888252Smrg	CR1E,
3176888252Smrg	/* SR regs */
3276888252Smrg	SR07,
3376888252Smrg	SR0E,
3476888252Smrg	SR1E,
3576888252Smrg	/* Must be last! */
3676888252Smrg	LG_LAST_REG
3776888252Smrg};
3876888252Smrg
3976888252Smrg#undef FORMAT
4076888252Smrg
4176888252Smrgtypedef struct {
4276888252Smrg	unsigned char ExtVga[LG_LAST_REG];
4376888252Smrg
4476888252Smrg	/* Laguna regs */
4576888252Smrg	CARD8 TILE, BCLK;
4676888252Smrg	CARD16 FORMAT, DTTC, TileCtrl, CONTROL;
470814a2baSmrg	CARD16 RIFCtrl, RACCtrl;
4876888252Smrg	CARD32 VSC;
4976888252Smrg} LgRegRec, *LgRegPtr;
5076888252Smrg
5176888252Smrgtypedef struct {
5276888252Smrg	int tilesPerLine;	/* Number of tiles per line */
5376888252Smrg	int pitch;			/* Display pitch, in bytes */
5476888252Smrg	int width;			/* Tile width.  0 = 128 byte  1 = 256 byte */
5576888252Smrg} LgLineDataRec, *LgLineDataPtr;
5676888252Smrg
5776888252Smrg
5876888252Smrg/* lg_driver.c */
5976888252Smrgextern LgLineDataRec LgLineData[];
6076888252Smrg
6163847c39Smrg#ifdef HAVE_XAA_H
6276888252Smrg/* lg_xaa.c */
6376888252Smrgextern Bool LgXAAInit(ScreenPtr pScreen);
6463847c39Smrg#endif
6576888252Smrg
6676888252Smrg/* lg_hwcurs.c */
6776888252Smrgextern Bool LgHWCursorInit(ScreenPtr pScreen);
6876888252Smrgextern void LgHideCursor(ScrnInfoPtr pScrn);
6976888252Smrgextern void LgShowCursor(ScrnInfoPtr pScrn);
7076888252Smrg
7176888252Smrg/* lg_i2c.c */
7276888252Smrgextern Bool LgI2CInit(ScrnInfoPtr pScrn);
7376888252Smrg
7476888252Smrg#define memrb(off) MMIO_IN8(pCir->IOBase,off)
7576888252Smrg#define memrw(off) MMIO_IN16(pCir->IOBase,off)
7676888252Smrg#define memrl(off) MMIO_IN32(pCir->IOBase,off)
7776888252Smrg#define memwb(off,val) MMIO_OUT8(pCir->IOBase,off,val)
7876888252Smrg#define memww(off,val) MMIO_OUT16(pCir->IOBase,off,val)
7976888252Smrg#define memwl(off,val) MMIO_OUT32(pCir->IOBase,off,val)
8076888252Smrg
8176888252Smrg/* Card-specific driver information */
8276888252Smrg#define LGPTR(p) ((LgPtr)((p)->chip.lg))
8376888252Smrg
8476888252Smrgtypedef struct lgRec {
8576888252Smrg	CARD32		HWCursorAddr;
8676888252Smrg	int			HWCursorImageX;
8776888252Smrg	int			HWCursorImageY;
8876888252Smrg	int			HWCursorTileWidth;
8976888252Smrg	int			HWCursorTileHeight;
9076888252Smrg
9176888252Smrg	int			lineDataIndex;
9276888252Smrg
9376888252Smrg	int			memInterleave;
9476888252Smrg
9576888252Smrg	LgRegRec	SavedReg;
9676888252Smrg	LgRegRec	ModeReg;
9776888252Smrg
9876888252Smrg	CARD32		oldBitmask;
9976888252Smrg	Bool		blitTransparent;
10076888252Smrg	int			blitYDir;
10176888252Smrg} LgRec, *LgPtr;
10276888252Smrg
10376888252Smrg# endif /* _LG_PRIVATE_ */
10476888252Smrg#endif /* LG_H */
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