1f29dbc25Smrg/* Copyright (c) 2005 Advanced Micro Devices, Inc. 2f29dbc25Smrg * 3f29dbc25Smrg * Permission is hereby granted, free of charge, to any person obtaining a copy 4f29dbc25Smrg * of this software and associated documentation files (the "Software"), to 5f29dbc25Smrg * deal in the Software without restriction, including without limitation the 6f29dbc25Smrg * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 7f29dbc25Smrg * sell copies of the Software, and to permit persons to whom the Software is 8f29dbc25Smrg * furnished to do so, subject to the following conditions: 9f29dbc25Smrg * 10f29dbc25Smrg * The above copyright notice and this permission notice shall be included in 11f29dbc25Smrg * all copies or substantial portions of the Software. 12f29dbc25Smrg * 13f29dbc25Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14f29dbc25Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15f29dbc25Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16f29dbc25Smrg * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17f29dbc25Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 18f29dbc25Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 19f29dbc25Smrg * IN THE SOFTWARE. 20f29dbc25Smrg * 21f29dbc25Smrg * Neither the name of the Advanced Micro Devices, Inc. nor the names of its 22f29dbc25Smrg * contributors may be used to endorse or promote products derived from this 23f29dbc25Smrg * software without specific prior written permission. 24f29dbc25Smrg * */ 25f29dbc25Smrg 26f29dbc25Smrg/* 27f29dbc25Smrg * This header file contains the mode tables. It is used by the "gfx_disp.c" 28f29dbc25Smrg * file to set a display mode. 29f29dbc25Smrg * */ 30f29dbc25Smrg 31f29dbc25Smrg#ifndef _gfx_mode_h 32f29dbc25Smrg#define _gfx_mode_h 33f29dbc25Smrg 34f29dbc25Smrg/* MODE FLAGS (BITWISE-OR) */ 35f29dbc25Smrg 36f29dbc25Smrg#define GFX_MODE_8BPP 0x00000001 37f29dbc25Smrg#define GFX_MODE_12BPP 0x00000002 38f29dbc25Smrg#define GFX_MODE_15BPP 0x00000004 39f29dbc25Smrg#define GFX_MODE_16BPP 0x00000008 40f29dbc25Smrg#define GFX_MODE_24BPP 0x00000010 41f29dbc25Smrg#define GFX_MODE_56HZ 0x00000020 42f29dbc25Smrg#define GFX_MODE_60HZ 0x00000040 43f29dbc25Smrg#define GFX_MODE_70HZ 0x00000080 44f29dbc25Smrg#define GFX_MODE_72HZ 0x00000100 45f29dbc25Smrg#define GFX_MODE_75HZ 0x00000200 46f29dbc25Smrg#define GFX_MODE_85HZ 0x00000400 47f29dbc25Smrg#define GFX_MODE_90HZ 0x00000800 48f29dbc25Smrg#define GFX_MODE_100HZ 0x00001000 49f29dbc25Smrg#define GFX_MODE_NEG_HSYNC 0x00002000 50f29dbc25Smrg#define GFX_MODE_NEG_VSYNC 0x00004000 51f29dbc25Smrg#define GFX_MODE_PIXEL_DOUBLE 0x00008000 52f29dbc25Smrg#define GFX_MODE_LINE_DOUBLE 0x00010000 53f29dbc25Smrg#define GFX_MODE_TV_NTSC 0x00020000 54f29dbc25Smrg#define GFX_MODE_TV_PAL 0x00040000 55f29dbc25Smrg#define GFX_MODE_EXCLUDE_PLL 0x00080000 56f29dbc25Smrg#define GFX_MODE_LOCK_TIMING 0x10000000 57f29dbc25Smrg 58f29dbc25Smrg#define gfx_mode_hz_conversion \ 59f29dbc25Smrg switch (hz) { \ 60f29dbc25Smrg case 56: \ 61f29dbc25Smrg hz_flag = GFX_MODE_56HZ; \ 62f29dbc25Smrg break; \ 63f29dbc25Smrg case 60: \ 64f29dbc25Smrg hz_flag = GFX_MODE_60HZ; \ 65f29dbc25Smrg break; \ 66f29dbc25Smrg case 70: \ 67f29dbc25Smrg hz_flag = GFX_MODE_70HZ; \ 68f29dbc25Smrg break; \ 69f29dbc25Smrg case 72: \ 70f29dbc25Smrg hz_flag = GFX_MODE_72HZ; \ 71f29dbc25Smrg break; \ 72f29dbc25Smrg case 75: \ 73f29dbc25Smrg hz_flag = GFX_MODE_75HZ; \ 74f29dbc25Smrg break; \ 75f29dbc25Smrg case 85: \ 76f29dbc25Smrg hz_flag = GFX_MODE_85HZ; \ 77f29dbc25Smrg break; \ 78f29dbc25Smrg case 90: \ 79f29dbc25Smrg hz_flag = GFX_MODE_90HZ; \ 80f29dbc25Smrg break; \ 81f29dbc25Smrg case 100: \ 82f29dbc25Smrg hz_flag = GFX_MODE_100HZ; \ 83f29dbc25Smrg break; \ 84f29dbc25Smrg } 85f29dbc25Smrg 86f29dbc25Smrg#define gfx_mode_bpp_conversion \ 87f29dbc25Smrg switch (bpp) { \ 88f29dbc25Smrg case 8: \ 89f29dbc25Smrg bpp_flag = GFX_MODE_8BPP; \ 90f29dbc25Smrg break; \ 91f29dbc25Smrg case 12: \ 92f29dbc25Smrg bpp_flag = GFX_MODE_12BPP; \ 93f29dbc25Smrg break; \ 94f29dbc25Smrg case 15: \ 95f29dbc25Smrg bpp_flag = GFX_MODE_15BPP; \ 96f29dbc25Smrg break; \ 97f29dbc25Smrg case 16: \ 98f29dbc25Smrg bpp_flag = GFX_MODE_16BPP; \ 99f29dbc25Smrg break; \ 100f29dbc25Smrg case 32: \ 101f29dbc25Smrg bpp_flag = GFX_MODE_24BPP; \ 102f29dbc25Smrg break; \ 103f29dbc25Smrg default: \ 104f29dbc25Smrg return -1; \ 105f29dbc25Smrg } 106f29dbc25Smrg 107f29dbc25Smrg#define gfx_mode_bpp_conversion_def(bpp) \ 108f29dbc25Smrg switch (bpp) { \ 109f29dbc25Smrg case 8: \ 110f29dbc25Smrg bpp_flag = GFX_MODE_8BPP; \ 111f29dbc25Smrg break; \ 112f29dbc25Smrg case 12: \ 113f29dbc25Smrg bpp_flag = GFX_MODE_12BPP; \ 114f29dbc25Smrg break; \ 115f29dbc25Smrg case 15: \ 116f29dbc25Smrg bpp_flag = GFX_MODE_15BPP; \ 117f29dbc25Smrg break; \ 118f29dbc25Smrg case 16: \ 119f29dbc25Smrg bpp_flag = GFX_MODE_16BPP; \ 120f29dbc25Smrg break; \ 121f29dbc25Smrg case 32: \ 122f29dbc25Smrg bpp_flag = GFX_MODE_24BPP; \ 123f29dbc25Smrg break; \ 124f29dbc25Smrg default: \ 125f29dbc25Smrg bpp_flag = GFX_MODE_8BPP; \ 126f29dbc25Smrg } 127f29dbc25Smrg 128f29dbc25Smrg/* STRUCTURE DEFINITION */ 129f29dbc25Smrg 13004007ebaSmrgtypedef struct tagDISPLAYMODE { 131f29dbc25Smrg /* DISPLAY MODE FLAGS */ 132f29dbc25Smrg /* Specify valid color depths and the refresh rate. */ 133f29dbc25Smrg 134f29dbc25Smrg unsigned long flags; 135f29dbc25Smrg 136f29dbc25Smrg /* TIMINGS */ 137f29dbc25Smrg 138f29dbc25Smrg unsigned short hactive; 139f29dbc25Smrg unsigned short hblankstart; 140f29dbc25Smrg unsigned short hsyncstart; 141f29dbc25Smrg unsigned short hsyncend; 142f29dbc25Smrg unsigned short hblankend; 143f29dbc25Smrg unsigned short htotal; 144f29dbc25Smrg 145f29dbc25Smrg unsigned short vactive; 146f29dbc25Smrg unsigned short vblankstart; 147f29dbc25Smrg unsigned short vsyncstart; 148f29dbc25Smrg unsigned short vsyncend; 149f29dbc25Smrg unsigned short vblankend; 150f29dbc25Smrg unsigned short vtotal; 151f29dbc25Smrg 152f29dbc25Smrg /* CLOCK FREQUENCY */ 153f29dbc25Smrg 154f29dbc25Smrg unsigned long frequency; 155f29dbc25Smrg 156f29dbc25Smrg} DISPLAYMODE; 157f29dbc25Smrg 158f29dbc25Smrg/* For Fixed timings */ 15904007ebaSmrgtypedef struct tagFIXEDTIMINGS { 160f29dbc25Smrg /* DISPLAY MODE FLAGS */ 161f29dbc25Smrg /* Specify valid color depths and the refresh rate. */ 162f29dbc25Smrg 163f29dbc25Smrg int panelresx; 164f29dbc25Smrg int panelresy; 165f29dbc25Smrg unsigned short xres; 166f29dbc25Smrg unsigned short yres; 167f29dbc25Smrg 168f29dbc25Smrg /* TIMINGS */ 169f29dbc25Smrg 170f29dbc25Smrg unsigned short hactive; 171f29dbc25Smrg unsigned short hblankstart; 172f29dbc25Smrg unsigned short hsyncstart; 173f29dbc25Smrg unsigned short hsyncend; 174f29dbc25Smrg unsigned short hblankend; 175f29dbc25Smrg unsigned short htotal; 176f29dbc25Smrg 177f29dbc25Smrg unsigned short vactive; 178f29dbc25Smrg unsigned short vblankstart; 179f29dbc25Smrg unsigned short vsyncstart; 180f29dbc25Smrg unsigned short vsyncend; 181f29dbc25Smrg unsigned short vblankend; 182f29dbc25Smrg unsigned short vtotal; 183f29dbc25Smrg 184f29dbc25Smrg /* CLOCK FREQUENCY */ 185f29dbc25Smrg 186f29dbc25Smrg unsigned long frequency; 187f29dbc25Smrg 188f29dbc25Smrg} FIXEDTIMINGS; 189f29dbc25Smrg 19004007ebaSmrg#endif /* !_gfx_mode_h */ 191f29dbc25Smrg 192f29dbc25Smrg/* END OF FILE */ 193