1f29dbc25Smrg/* Copyright (c) 2005 Advanced Micro Devices, Inc. 2f29dbc25Smrg * 3f29dbc25Smrg * Permission is hereby granted, free of charge, to any person obtaining a copy 4f29dbc25Smrg * of this software and associated documentation files (the "Software"), to 5f29dbc25Smrg * deal in the Software without restriction, including without limitation the 6f29dbc25Smrg * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 7f29dbc25Smrg * sell copies of the Software, and to permit persons to whom the Software is 8f29dbc25Smrg * furnished to do so, subject to the following conditions: 9f29dbc25Smrg * 10f29dbc25Smrg * The above copyright notice and this permission notice shall be included in 11f29dbc25Smrg * all copies or substantial portions of the Software. 12f29dbc25Smrg * 13f29dbc25Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14f29dbc25Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15f29dbc25Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16f29dbc25Smrg * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17f29dbc25Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 18f29dbc25Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 19f29dbc25Smrg * IN THE SOFTWARE. 20f29dbc25Smrg * 21f29dbc25Smrg * Neither the name of the Advanced Micro Devices, Inc. nor the names of its 22f29dbc25Smrg * contributors may be used to endorse or promote products derived from this 23f29dbc25Smrg * software without specific prior written permission. 24f29dbc25Smrg * */ 25f29dbc25Smrg 26f29dbc25Smrg/* 27f29dbc25Smrg * This file contains routines used in the initialization of Geode-family 28f29dbc25Smrg * processors. 29f29dbc25Smrg * */ 30f29dbc25Smrg 31f29dbc25Smrg/*---------------------------------------------------------------------------- 32f29dbc25Smrg * gfx_gxm_config_read 33f29dbc25Smrg * 34f29dbc25Smrg * This routine reads the value of the specified GXm configuration register. 35f29dbc25Smrg *---------------------------------------------------------------------------- 36f29dbc25Smrg */ 37f29dbc25Smrgunsigned char 38f29dbc25Smrggfx_gxm_config_read(unsigned char index) 39f29dbc25Smrg{ 40f29dbc25Smrg unsigned char value = 0xFF; 41f29dbc25Smrg unsigned char lock; 42f29dbc25Smrg 43f29dbc25Smrg OUTB(0x22, GXM_CONFIG_CCR3); 44f29dbc25Smrg lock = INB(0x23); 45f29dbc25Smrg OUTB(0x22, GXM_CONFIG_CCR3); 4604007ebaSmrg OUTB(0x23, (unsigned char) (lock | 0x10)); 47f29dbc25Smrg OUTB(0x22, index); 48f29dbc25Smrg value = INB(0x23); 49f29dbc25Smrg OUTB(0x22, GXM_CONFIG_CCR3); 50f29dbc25Smrg OUTB(0x23, lock); 51f29dbc25Smrg return (value); 52f29dbc25Smrg} 53f29dbc25Smrg 54f29dbc25Smrg/*---------------------------------------------------------------------------- 55f29dbc25Smrg * gfx_get_core_freq 56f29dbc25Smrg * 57f29dbc25Smrg * This routine returns the core clock frequency of a GXm if valid jumper 58f29dbc25Smrg * settings are detected; 0 It assumes that a 33.3 MHz PCI clock is being used 59f29dbc25Smrg * for GX1. 60f29dbc25Smrg * For SCx2xx, the fast PCI divisor is read. 61f29dbc25Smrg *---------------------------------------------------------------------------- 62f29dbc25Smrg */ 63f29dbc25Smrg#if GFX_INIT_DYNAMIC 64f29dbc25Smrgunsigned long 65f29dbc25Smrggu1_get_core_freq(void) 66f29dbc25Smrg#else 67f29dbc25Smrgunsigned long 68f29dbc25Smrggfx_get_core_freq(void) 69f29dbc25Smrg#endif 70f29dbc25Smrg{ 71f29dbc25Smrg unsigned char dir0, dir1; 72f29dbc25Smrg unsigned long cpu_speed; 73f29dbc25Smrg 74f29dbc25Smrg dir0 = gfx_gxm_config_read(GXM_CONFIG_DIR0) & 0x0F; 75f29dbc25Smrg dir1 = gfx_gxm_config_read(GXM_CONFIG_DIR1); 76f29dbc25Smrg 77f29dbc25Smrg /* REVISION 4.0 AND UP */ 78f29dbc25Smrg 79f29dbc25Smrg if (dir1 >= 0x50) { 80f29dbc25Smrg switch (dir0) { 81f29dbc25Smrg case 0: 82f29dbc25Smrg case 2: 83f29dbc25Smrg cpu_speed = 133; 84f29dbc25Smrg break; 85f29dbc25Smrg case 5: 86f29dbc25Smrg cpu_speed = 166; 87f29dbc25Smrg break; 88f29dbc25Smrg case 3: 89f29dbc25Smrg cpu_speed = 200; 90f29dbc25Smrg break; 91f29dbc25Smrg case 6: 92f29dbc25Smrg cpu_speed = 233; 93f29dbc25Smrg break; 94f29dbc25Smrg case 7: 95f29dbc25Smrg cpu_speed = 266; 96f29dbc25Smrg break; 97f29dbc25Smrg case 4: 98f29dbc25Smrg cpu_speed = 300; 99f29dbc25Smrg break; 100f29dbc25Smrg case 1: 101f29dbc25Smrg cpu_speed = 333; 102f29dbc25Smrg break; 103f29dbc25Smrg default: 104f29dbc25Smrg return (0); 105f29dbc25Smrg } 10604007ebaSmrg } 10704007ebaSmrg else { 108f29dbc25Smrg switch (dir0) { 109f29dbc25Smrg case 0: 110f29dbc25Smrg case 2: 111f29dbc25Smrg cpu_speed = 133; 112f29dbc25Smrg break; 113f29dbc25Smrg case 7: 114f29dbc25Smrg cpu_speed = 166; 115f29dbc25Smrg break; 116f29dbc25Smrg case 1: 117f29dbc25Smrg case 3: 118f29dbc25Smrg cpu_speed = 200; 119f29dbc25Smrg break; 120f29dbc25Smrg case 4: 121f29dbc25Smrg case 6: 122f29dbc25Smrg cpu_speed = 233; 123f29dbc25Smrg break; 124f29dbc25Smrg case 5: 125f29dbc25Smrg cpu_speed = 266; 126f29dbc25Smrg break; 127f29dbc25Smrg default: 128f29dbc25Smrg return (0); 129f29dbc25Smrg } 130f29dbc25Smrg } 131f29dbc25Smrg 132f29dbc25Smrg if ((gfx_cpu_version & 0xFF) == GFX_CPU_SC1200) { 133f29dbc25Smrg cpu_speed = (cpu_speed * gfx_pci_speed_khz) / 33300; 134f29dbc25Smrg } 135f29dbc25Smrg return (cpu_speed); 136f29dbc25Smrg} 137f29dbc25Smrg 138f29dbc25Smrg/*---------------------------------------------------------------------------- 139f29dbc25Smrg * gfx_get_cpu_register_base 140f29dbc25Smrg * 141f29dbc25Smrg * This routine returns the base address for graphics registers. 142f29dbc25Smrg *---------------------------------------------------------------------------- 143f29dbc25Smrg */ 144f29dbc25Smrg#if GFX_INIT_DYNAMIC 145f29dbc25Smrgunsigned long 146f29dbc25Smrggu1_get_cpu_register_base(void) 147f29dbc25Smrg#else 148f29dbc25Smrgunsigned long 149f29dbc25Smrggfx_get_cpu_register_base(void) 150f29dbc25Smrg#endif 151f29dbc25Smrg{ 152f29dbc25Smrg unsigned long base; 153f29dbc25Smrg 15404007ebaSmrg base = (unsigned long) gfx_gxm_config_read(GXM_CONFIG_GCR); 155f29dbc25Smrg base = (base & 0x03) << 30; 156f29dbc25Smrg return (base); 157f29dbc25Smrg} 158f29dbc25Smrg 159f29dbc25Smrg/*---------------------------------------------------------------------------- 160f29dbc25Smrg * gfx_get_frame_buffer_base 161f29dbc25Smrg * 162f29dbc25Smrg * This routine returns the base address for graphics memory. This is an 163f29dbc25Smrg * offset of 0x00800000 from the base address specified in the GCR register. 164f29dbc25Smrg * 165f29dbc25Smrg * The function returns zero if the GCR indicates the graphics subsystem 166f29dbc25Smrg * is disabled. 167f29dbc25Smrg *---------------------------------------------------------------------------- 168f29dbc25Smrg */ 169f29dbc25Smrg#if GFX_INIT_DYNAMIC 170f29dbc25Smrgunsigned long 171f29dbc25Smrggu1_get_frame_buffer_base(void) 172f29dbc25Smrg#else 173f29dbc25Smrgunsigned long 174f29dbc25Smrggfx_get_frame_buffer_base(void) 175f29dbc25Smrg#endif 176f29dbc25Smrg{ 177f29dbc25Smrg unsigned long base; 178f29dbc25Smrg 17904007ebaSmrg base = (unsigned long) gfx_gxm_config_read(GXM_CONFIG_GCR); 180f29dbc25Smrg base = (base & 0x03) << 30; 181f29dbc25Smrg if (base) 182f29dbc25Smrg base |= 0x00800000; 183f29dbc25Smrg return (base); 184f29dbc25Smrg} 185f29dbc25Smrg 186f29dbc25Smrg/*---------------------------------------------------------------------------- 187f29dbc25Smrg * gfx_get_frame_buffer_size 188f29dbc25Smrg * 189f29dbc25Smrg * This routine returns the total size of graphics memory, in bytes. 190f29dbc25Smrg * 191f29dbc25Smrg * Currently this routine is hardcoded to return 2 Meg. 192f29dbc25Smrg *---------------------------------------------------------------------------- 193f29dbc25Smrg */ 194f29dbc25Smrg#if GFX_INIT_DYNAMIC 195f29dbc25Smrgunsigned long 196f29dbc25Smrggu1_get_frame_buffer_size(void) 197f29dbc25Smrg#else 198f29dbc25Smrgunsigned long 199f29dbc25Smrggfx_get_frame_buffer_size(void) 200f29dbc25Smrg#endif 201f29dbc25Smrg{ 202f29dbc25Smrg#if FB4MB 203f29dbc25Smrg return (0x00400000); 204f29dbc25Smrg#else 205f29dbc25Smrg return (0x00200000); 206f29dbc25Smrg#endif 207f29dbc25Smrg} 208f29dbc25Smrg 209f29dbc25Smrg/*---------------------------------------------------------------------------- 210f29dbc25Smrg * gfx_get_vid_register_base 211f29dbc25Smrg * 212f29dbc25Smrg * This routine returns the base address for the video hardware. It assumes 213f29dbc25Smrg * an offset of 0x00010000 from the base address specified by the GCR. 214f29dbc25Smrg * 215f29dbc25Smrg * The function returns zero if the GCR indicates the graphics subsystem 216f29dbc25Smrg * is disabled. 217f29dbc25Smrg *---------------------------------------------------------------------------- 218f29dbc25Smrg */ 219f29dbc25Smrg#if GFX_INIT_DYNAMIC 220f29dbc25Smrgunsigned long 221f29dbc25Smrggu1_get_vid_register_base(void) 222f29dbc25Smrg#else 223f29dbc25Smrgunsigned long 224f29dbc25Smrggfx_get_vid_register_base(void) 225f29dbc25Smrg#endif 226f29dbc25Smrg{ 227f29dbc25Smrg unsigned long base; 228f29dbc25Smrg 22904007ebaSmrg base = (unsigned long) gfx_gxm_config_read(GXM_CONFIG_GCR); 230f29dbc25Smrg base = (base & 0x03) << 30; 231f29dbc25Smrg if (base) 232f29dbc25Smrg base |= 0x00010000; 233f29dbc25Smrg return (base); 234f29dbc25Smrg} 235f29dbc25Smrg 236f29dbc25Smrg/*---------------------------------------------------------------------------- 237f29dbc25Smrg * gfx_get_vip_register_base 238f29dbc25Smrg * 239f29dbc25Smrg * This routine returns the base address for the VIP hardware. This is 240f29dbc25Smrg * only applicable to the SC1200, for which this routine assumes an offset 241f29dbc25Smrg * of 0x00015000 from the base address specified by the GCR. 242f29dbc25Smrg * 243f29dbc25Smrg * The function returns zero if the GCR indicates the graphics subsystem 244f29dbc25Smrg * is disabled. 245f29dbc25Smrg *---------------------------------------------------------------------------- 246f29dbc25Smrg */ 247f29dbc25Smrg#if GFX_INIT_DYNAMIC 248f29dbc25Smrgunsigned long 249f29dbc25Smrggu1_get_vip_register_base(void) 250f29dbc25Smrg#else 251f29dbc25Smrgunsigned long 252f29dbc25Smrggfx_get_vip_register_base(void) 253f29dbc25Smrg#endif 254f29dbc25Smrg{ 255f29dbc25Smrg unsigned long base = 0; 256f29dbc25Smrg 257f29dbc25Smrg if ((gfx_cpu_version & 0xFF) == GFX_CPU_SC1200) { 25804007ebaSmrg base = (unsigned long) gfx_gxm_config_read(GXM_CONFIG_GCR); 259f29dbc25Smrg base = (base & 0x03) << 30; 260f29dbc25Smrg if (base) 261f29dbc25Smrg base |= 0x00015000; 262f29dbc25Smrg } 263f29dbc25Smrg return (base); 264f29dbc25Smrg} 265f29dbc25Smrg 266f29dbc25Smrg/* END OF FILE */ 267