1c35d236eSmrg/*
2c35d236eSmrg * glint register file
3c35d236eSmrg *
4c35d236eSmrg * Copyright by Stefan Dirsch, Dirk Hohndel, Alan Hourihane
5c35d236eSmrg * Authors: Alan Hourihane, <alanh@fairlite.demon.co.uk>
6c35d236eSmrg *          Dirk Hohndel, <hohndel@suse.de>
7c35d236eSmrg *          Stefan Dirsch, <sndirsch@suse.de>
8c35d236eSmrg *          Simon P., <sim@suse.de>
9c35d236eSmrg *
10c35d236eSmrg * this work is sponsored by S.u.S.E. GmbH, Fuerth, Elsa GmbH, Aachen and
11c35d236eSmrg * Siemens Nixdorf Informationssysteme
12c35d236eSmrg *
13c35d236eSmrg */
14c35d236eSmrg
15c35d236eSmrg#ifndef _GLINTREG_H_
16c35d236eSmrg#define _GLINTREG_H_
17c35d236eSmrg
18c35d236eSmrg#include "compiler.h"
19c35d236eSmrg
20c35d236eSmrg/* The chips we know */
21c35d236eSmrg#define PCI_CHIP_3DLABS_300SX					0x01
22c35d236eSmrg#define PCI_CHIP_3DLABS_500TX					0x02
23c35d236eSmrg#define PCI_CHIP_3DLABS_DELTA					0x03
24c35d236eSmrg#define PCI_CHIP_3DLABS_PERMEDIA				0x04
25c35d236eSmrg#define PCI_CHIP_3DLABS_MX					0x06
26c35d236eSmrg#define PCI_CHIP_3DLABS_PERMEDIA2				0x07
27c35d236eSmrg#define PCI_CHIP_3DLABS_GAMMA					0x08
28c35d236eSmrg#define PCI_CHIP_3DLABS_PERMEDIA2V				0x09
29c35d236eSmrg#define PCI_CHIP_3DLABS_PERMEDIA3				0x0A
30c35d236eSmrg#define PCI_CHIP_3DLABS_PERMEDIA4				0x0C
31c35d236eSmrg#define PCI_CHIP_3DLABS_R4					0x0D
32c35d236eSmrg#define PCI_CHIP_3DLABS_GAMMA2					0x0E
331fb744b4Smrg#define PCI_CHIP_3DLABS_R4ALT					0x11
341fb744b4Smrg
351fb744b4Smrg/* Texas Instruments */
361fb744b4Smrg#define PCI_CHIP_TI_PERMEDIA					0x3D04
371fb744b4Smrg#define PCI_CHIP_TI_PERMEDIA2					0x3D07
38c35d236eSmrg
39c35d236eSmrg/* The boards we know */
404f6cd06fSmrg#define IS_GLORIAXXL	((PCI_SUB_VENDOR_ID(pGlint->PciInfo) == 0x1048) && \
414f6cd06fSmrg			 (PCI_SUB_DEVICE_ID(pGlint->PciInfo)   == 0x0a42))
42c35d236eSmrg
434f6cd06fSmrg#define IS_GLORIASYNERGY ((PCI_SUB_VENDOR_ID(pGlint->PciInfo) == 0x1048) && \
444f6cd06fSmrg			 (PCI_SUB_DEVICE_ID(pGlint->PciInfo)   == 0x0a32))
45c35d236eSmrg
464f6cd06fSmrg#define IS_GMX2000	((PCI_SUB_VENDOR_ID(pGlint->PciInfo) == 0x3d3d) && \
474f6cd06fSmrg			 (PCI_SUB_DEVICE_ID(pGlint->PciInfo)   == 0x0106))
48c35d236eSmrg
494f6cd06fSmrg#define IS_J2000	((PCI_SUB_VENDOR_ID(pGlint->PciInfo) == 0x1097) && \
504f6cd06fSmrg			 (PCI_SUB_DEVICE_ID(pGlint->PciInfo)   == 0x3d32))
51c35d236eSmrg
524f6cd06fSmrg#define IS_JPRO		((PCI_SUB_VENDOR_ID(pGlint->PciInfo) == 0x1097) && \
534f6cd06fSmrg			 (PCI_SUB_DEVICE_ID(pGlint->PciInfo)   == 0x3db3))
54c35d236eSmrg
55c35d236eSmrg/* COMPAQ OEM VX1 PCI
56c35d236eSmrg *   subsys == 0x0121 if VGA is enabled
57c35d236eSmrg *   subsys == 0x000a if VGA has never been enabled
58c35d236eSmrg */
594f6cd06fSmrg#define IS_PCI_QVX1	(PCI_SUB_VENDOR_ID(pGlint->PciInfo) == 0x3d3d &&  \
604f6cd06fSmrg                         ((PCI_SUB_DEVICE_ID(pGlint->PciInfo) == 0x0121) ||  \
614f6cd06fSmrg			  (PCI_SUB_DEVICE_ID(pGlint->PciInfo) == 0x000a)))
62c35d236eSmrg
63c35d236eSmrg/* COMPAQ OEM VX1 AGP
64c35d236eSmrg *   subsys == 0x0144 if VGA is enabled
65c35d236eSmrg *   subsys == 0x000c if VGA has never been enabled
66c35d236eSmrg */
674f6cd06fSmrg#define IS_AGP_QVX1	(PCI_SUB_VENDOR_ID(pGlint->PciInfo) == 0x3d3d &&  \
684f6cd06fSmrg			 ((PCI_SUB_DEVICE_ID(pGlint->PciInfo) == 0x0144) ||  \
694f6cd06fSmrg			  (PCI_SUB_DEVICE_ID(pGlint->PciInfo) == 0x000c)))
70c35d236eSmrg
71c35d236eSmrg#define IS_QVX1		(IS_PCI_QVX1 || IS_AGP_QVX1)
72c35d236eSmrg
734f6cd06fSmrg#define IS_ELSA_SYNERGY	((PCI_SUB_VENDOR_ID(pGlint->PciInfo) == 0x1048) && \
744f6cd06fSmrg			 (PCI_SUB_DEVICE_ID(pGlint->PciInfo)   == 0x0a32))
75c35d236eSmrg
76c35d236eSmrg/* COMPAQ OEM Permedia 2V with VGA disable jumper - 0x13e9 ? */
774f6cd06fSmrg#define IS_QPM2V	((PCI_SUB_VENDOR_ID(pGlint->PciInfo) == 0x13e9) && \
784f6cd06fSmrg			 ((PCI_SUB_DEVICE_ID(pGlint->PciInfo) == 0x0100) ||  \
794f6cd06fSmrg			  (PCI_SUB_DEVICE_ID(pGlint->PciInfo) == 0x0002)))
80c35d236eSmrg
81c35d236eSmrg/**********************************************
82c35d236eSmrg*  GLINT 500TX Configuration Region Registers *
83c35d236eSmrg***********************************************/
84c35d236eSmrg
85c35d236eSmrg/* Device Identification */
86c35d236eSmrg#define CFGVendorId						0x0000
87c35d236eSmrg#define PCI_VENDOR_3DLABS					0x3D3D
88c35d236eSmrg#define PCI_VENDOR_TI						0x104C
89c35d236eSmrg#define CFGDeviceId						0x0002
90c35d236eSmrg
91c35d236eSmrg#define CFGRevisionId						0x08
92c35d236eSmrg#define CFGClassCode						0x09
93c35d236eSmrg#define CFGHeaderType						0x0E
94c35d236eSmrg
95c35d236eSmrg/* Device Control/Status */
96c35d236eSmrg#define CFGCommand							0x04
97c35d236eSmrg#define CFGStatus							0x06
98c35d236eSmrg
99c35d236eSmrg/* Miscellaneous Functions */
100c35d236eSmrg#define CFGBist								0x0f
101c35d236eSmrg#define CFGLatTimer							0x0d
102c35d236eSmrg#define CFGCacheLine							0x0c
103c35d236eSmrg#define CFGMaxLat							0x3f
104c35d236eSmrg#define CFGMinGrant							0x3e
105c35d236eSmrg#define CFGIntPin							0x3d
106c35d236eSmrg#define CFGIntLine							0x3c
107c35d236eSmrg
108c35d236eSmrg/* Base Adresses */
109c35d236eSmrg#define CFGBaseAddr0							0x10
110c35d236eSmrg#define CFGBaseAddr1							0x14
111c35d236eSmrg#define CFGBaseAddr2							0x18
112c35d236eSmrg#define CFGBaseAddr3							0x1C
113c35d236eSmrg#define CFGBaseAddr4							0x20
114c35d236eSmrg#define CFGRomAddr							0x30
115c35d236eSmrg
116c35d236eSmrg
117c35d236eSmrg
118c35d236eSmrg/**********************************
119c35d236eSmrg * GLINT 500TX Region 0 Registers *
120c35d236eSmrg **********************************/
121c35d236eSmrg
122c35d236eSmrg/* Control Status Registers */
123c35d236eSmrg#define ResetStatus							0x0000
124c35d236eSmrg#define IntEnable							0x0008
125c35d236eSmrg#define IntFlags							0x0010
126c35d236eSmrg#define InFIFOSpace							0x0018
127c35d236eSmrg#define OutFIFOWords							0x0020
128c35d236eSmrg#define DMAAddress							0x0028
129c35d236eSmrg#define DMACount							0x0030
130c35d236eSmrg#define ErrorFlags							0x0038
131c35d236eSmrg#define VClkCtl								0x0040
132c35d236eSmrg#define TestRegister							0x0048
133c35d236eSmrg#define Aperture0							0x0050
134c35d236eSmrg#define Aperture1							0x0058
135c35d236eSmrg#define DMAControl							0x0060
136c35d236eSmrg#define FIFODis								0x0068
137c35d236eSmrg
138c35d236eSmrg/* GLINT PerMedia Region 0 additional Registers */
139c35d236eSmrg#define ChipConfig							0x0070
140c35d236eSmrg#define   SCLK_SEL_MASK		(3 << 10)
141c35d236eSmrg#define   SCLK_SEL_MCLK_HALF	(3 << 10)
142c35d236eSmrg#define ByDMAControl							0x00D8
143c35d236eSmrg
144c35d236eSmrg/* GLINT 500TX LocalBuffer Registers */
145c35d236eSmrg#define LBMemoryCtl							0x1000
146c35d236eSmrg#define   LBNumBanksMask	0x00000001
147c35d236eSmrg#define    LBNumBanks1		(0)
148c35d236eSmrg#define    LBNumBanks2		(1)
149c35d236eSmrg#define   LBPageSizeMask        0x00000006
150c35d236eSmrg#define    LBPageSize256	(0<<1)
151c35d236eSmrg#define    LBPageSize512	(1<<1)
152c35d236eSmrg#define    LBPageSize1024	(2<<1)
153c35d236eSmrg#define    LBPageSize2048	(3<<1)
154c35d236eSmrg#define   LBRASCASLowMask	0x00000018
155c35d236eSmrg#define    LBRASCASLow2		(0<<3)
156c35d236eSmrg#define    LBRASCASLow3		(1<<3)
157c35d236eSmrg#define    LBRASCASLow4		(2<<3)
158c35d236eSmrg#define    LBRASCASLow5		(3<<3)
159c35d236eSmrg#define   LBRASPrechargeMask	0x00000060
160c35d236eSmrg#define    LBRASPrecharge2	(0<<5)
161c35d236eSmrg#define    LBRASPrecharge3	(1<<5)
162c35d236eSmrg#define    LBRASPrecharge4	(2<<5)
163c35d236eSmrg#define    LBRASPrecharge5	(3<<5)
164c35d236eSmrg#define   LBCASLowMask		0x00000180
165c35d236eSmrg#define    LBCASLow1		(0<<7)
166c35d236eSmrg#define    LBCASLow2		(1<<7)
167c35d236eSmrg#define    LBCASLow3		(2<<7)
168c35d236eSmrg#define    LBCASLow4		(3<<7)
169c35d236eSmrg#define   LBPageModeMask	0x00000200
170c35d236eSmrg#define    LBPageModeEnabled	(0<<9)
171c35d236eSmrg#define    LBPageModeDisabled	(1<<9)
172c35d236eSmrg#define   LBRefreshCountMask    0x0003fc00
173c35d236eSmrg#define   LBRefreshCountShift   10
174c35d236eSmrg
175c35d236eSmrg#define LBMemoryEDO							0x1008
176c35d236eSmrg#define   LBEDOMask		0x00000001
177c35d236eSmrg#define    LBEDODisabled	(0)
178c35d236eSmrg#define    LBEDOEnabled		(1)
179c35d236eSmrg#define   LBEDOBankSizeMask	0x0000000e
180c35d236eSmrg#define    LBEDOBankSizeDiabled	(0<<1)
181c35d236eSmrg#define    LBEDOBankSize256K	(1<<1)
182c35d236eSmrg#define    LBEDOBankSize512K	(2<<1)
183c35d236eSmrg#define    LBEDOBankSize1M	(3<<1)
184c35d236eSmrg#define    LBEDOBankSize2M	(4<<1)
185c35d236eSmrg#define    LBEDOBankSize4M	(5<<1)
186c35d236eSmrg#define    LBEDOBankSize8M	(6<<1)
187c35d236eSmrg#define    LBEDOBankSize16M	(7<<1)
188c35d236eSmrg#define   LBTwoPageDetectorMask	0x00000010
189c35d236eSmrg#define    LBSinglePageDetector	(0<<4)
190c35d236eSmrg#define    LBTwoPageDetector	(1<<4)
191c35d236eSmrg
192c35d236eSmrg/* GLINT PerMedia Memory Control Registers */
193c35d236eSmrg#define PMReboot							0x1000
194c35d236eSmrg#define PMRomControl							0x1040
195c35d236eSmrg#define PMBootAddress							0x1080
196c35d236eSmrg#define PMMemConfig							0x10C0
197c35d236eSmrg#    define RowCharge8    1 << 10
198c35d236eSmrg#    define TimeRCD8      1 <<  7
199c35d236eSmrg#    define TimeRC8       0x6 << 3
200c35d236eSmrg#    define TimeRP8       1
201c35d236eSmrg#    define CAS3Latency8  0 << 16
202c35d236eSmrg#    define BootAdress8   0x10
203c35d236eSmrg#    define NumberBanks8  0x3 << 29
204c35d236eSmrg#    define RefreshCount8 0x41 << 21
205c35d236eSmrg#    define TimeRASMin8   1 << 13
206c35d236eSmrg#    define DeadCycle8    1 << 17
207c35d236eSmrg#    define BankDelay8    0 << 18
208c35d236eSmrg#    define Burst1Cycle8  1 << 31
209c35d236eSmrg#    define SDRAM8        0 << 4
210c35d236eSmrg
211c35d236eSmrg#    define RowCharge6    1 << 10
212c35d236eSmrg#    define TimeRCD6      1 <<  7
213c35d236eSmrg#    define TimeRC6       0x6 << 3
214c35d236eSmrg#    define TimeRP6       0x2
215c35d236eSmrg#    define CAS3Latency6  1 << 16
216c35d236eSmrg#    define BootAdress6   0x60
217c35d236eSmrg#    define NumberBanks6  0x2 << 29
218c35d236eSmrg#    define RefreshCount6 0x41 << 21
219c35d236eSmrg#    define TimeRASMin6   1 << 13
220c35d236eSmrg#    define DeadCycle6    1 << 17
221c35d236eSmrg#    define BankDelay6    0 << 18
222c35d236eSmrg#    define Burst1Cycle6  1 << 31
223c35d236eSmrg#    define SDRAM6        0 << 4
224c35d236eSmrg
225c35d236eSmrg#    define RowCharge4    0 << 10
226c35d236eSmrg#    define TimeRCD4      0 <<  7
227c35d236eSmrg#    define TimeRC4       0x4 << 3
228c35d236eSmrg#    define TimeRP4       1
229c35d236eSmrg#    define CAS3Latency4  0 << 16
230c35d236eSmrg#    define BootAdress4   0x10
231c35d236eSmrg#    define NumberBanks4  1 << 29
232c35d236eSmrg#    define RefreshCount4 0x30 << 21
233c35d236eSmrg#    define TimeRASMin4   1 << 13
234c35d236eSmrg#    define DeadCycle4    0 << 17
235c35d236eSmrg#    define BankDelay4    0 << 18
236c35d236eSmrg#    define Burst1Cycle4  1 << 31
237c35d236eSmrg#    define SDRAM4        0 << 4
238c35d236eSmrg
239c35d236eSmrg/* Permedia 2 Control */
240c35d236eSmrg#define MemControl							0x1040
241c35d236eSmrg
242c35d236eSmrg#define PMBypassWriteMask						0x1100
243c35d236eSmrg#define PMFramebufferWriteMask					        0x1140
244c35d236eSmrg#define PMCount								0x1180
245c35d236eSmrg
246c35d236eSmrg/* Framebuffer Registers */
247c35d236eSmrg#define FBMemoryCtl							0x1800
248c35d236eSmrg#define FBModeSel							0x1808
249c35d236eSmrg#define FBGCWrMask							0x1810
250c35d236eSmrg#define FBGCColorLower							0x1818
251c35d236eSmrg#define FBTXMemCtl							0x1820
252c35d236eSmrg#define FBWrMaskk							0x1830
253c35d236eSmrg#define FBGCColorUpper							0x1838
254c35d236eSmrg
255c35d236eSmrg/* Core FIFO */
256c35d236eSmrg#define OutputFIFO							0x2000
257c35d236eSmrg
258c35d236eSmrg/* 500TX Internal Video Registers */
259c35d236eSmrg#define VTGHLimit							0x3000
260c35d236eSmrg#define VTGHSyncStart							0x3008
261c35d236eSmrg#define VTGHSyncEnd							0x3010
262c35d236eSmrg#define VTGHBlankEnd							0x3018
263c35d236eSmrg#define VTGVLimit							0x3020
264c35d236eSmrg#define VTGVSyncStart							0x3028
265c35d236eSmrg#define VTGVSyncEnd							0x3030
266c35d236eSmrg#define VTGVBlankEnd							0x3038
267c35d236eSmrg#define VTGHGateStart							0x3040
268c35d236eSmrg#define VTGHGateEnd							0x3048
269c35d236eSmrg#define VTGVGateStart							0x3050
270c35d236eSmrg#define VTGVGateEnd							0x3058
271c35d236eSmrg#define VTGPolarity							0x3060
272c35d236eSmrg#define VTGFrameRowAddr							0x3068
273c35d236eSmrg#define VTGVLineNumber							0x3070
274c35d236eSmrg#define VTGSerialClk							0x3078
275c35d236eSmrg#define VTGModeCtl							0x3080
276c35d236eSmrg
277c35d236eSmrg/* Permedia Video Control Registers */
278c35d236eSmrg#define PMScreenBase							0x3000
279c35d236eSmrg#define PMScreenStride							0x3008
280c35d236eSmrg#define PMHTotal							0x3010
281c35d236eSmrg#define PMHgEnd								0x3018
282c35d236eSmrg#define PMHbEnd								0x3020
283c35d236eSmrg#define PMHsStart							0x3028
284c35d236eSmrg#define PMHsEnd								0x3030
285c35d236eSmrg#define PMVTotal							0x3038
286c35d236eSmrg#define PMVbEnd								0x3040
287c35d236eSmrg#define PMVsStart							0x3048
288c35d236eSmrg#define PMVsEnd								0x3050
289c35d236eSmrg#define PMVideoControl							0x3058
290c35d236eSmrg#define PMInterruptLine							0x3060
291c35d236eSmrg#define PMDDCData							0x3068
292c35d236eSmrg#define   DataIn             						(1<<0)
293c35d236eSmrg#define   ClkIn              						(1<<1)
294c35d236eSmrg#define   DataOut            						(1<<2)
295c35d236eSmrg#define   ClkOut             						(1<<3)
296c35d236eSmrg#define PMLineCount							0x3070
297c35d236eSmrg#define PMFifoControl							0x3078
298c35d236eSmrg
299c35d236eSmrg/* Permedia 2 RAMDAC Registers */
300c35d236eSmrg#define PM2DACWriteAddress						0x4000
301c35d236eSmrg#define PM2DACIndexReg							0x4000
302c35d236eSmrg#define PM2DACData							0x4008
303c35d236eSmrg#define PM2DACReadMask							0x4010
304c35d236eSmrg#define PM2DACReadAddress						0x4018
305c35d236eSmrg#define PM2DACCursorColorAddress				        0x4020
306c35d236eSmrg#define PM2DACCursorColorData					        0x4028
307c35d236eSmrg#define PM2DACIndexData							0x4050
308c35d236eSmrg#define PM2DACCursorData						0x4058
309c35d236eSmrg#define PM2DACCursorXLsb						0x4060
310c35d236eSmrg#define PM2DACCursorXMsb						0x4068
311c35d236eSmrg#define PM2DACCursorYLsb						0x4070
312c35d236eSmrg#define PM2DACCursorYMsb						0x4078
313c35d236eSmrg#define PM2DACCursorControl						0x06
314c35d236eSmrg#define PM2DACIndexCMR							0x18
315c35d236eSmrg#define   PM2DAC_TRUECOLOR				0x80
316c35d236eSmrg#define   PM2DAC_RGB					0x20
317c35d236eSmrg#define   PM2DAC_GRAPHICS				0x10
318c35d236eSmrg#define   PM2DAC_PACKED					0x09
319c35d236eSmrg#define   PM2DAC_8888					0x08
320c35d236eSmrg#define   PM2DAC_565					0x06
321c35d236eSmrg#define   PM2DAC_4444					0x05
322c35d236eSmrg#define   PM2DAC_5551					0x04
323c35d236eSmrg#define   PM2DAC_2321					0x03
324c35d236eSmrg#define   PM2DAC_2320					0x02
325c35d236eSmrg#define   PM2DAC_332					0x01
326c35d236eSmrg#define   PM2DAC_CI8					0x00
327c35d236eSmrg#define PM2DACIndexMDCR							0x19
328c35d236eSmrg#define PM2DACIndexPalettePage					        0x1c
329c35d236eSmrg#define PM2DACIndexMCR							0x1e
330c35d236eSmrg#define PM2DACIndexClockAM						0x20
331c35d236eSmrg#define PM2DACIndexClockAN						0x21
332c35d236eSmrg#define PM2DACIndexClockAP						0x22
333c35d236eSmrg#define PM2DACIndexClockBM						0x23
334c35d236eSmrg#define PM2DACIndexClockBN						0x24
335c35d236eSmrg#define PM2DACIndexClockBP						0x25
336c35d236eSmrg#define PM2DACIndexClockCM						0x26
337c35d236eSmrg#define PM2DACIndexClockCN						0x27
338c35d236eSmrg#define PM2DACIndexClockCP						0x28
339c35d236eSmrg#define PM2DACIndexClockStatus						0x29
340c35d236eSmrg#define PM2DACIndexMemClockM						0x30
341c35d236eSmrg#define PM2DACIndexMemClockN						0x31
342c35d236eSmrg#define PM2DACIndexMemClockP						0x32
343c35d236eSmrg#define PM2DACIndexMemClockStatus					0x33
344c35d236eSmrg#define PM2DACIndexColorKeyControl					0x40
345c35d236eSmrg#define PM2DACIndexColorKeyOverlay					0x41
346c35d236eSmrg#define PM2DACIndexColorKeyRed						0x42
347c35d236eSmrg#define PM2DACIndexColorKeyGreen					0x43
348c35d236eSmrg#define PM2DACIndexColorKeyBlue						0x44
349c35d236eSmrg
350c35d236eSmrg/* Permedia 2V extensions */
351c35d236eSmrg#define PM2VDACRDMiscControl						0x000
352c35d236eSmrg#define PM2VDACRDSyncControl						0x001
353c35d236eSmrg#define PM2VDACRDDACControl						0x002
354c35d236eSmrg#define PM2VDACRDPixelSize						0x003
355c35d236eSmrg#define PM2VDACRDColorFormat						0x004
356c35d236eSmrg#define PM2VDACRDCursorMode						0x005
357c35d236eSmrg#define PM2VDACRDCursorXLow						0x007
358c35d236eSmrg#define PM2VDACRDCursorXHigh						0x008
359c35d236eSmrg#define PM2VDACRDCursorYLow						0x009
360c35d236eSmrg#define PM2VDACRDCursorYHigh						0x00A
361c35d236eSmrg#define PM2VDACRDCursorHotSpotX						0x00B
362c35d236eSmrg#define PM2VDACRDCursorHotSpotY						0x00C
363c35d236eSmrg#define PM2VDACRDOverlayKey						0x00D
364c35d236eSmrg#define PM2VDACRDPan							0x00E
365c35d236eSmrg#define PM2VDACRDSense							0x00F
366c35d236eSmrg#define PM2VDACRDCheckControl						0x018
367c35d236eSmrg#define PM2VDACIndexClockControl					0x200
368c35d236eSmrg#define PM2VDACRDDClk0PreScale						0x201
369c35d236eSmrg#define PM2VDACRDDClk0FeedbackScale					0x202
370c35d236eSmrg#define PM2VDACRDDClk0PostScale						0x203
371c35d236eSmrg#define PM2VDACRDDClk1PreScale						0x204
372c35d236eSmrg#define PM2VDACRDDClk1FeedbackScale					0x205
373c35d236eSmrg#define PM2VDACRDDClk1PostScale						0x206
374c35d236eSmrg#define PM2VDACRDMClkControl						0x20D
375c35d236eSmrg#define PM2VDACRDMClkPreScale						0x20E
376c35d236eSmrg#define PM2VDACRDMClkFeedbackScale					0x20F
377c35d236eSmrg#define PM2VDACRDMClkPostScale						0x210
378c35d236eSmrg#define PM2VDACRDCursorPalette						0x303
379c35d236eSmrg#define PM2VDACRDCursorPattern						0x400
380c35d236eSmrg#define PM2VDACIndexRegLow						0x4020
381c35d236eSmrg#define PM2VDACIndexRegHigh						0x4028
382c35d236eSmrg#define PM2VDACIndexData						0x4030
383c35d236eSmrg#define PM2VDACRDIndexControl						0x4038
384c35d236eSmrg
385c35d236eSmrg/* Permedia 2 Video Streams Unit Registers */
386c35d236eSmrg#define   VSBIntFlag            					(1<<8)
387c35d236eSmrg#define   VSAIntFlag            					(1<<9)
388c35d236eSmrg
389c35d236eSmrg#define VSConfiguration							0x5800
390c35d236eSmrg#define   VS_UnitMode_ROM						0
391c35d236eSmrg#define   VS_UnitMode_AB8						3
392c35d236eSmrg#define   VS_UnitMode_Mask						7
393c35d236eSmrg#define   VS_GPBusMode_A        					(1<<3)
394c35d236eSmrg#define   VS_HRefPolarityA      					(1<<9)
395c35d236eSmrg#define   VS_VRefPolarityA      					(1<<10)
396c35d236eSmrg#define   VS_VActivePolarityA   					(1<<11)
397c35d236eSmrg#define   VS_UseFieldA          					(1<<12)
398c35d236eSmrg#define   VS_FieldPolarityA						(1<<13)
399c35d236eSmrg#define   VS_FieldEdgeA         					(1<<14)
400c35d236eSmrg#define   VS_VActiveVBIA						(1<<15)
401c35d236eSmrg#define   VS_InterlaceA         					(1<<16)
402c35d236eSmrg#define   VS_ReverseDataA       					(1<<17)
403c35d236eSmrg#define   VS_HRefPolarityB      					(1<<18)
404c35d236eSmrg#define   VS_VRefPolarityB      					(1<<19)
405c35d236eSmrg#define   VS_VActivePolarityB   					(1<<20)
406c35d236eSmrg#define   VS_UseFieldB							(1<<21)
407c35d236eSmrg#define   VS_FieldPolarityB						(1<<22)
408c35d236eSmrg#define   VS_FieldEdgeB							(1<<23)
409c35d236eSmrg#define   VS_VActiveVBIB						(1<<24)
410c35d236eSmrg#define   VS_InterlaceB							(1<<25)
411c35d236eSmrg#define   VS_ColorSpaceB_RGB						(1<<26)
412c35d236eSmrg#define   VS_ReverseDataB						(1<<27)
413c35d236eSmrg#define   VS_DoubleEdgeB						(1<<28)
414c35d236eSmrg
415c35d236eSmrg#define VSStatus							0x5808
416c35d236eSmrg#define   VS_FieldOne0A							(1<<9)
417c35d236eSmrg#define   VS_FieldOne1A							(1<<10)
418c35d236eSmrg#define   VS_FieldOne2A							(1<<11)
419c35d236eSmrg#define   VS_InvalidInterlaceA						(1<<12)
420c35d236eSmrg#define   VS_FieldOne0B							(1<<17)
421c35d236eSmrg#define   VS_FieldOne1B							(1<<18)
422c35d236eSmrg#define   VS_FieldOne2B							(1<<19)
423c35d236eSmrg#define   VS_InvalidInterlaceB						(1<<20)
424c35d236eSmrg
425c35d236eSmrg#define VSSerialBusControl						0x5810
426c35d236eSmrg
427c35d236eSmrg#define VSABase          						0x5900
428c35d236eSmrg#define   VSA_Video             					(1<<0)
429c35d236eSmrg#define   VSA_VBI               					(1<<1)
430c35d236eSmrg#define   VSA_BufferCtl         					(1<<2)
431c35d236eSmrg#define   VSA_MirrorX           					(1<<7)
432c35d236eSmrg#define   VSA_MirrorY           					(1<<8)
433c35d236eSmrg#define   VSA_Discard_None      					(0<<9)
434c35d236eSmrg#define   VSA_Discard_FieldOne  					(1<<9)
435c35d236eSmrg#define   VSA_Discard_FieldTwo  					(2<<9)
436c35d236eSmrg#define   VSA_CombineFields     					(1<<11)
437c35d236eSmrg#define   VSA_LockToStreamB     					(1<<12)
438c35d236eSmrg#define VSBBase								0x5A00
439c35d236eSmrg#define   VSB_Video             					(1<<0)
440c35d236eSmrg#define   VSB_VBI               					(1<<1)
441c35d236eSmrg#define   VSB_BufferCtl         					(1<<2)
442c35d236eSmrg#define   VSB_CombineFields     					(1<<3)
443c35d236eSmrg#define   VSB_RGBOrder          					(1<<11)
444c35d236eSmrg#define   VSB_GammaCorrect      					(1<<12)
445c35d236eSmrg#define   VSB_LockToStreamA     					(1<<13)
446c35d236eSmrg
447c35d236eSmrg#define VSControl							0x0000
448c35d236eSmrg#define VSInterrupt            						0x0008
449c35d236eSmrg#define VSCurrentLine          						0x0010
450c35d236eSmrg#define VSVideoAddressHost     						0x0018
451c35d236eSmrg#define VSVideoAddressIndex    						0x0020
452c35d236eSmrg#define VSVideoAddress0        						0x0028
453c35d236eSmrg#define VSVideoAddress1        						0x0030
454c35d236eSmrg#define VSVideoAddress2        						0x0038
455c35d236eSmrg#define VSVideoStride          						0x0040
456c35d236eSmrg#define VSVideoStartLine       						0x0048
457c35d236eSmrg#define VSVideoEndLine     						0x0050
458c35d236eSmrg#define VSVideoStartData       						0x0058
459c35d236eSmrg#define VSVideoEndData         						0x0060
460c35d236eSmrg#define VSVBIAddressHost       						0x0068
461c35d236eSmrg#define VSVBIAddressIndex      						0x0070
462c35d236eSmrg#define VSVBIAddress0          						0x0078
463c35d236eSmrg#define VSVBIAddress1          						0x0080
464c35d236eSmrg#define VSVBIAddress2          						0x0088
465c35d236eSmrg#define VSVBIStride            						0x0090
466c35d236eSmrg#define VSVBIStartLine         						0x0098
467c35d236eSmrg#define VSVBIEndLine           						0x00A0
468c35d236eSmrg#define VSVBIStartData         						0x00A8
469c35d236eSmrg#define VSVBIEndData           						0x00B0
470c35d236eSmrg#define VSFifoControl          						0x00B8
471c35d236eSmrg
472c35d236eSmrg/**********************************
473c35d236eSmrg * GLINT Delta Region 0 Registers *
474c35d236eSmrg **********************************/
475c35d236eSmrg
476c35d236eSmrg/* Control Status Registers */
477c35d236eSmrg#define DResetStatus							0x0800
478c35d236eSmrg#define DIntEnable							0x0808
479c35d236eSmrg#define DIntFlags							0x0810
480c35d236eSmrg#define DErrorFlags							0x0838
481c35d236eSmrg#define DTestRegister							0x0848
482c35d236eSmrg#define DFIFODis							0x0868
483c35d236eSmrg
484c35d236eSmrg
485c35d236eSmrg
486c35d236eSmrg/**********************************
487c35d236eSmrg * GLINT Gamma Region 0 Registers *
488c35d236eSmrg **********************************/
489c35d236eSmrg
490c35d236eSmrg/* Control Status Registers */
491c35d236eSmrg#define GInFIFOSpace							0x0018
492c35d236eSmrg#define GDMAAddress							0x0028
493c35d236eSmrg#define GDMACount							0x0030
494c35d236eSmrg#define GDMAControl							0x0060
495c35d236eSmrg#define GOutDMA								0x0080
496c35d236eSmrg#define GOutDMACount							0x0088
497c35d236eSmrg#define GResetStatus							0x0800
498c35d236eSmrg#define GIntEnable							0x0808
499c35d236eSmrg#define GIntFlags							0x0810
500c35d236eSmrg#define GErrorFlags							0x0838
501c35d236eSmrg#define GTestRegister							0x0848
502c35d236eSmrg#define GFIFODis							0x0868
503c35d236eSmrg
504c35d236eSmrg#define GChipConfig							0x0870
505c35d236eSmrg#define   GChipAGPCapable		1 << 0
506c35d236eSmrg#define   GChipAGPSideband		1 << 1
507c35d236eSmrg#define   GChipMultiGLINTApMask		3 << 19
508c35d236eSmrg#define   GChipMultiGLINTAp_0M		0 << 19
509c35d236eSmrg#define   GChipMultiGLINTAp_16M		1 << 19
510c35d236eSmrg#define   GChipMultiGLINTAp_32M		2 << 19
511c35d236eSmrg#define   GChipMultiGLINTAp_64M		3 << 19
512c35d236eSmrg
513c35d236eSmrg#define GCSRAperture							0x0878
514c35d236eSmrg#define   GCSRSecondaryGLINTMapEn	1 << 0
515c35d236eSmrg#define   GCSRBitSwap			1 << 1
516c35d236eSmrg
517c35d236eSmrg#define GPageTableAddr							0x0c00
518c35d236eSmrg#define GPageTableLength						0x0c08
519c35d236eSmrg#define GDelayTimer							0x0c38
520c35d236eSmrg#define GCommandMode							0x0c40
521c35d236eSmrg#define GCommandIntEnable						0x0c48
522c35d236eSmrg#define GCommandIntFlags						0x0c50
523c35d236eSmrg#define GCommandErrorFlags						0x0c58
524c35d236eSmrg#define GCommandStatus							0x0c60
525c35d236eSmrg#define GCommandFaultingAddr						0x0c68
526c35d236eSmrg#define GVertexFaultingAddr						0x0c70
527c35d236eSmrg#define GWriteFaultingAddr						0x0c88
528c35d236eSmrg#define GFeedbackSelectCount						0x0c98
529c35d236eSmrg#define GGammaProcessorMode						0x0cb8
530c35d236eSmrg#define GVGAShadow							0x0d00
531c35d236eSmrg#define GMultGLINTAperture						0x0d08
532c35d236eSmrg#define GMultGLINT1							0x0d10
533c35d236eSmrg#define GMultGLINT2							0x0d18
534c35d236eSmrg
535c35d236eSmrg/************************
536c35d236eSmrg * GLINT Core Registers *
537c35d236eSmrg ************************/
538c35d236eSmrg
539c35d236eSmrg#define GLINT_TAG(major,offset)			(((major) << 7) | ((offset) << 3))
540c35d236eSmrg#define GLINT_TAG_ADDR(major,offset)	(0x8000 | GLINT_TAG((major),(offset)))
541c35d236eSmrg
542c35d236eSmrg#define UNIT_DISABLE							0
543c35d236eSmrg#define UNIT_ENABLE							1
544c35d236eSmrg
545c35d236eSmrg#define StartXDom							GLINT_TAG_ADDR(0x00,0x00)
546c35d236eSmrg#define dXDom								GLINT_TAG_ADDR(0x00,0x01)
547c35d236eSmrg#define StartXSub							GLINT_TAG_ADDR(0x00,0x02)
548c35d236eSmrg#define dXSub								GLINT_TAG_ADDR(0x00,0x03)
549c35d236eSmrg#define StartY								GLINT_TAG_ADDR(0x00,0x04)
550c35d236eSmrg#define dY									GLINT_TAG_ADDR(0x00,0x05)
551c35d236eSmrg#define GLINTCount							GLINT_TAG_ADDR(0x00,0x06)
552c35d236eSmrg#define Render								GLINT_TAG_ADDR(0x00,0x07)
553c35d236eSmrg#	define AreaStippleEnable					0x00001
554c35d236eSmrg#	define LineStippleEnable					0x00002
555c35d236eSmrg#	define ResetLineStipple					0x00004
556c35d236eSmrg#	define FastFillEnable						0x00008
557c35d236eSmrg#	define PrimitiveLine						0
558c35d236eSmrg#	define PrimitiveTrapezoid					0x00040
559c35d236eSmrg#	define PrimitivePoint						0x00080
560c35d236eSmrg#	define PrimitiveRectangle					0x000C0
561c35d236eSmrg#	define AntialiasEnable         				0x00100
562c35d236eSmrg#	define AntialiasingQuality     				0x00200
563c35d236eSmrg#	define UsePointTable						0x00400
564c35d236eSmrg#	define SyncOnBitMask						0x00800
565c35d236eSmrg#	define SyncOnHostData						0x01000
566c35d236eSmrg#	define TextureEnable           				0x02000
567c35d236eSmrg#	define FogEnable               				0x04000
568c35d236eSmrg#	define CoverageEnable						0x08000
569c35d236eSmrg#	define SubPixelCorrectionEnable				0x10000
570c35d236eSmrg#	define SpanOperation						0x40000
571c35d236eSmrg#	define XPositive			1<<21
572c35d236eSmrg#	define YPositive			1<<22
573c35d236eSmrg
574c35d236eSmrg
575c35d236eSmrg#define ContinueNewLine							GLINT_TAG_ADDR(0x00,0x08)
576c35d236eSmrg#define ContinueNewDom							GLINT_TAG_ADDR(0x00,0x09)
577c35d236eSmrg#define ContinueNewSub							GLINT_TAG_ADDR(0x00,0x0a)
578c35d236eSmrg#define Continue							GLINT_TAG_ADDR(0x00,0x0b)
579c35d236eSmrg#define FlushSpan							GLINT_TAG_ADDR(0x00,0x0c)
580c35d236eSmrg#define BitMaskPattern							GLINT_TAG_ADDR(0x00,0x0d)
581c35d236eSmrg
582c35d236eSmrg#define PointTable0							GLINT_TAG_ADDR(0x01,0x00)
583c35d236eSmrg#define PointTable1							GLINT_TAG_ADDR(0x01,0x01)
584c35d236eSmrg#define PointTable2							GLINT_TAG_ADDR(0x01,0x02)
585c35d236eSmrg#define PointTable3							GLINT_TAG_ADDR(0x01,0x03)
586c35d236eSmrg#define RasterizerMode							GLINT_TAG_ADDR(0x01,0x04)
587c35d236eSmrg#define		RMMultiGLINT			1<<17
588c35d236eSmrg#define		BitMaskPackingEachScanline	1<<9
589c35d236eSmrg#define		ForceBackgroundColor		1<<6
590c35d236eSmrg#define		InvertBitMask			1<<1
591c35d236eSmrg#define YLimits								GLINT_TAG_ADDR(0x01,0x05)
592c35d236eSmrg#define ScanLineOwnership						GLINT_TAG_ADDR(0x01,0x06)
593c35d236eSmrg#define WaitForCompletion						GLINT_TAG_ADDR(0x01,0x07)
594c35d236eSmrg#define PixelSize							GLINT_TAG_ADDR(0x01,0x08)
595c35d236eSmrg#define XLimits								GLINT_TAG_ADDR(0x01,0x09) /* PM only */
596c35d236eSmrg
597c35d236eSmrg#define RectangleOrigin							GLINT_TAG_ADDR(0x01,0x0A) /* PM2 only */
598c35d236eSmrg#define RectangleSize							GLINT_TAG_ADDR(0x01,0x0B) /* PM2 only */
599c35d236eSmrg
600c35d236eSmrg#define PackedDataLimits						GLINT_TAG_ADDR(0x02,0x0a) /* PM only */
601c35d236eSmrg
602c35d236eSmrg#define ScissorMode							GLINT_TAG_ADDR(0x03,0x00)
603c35d236eSmrg#	define                                    	        SCI_USER          0x01
604c35d236eSmrg#	define                                                 SCI_SCREEN        0x02
605c35d236eSmrg#	define                                                 SCI_USERANDSCREEN 0x03
606c35d236eSmrg
607c35d236eSmrg#define ScissorMinXY						GLINT_TAG_ADDR(0x03,0x01)
608c35d236eSmrg#define ScissorMaxXY						GLINT_TAG_ADDR(0x03,0x02)
609c35d236eSmrg#define ScreenSize						GLINT_TAG_ADDR(0x03,0x03)
610c35d236eSmrg#define AreaStippleMode						GLINT_TAG_ADDR(0x03,0x04)
611c35d236eSmrg	/* 0:				*/
612c35d236eSmrg	/* NoMirrorY			*/
613c35d236eSmrg	/* NoMirrorX			*/
614c35d236eSmrg	/* NoInvertPattern		*/
615c35d236eSmrg	/* YAddress_1bit		*/
616c35d236eSmrg	/* XAddress_1bit		*/
617c35d236eSmrg	/* UNIT_DISABLE			*/
618c35d236eSmrg
619c35d236eSmrg#	define ASM_XAddress_2bit					1 << 1
620c35d236eSmrg#	define ASM_XAddress_3bit					2 << 1
621c35d236eSmrg#	define ASM_XAddress_4bit					3 << 1
622c35d236eSmrg#	define ASM_XAddress_5bit					4 << 1
623c35d236eSmrg#	define ASM_YAddress_2bit					1 << 4
624c35d236eSmrg#	define ASM_YAddress_3bit					2 << 4
625c35d236eSmrg#	define ASM_YAddress_4bit					3 << 4
626c35d236eSmrg#	define ASM_YAddress_5bit					4 << 4
627c35d236eSmrg#	define ASM_InvertPattern					1 << 17
628c35d236eSmrg#	define ASM_MirrorX						1 << 18
629c35d236eSmrg#	define ASM_MirrorY						1 << 19
630c35d236eSmrg
631c35d236eSmrg#define LineStippleMode						GLINT_TAG_ADDR(0x03,0x05)
632c35d236eSmrg#define LoadLineStippleCounters					GLINT_TAG_ADDR(0x03,0x06)
633c35d236eSmrg#define UpdateLineStippleCounters				GLINT_TAG_ADDR(0x03,0x07)
634c35d236eSmrg#define SaveLineStippleState					GLINT_TAG_ADDR(0x03,0x08)
635c35d236eSmrg#define WindowOrigin						GLINT_TAG_ADDR(0x03,0x09)
636c35d236eSmrg
637c35d236eSmrg#define AreaStipplePattern0					GLINT_TAG_ADDR(0x04,0x00)
638c35d236eSmrg#define AreaStipplePattern1					GLINT_TAG_ADDR(0x04,0x01)
639c35d236eSmrg#define AreaStipplePattern2					GLINT_TAG_ADDR(0x04,0x02)
640c35d236eSmrg#define AreaStipplePattern3					GLINT_TAG_ADDR(0x04,0x03)
641c35d236eSmrg#define AreaStipplePattern4					GLINT_TAG_ADDR(0x04,0x04)
642c35d236eSmrg#define AreaStipplePattern5					GLINT_TAG_ADDR(0x04,0x05)
643c35d236eSmrg#define AreaStipplePattern6					GLINT_TAG_ADDR(0x04,0x06)
644c35d236eSmrg#define AreaStipplePattern7					GLINT_TAG_ADDR(0x04,0x07)
645c35d236eSmrg
646c35d236eSmrg#define TextureAddressMode					GLINT_TAG_ADDR(0x07,0x00)
647c35d236eSmrg#define SStart							GLINT_TAG_ADDR(0x07,0x01)
648c35d236eSmrg#define dSdx							GLINT_TAG_ADDR(0x07,0x02)
649c35d236eSmrg#define dSdyDom							GLINT_TAG_ADDR(0x07,0x03)
650c35d236eSmrg#define TStart							GLINT_TAG_ADDR(0x07,0x04)
651c35d236eSmrg#define dTdx							GLINT_TAG_ADDR(0x07,0x05)
652c35d236eSmrg#define dTdyDom							GLINT_TAG_ADDR(0x07,0x06)
653c35d236eSmrg#define QStart							GLINT_TAG_ADDR(0x07,0x07)
654c35d236eSmrg#define dQdx							GLINT_TAG_ADDR(0x07,0x08)
655c35d236eSmrg#define dQdyDom							GLINT_TAG_ADDR(0x07,0x09)
656c35d236eSmrg#define LOD							GLINT_TAG_ADDR(0x07,0x0A)
657c35d236eSmrg#define dSdy							GLINT_TAG_ADDR(0x07,0x0B)
658c35d236eSmrg#define dTdy							GLINT_TAG_ADDR(0x07,0x0C)
659c35d236eSmrg#define dQdy							GLINT_TAG_ADDR(0x07,0x0D)
660c35d236eSmrg
661c35d236eSmrg#define TextureReadMode						GLINT_TAG_ADDR(0x09,0x00)
662c35d236eSmrg#define TextureFormat						GLINT_TAG_ADDR(0x09,0x01)
663c35d236eSmrg#  define Texture_4_Components 3 << 3
664c35d236eSmrg#  define Texture_Texel        0
665c35d236eSmrg
666c35d236eSmrg#define TextureCacheControl					GLINT_TAG_ADDR(0x09,0x02)
667c35d236eSmrg#  define TextureCacheControlEnable     2
668c35d236eSmrg#  define TextureCacheControlInvalidate 1
669c35d236eSmrg
670c35d236eSmrg#define GLINTBorderColor					GLINT_TAG_ADDR(0x09,0x05)
671c35d236eSmrg
672c35d236eSmrg#define TexelLUTIndex						GLINT_TAG_ADDR(0x09,0x08)
673c35d236eSmrg#define TexelLUTData						GLINT_TAG_ADDR(0x09,0x09)
674c35d236eSmrg#define TexelLUTAddress						GLINT_TAG_ADDR(0x09,0x0A)
675c35d236eSmrg#define TexelLUTTransfer					GLINT_TAG_ADDR(0x09,0x0B)
676c35d236eSmrg#define TextureFilterMode					GLINT_TAG_ADDR(0x09,0x0C)
677c35d236eSmrg#define TextureChromaUpper					GLINT_TAG_ADDR(0x09,0x0D)
678c35d236eSmrg#define TextureChromaLower					GLINT_TAG_ADDR(0x09,0x0E)
679c35d236eSmrg
680c35d236eSmrg#define TxBaseAddr0						GLINT_TAG_ADDR(0x0A,0x00)
681c35d236eSmrg#define TxBaseAddr1						GLINT_TAG_ADDR(0x0A,0x01)
682c35d236eSmrg#define TxBaseAddr2						GLINT_TAG_ADDR(0x0A,0x02)
683c35d236eSmrg#define TxBaseAddr3						GLINT_TAG_ADDR(0x0A,0x03)
684c35d236eSmrg#define TxBaseAddr4						GLINT_TAG_ADDR(0x0A,0x04)
685c35d236eSmrg#define TxBaseAddr5						GLINT_TAG_ADDR(0x0A,0x05)
686c35d236eSmrg#define TxBaseAddr6						GLINT_TAG_ADDR(0x0A,0x06)
687c35d236eSmrg#define TxBaseAddr7						GLINT_TAG_ADDR(0x0A,0x07)
688c35d236eSmrg#define TxBaseAddr8						GLINT_TAG_ADDR(0x0A,0x08)
689c35d236eSmrg#define TxBaseAddr9						GLINT_TAG_ADDR(0x0A,0x09)
690c35d236eSmrg#define TxBaseAddr10						GLINT_TAG_ADDR(0x0A,0x0A)
691c35d236eSmrg#define TxBaseAddr11						GLINT_TAG_ADDR(0x0A,0x0B)
692c35d236eSmrg
693c35d236eSmrg#define PMTextureBaseAddress					GLINT_TAG_ADDR(0x0b,0x00)
694c35d236eSmrg#define PMTextureMapFormat					GLINT_TAG_ADDR(0x0b,0x01)
695c35d236eSmrg#define PMTextureDataFormat					GLINT_TAG_ADDR(0x0b,0x02)
696c35d236eSmrg
697c35d236eSmrg#define Texel0							GLINT_TAG_ADDR(0x0c,0x00)
698c35d236eSmrg#define Texel1							GLINT_TAG_ADDR(0x0c,0x01)
699c35d236eSmrg#define Texel2							GLINT_TAG_ADDR(0x0c,0x02)
700c35d236eSmrg#define Texel3							GLINT_TAG_ADDR(0x0c,0x03)
701c35d236eSmrg#define Texel4							GLINT_TAG_ADDR(0x0c,0x04)
702c35d236eSmrg#define Texel5							GLINT_TAG_ADDR(0x0c,0x05)
703c35d236eSmrg#define Texel6							GLINT_TAG_ADDR(0x0c,0x06)
704c35d236eSmrg#define Texel7							GLINT_TAG_ADDR(0x0c,0x07)
705c35d236eSmrg#define Interp0							GLINT_TAG_ADDR(0x0c,0x08)
706c35d236eSmrg#define Interp1							GLINT_TAG_ADDR(0x0c,0x09)
707c35d236eSmrg#define Interp2							GLINT_TAG_ADDR(0x0c,0x0a)
708c35d236eSmrg#define Interp3							GLINT_TAG_ADDR(0x0c,0x0b)
709c35d236eSmrg#define Interp4							GLINT_TAG_ADDR(0x0c,0x0c)
710c35d236eSmrg#define TextureFilter						GLINT_TAG_ADDR(0x0c,0x0d)
711c35d236eSmrg#define PMTextureReadMode					GLINT_TAG_ADDR(0x0c,0x0e)
712c35d236eSmrg#define TexelLUTMode						GLINT_TAG_ADDR(0x0c,0x0f)
713c35d236eSmrg
714c35d236eSmrg#define TextureColorMode					GLINT_TAG_ADDR(0x0d,0x00)
715a3890ad9Smacallan#  define TextureModeModulate	0 << 1
716a3890ad9Smacallan#  define TextureModeDecal	1 << 1
717a3890ad9Smacallan#  define TextureModeCopy	3 << 1
718c35d236eSmrg#  define TextureTypeOpenGL 0
719c35d236eSmrg#  define TextureTypeApple  1 << 4
720c35d236eSmrg#  define TextureKsDDA      1 << 5 /* only Apple-Mode */
721c35d236eSmrg#  define TextureKdDDA      1 << 6 /* only Apple-Mode */
722c35d236eSmrg
723c35d236eSmrg#define TextureEnvColor						GLINT_TAG_ADDR(0x0d,0x01)
724c35d236eSmrg#define FogMode							GLINT_TAG_ADDR(0x0d,0x02)
725c35d236eSmrg	/* 0:				*/
726c35d236eSmrg	/* FOG RGBA			*/
727c35d236eSmrg	/* UNIT_DISABLE			*/
728c35d236eSmrg
729c35d236eSmrg#	define FOG_CI							0x0002
730c35d236eSmrg
731c35d236eSmrg#define FogColor							GLINT_TAG_ADDR(0x0d,0x03)
732c35d236eSmrg#define FStart								GLINT_TAG_ADDR(0x0d,0x04)
733c35d236eSmrg#define dFdx								GLINT_TAG_ADDR(0x0d,0x05)
734c35d236eSmrg#define dFdyDom								GLINT_TAG_ADDR(0x0d,0x06)
735c35d236eSmrg#define KsStart								GLINT_TAG_ADDR(0x0d,0x09)
736c35d236eSmrg#define dKsdx								GLINT_TAG_ADDR(0x0d,0x0a)
737c35d236eSmrg#define dKsdyDom							GLINT_TAG_ADDR(0x0d,0x0b)
738c35d236eSmrg#define KdStart								GLINT_TAG_ADDR(0x0d,0x0c)
739c35d236eSmrg#define dKdStart							GLINT_TAG_ADDR(0x0d,0x0d)
740c35d236eSmrg#define dKddyDom							GLINT_TAG_ADDR(0x0d,0x0e)
741c35d236eSmrg
742c35d236eSmrg#define RStart								GLINT_TAG_ADDR(0x0f,0x00)
743c35d236eSmrg#define dRdx								GLINT_TAG_ADDR(0x0f,0x01)
744c35d236eSmrg#define dRdyDom								GLINT_TAG_ADDR(0x0f,0x02)
745c35d236eSmrg#define GStart								GLINT_TAG_ADDR(0x0f,0x03)
746c35d236eSmrg#define dGdx								GLINT_TAG_ADDR(0x0f,0x04)
747c35d236eSmrg#define dGdyDom								GLINT_TAG_ADDR(0x0f,0x05)
748c35d236eSmrg#define BStart								GLINT_TAG_ADDR(0x0f,0x06)
749c35d236eSmrg#define dBdx								GLINT_TAG_ADDR(0x0f,0x07)
750c35d236eSmrg#define dBdyDom								GLINT_TAG_ADDR(0x0f,0x08)
751c35d236eSmrg#define AStart								GLINT_TAG_ADDR(0x0f,0x09)
752c35d236eSmrg#define dAdx								GLINT_TAG_ADDR(0x0f,0x0a)
753c35d236eSmrg#define dAdyDom								GLINT_TAG_ADDR(0x0f,0x0b)
754c35d236eSmrg#define ColorDDAMode							GLINT_TAG_ADDR(0x0f,0x0c)
755c35d236eSmrg	/* 0:					*/
756c35d236eSmrg#	define CDDA_FlatShading			                0
757c35d236eSmrg	/* UNIT_DISABLE			*/
758c35d236eSmrg#	define CDDA_GouraudShading					0x0002
759c35d236eSmrg
760c35d236eSmrg
761c35d236eSmrg#define ConstantColor						GLINT_TAG_ADDR(0x0f,0x0d)
762c35d236eSmrg#define GLINTColor						GLINT_TAG_ADDR(0x0f,0x0e)
763c35d236eSmrg#define AlphaTestMode						GLINT_TAG_ADDR(0x10,0x00)
764c35d236eSmrg#define AntialiasMode						GLINT_TAG_ADDR(0x10,0x01)
765c35d236eSmrg#define AlphaBlendMode						GLINT_TAG_ADDR(0x10,0x02)
766c35d236eSmrg	/* 0:					*/
767c35d236eSmrg	/* SrcZERO				*/
768c35d236eSmrg	/* DstZERO				*/
769c35d236eSmrg	/* ColorFormat8888			*/
770c35d236eSmrg	/* AlphaBuffer present			*/
771c35d236eSmrg	/* ColorOrderBGR			*/
772c35d236eSmrg	/* TypeOpenGL				*/
773c35d236eSmrg	/* DstFBData				*/
774c35d236eSmrg	/* UNIT_DISABLE				*/
775c35d236eSmrg
776a3890ad9Smacallan#	define ABM_SrcZERO					0 << 1
777c35d236eSmrg#	define ABM_SrcONE					1 << 1
778c35d236eSmrg#	define ABM_SrcDST_COLOR				2 << 1
779c35d236eSmrg#	define ABM_SrcONE_MINUS_DST_COLOR			3 << 1
780c35d236eSmrg#	define ABM_SrcSRC_ALPHA				4 << 1
781c35d236eSmrg#	define ABM_SrcONE_MINUS_SRC_ALPHA			5 << 1
782c35d236eSmrg#	define ABM_SrcDST_ALPHA				6 << 1
783c35d236eSmrg#	define ABM_SrcONE_MINUS_DST_ALPHA			7 << 1
784c35d236eSmrg#	define ABM_SrcSRC_ALPHA_SATURATE			8 << 1
785a3890ad9Smacallan#	define ABM_DstZERO					0 << 5
786c35d236eSmrg#	define ABM_DstONE					1 << 5
787c35d236eSmrg#	define ABM_DstSRC_COLOR				2 << 5
788c35d236eSmrg#	define ABM_DstONE_MINUS_SRC_COLOR			3 << 5
789c35d236eSmrg#	define ABM_DstSRC_ALPHA				4 << 5
790c35d236eSmrg#	define ABM_DstONE_MINUS_SRC_ALPHA			5 << 5
791c35d236eSmrg#	define ABM_DstDST_ALPHA				6 << 5
792c35d236eSmrg#	define ABM_DstONE_MINUS_DST_ALPHA			7 << 5
793c35d236eSmrg#	define ABM_ColorFormat5555				1 << 8
794c35d236eSmrg#	define ABM_ColorFormat4444				2 << 8
795c35d236eSmrg#	define ABM_ColorFormat4444_Front			3 << 8
796c35d236eSmrg#	define ABM_ColorFormat4444_Back			4 << 8
797c35d236eSmrg#	define ABM_ColorFormat332_Front			5 << 8
798c35d236eSmrg#	define ABM_ColorFormat332_Back				6 << 8
799c35d236eSmrg#	define ABM_ColorFormat121_Front			7 << 8
800c35d236eSmrg#	define ABM_ColorFormat121_Back				8 << 8
801c35d236eSmrg#	define ABM_ColorFormat555_Back				13 << 8
802c35d236eSmrg#	define ABM_ColorFormat_CI8				14 << 8
803c35d236eSmrg#	define ABM_ColorFormat_CI4				15 << 8
804c35d236eSmrg#	define ABM_NoAlphaBuffer				0x1000
805c35d236eSmrg#	define ABM_ColorOrderRGB				0x2000
806c35d236eSmrg#	define ABM_TypeQuickDraw3D				0x4000
807c35d236eSmrg#	define ABM_DstFBSourceData				0x8000
808c35d236eSmrg
809c35d236eSmrg#define DitherMode						GLINT_TAG_ADDR(0x10,0x03)
810c35d236eSmrg	/* 0:					*/
811c35d236eSmrg	/* ColorOrder BGR		*/
812c35d236eSmrg	/* AlphaDitherDefault	*/
813c35d236eSmrg	/* ColorFormat8888		*/
814c35d236eSmrg	/* TruncateMode 		*/
815c35d236eSmrg	/* DitherDisable		*/
816c35d236eSmrg	/* UNIT_DISABLE			*/
817c35d236eSmrg
818c35d236eSmrg#	define DTM_DitherEnable				1 << 1
819c35d236eSmrg#	define DTM_ColorFormat5555				1 << 2
820c35d236eSmrg#	define DTM_ColorFormat4444				2 << 2
821c35d236eSmrg#	define DTM_ColorFormat4444_Front			3 << 2
822c35d236eSmrg#	define DTM_ColorFormat4444_Back			4 << 2
823c35d236eSmrg#	define DTM_ColorFormat332_Front			5 << 2
824c35d236eSmrg#	define DTM_ColorFormat332_Back				6 << 2
825c35d236eSmrg#	define DTM_ColorFormat121_Front			7 << 2
826c35d236eSmrg#	define DTM_ColorFormat121_Back				8 << 2
827c35d236eSmrg#	define DTM_ColorFormat555_Back				13 << 2
828c35d236eSmrg#	define DTM_ColorFormat_CI8				14 << 2
829c35d236eSmrg#	define DTM_ColorFormat_CI4				15 << 2
830c35d236eSmrg#	define DTM_ColorOrderRGB				1 << 10
831c35d236eSmrg#	define DTM_NoAlphaDither				1 << 14
832c35d236eSmrg#	define DTM_RoundMode					1 << 15
833c35d236eSmrg
834c35d236eSmrg#define FBSoftwareWriteMask					GLINT_TAG_ADDR(0x10,0x04)
835c35d236eSmrg#define LogicalOpMode						GLINT_TAG_ADDR(0x10,0x05)
836c35d236eSmrg#	define Use_ConstantFBWriteData 0x40
837c35d236eSmrg
838c35d236eSmrg
839c35d236eSmrg#define FBWriteData						GLINT_TAG_ADDR(0x10,0x06)
840c35d236eSmrg#define RouterMode						GLINT_TAG_ADDR(0x10,0x08)
841c35d236eSmrg#	define ROUTER_Depth_Texture 1
842c35d236eSmrg#	define ROUTER_Texture_Depth 0
843c35d236eSmrg
844c35d236eSmrg
845c35d236eSmrg#define LBReadMode						GLINT_TAG_ADDR(0x11,0x00)
846c35d236eSmrg	/* 0:				*/
847c35d236eSmrg	/* SrcNoRead			*/
848c35d236eSmrg	/* DstNoRead			*/
849c35d236eSmrg	/* DataLBDefault		*/
850c35d236eSmrg	/* WinTopLeft			*/
851c35d236eSmrg	/* NoPatch			*/
852c35d236eSmrg	/* ScanlineInterval1 		*/
853c35d236eSmrg
854c35d236eSmrg#	define LBRM_SrcEnable						1 << 9
855c35d236eSmrg#	define LBRM_DstEnable						1 << 10
856c35d236eSmrg#	define LBRM_DataLBStencil					1 << 16
857c35d236eSmrg#	define LBRM_DataLBDepth					2 << 16
858c35d236eSmrg#	define LBRM_WinBottomLeft					1 << 18
859c35d236eSmrg#	define LBRM_DoPatch						1 << 19
860c35d236eSmrg
861c35d236eSmrg#	define LBRM_ScanlineInt2					1 << 20
862c35d236eSmrg#	define LBRM_ScanlineInt4					2 << 20
863c35d236eSmrg#	define LBRM_ScanlineInt8					3 << 20
864c35d236eSmrg
865c35d236eSmrg
866c35d236eSmrg#define LBReadFormat						GLINT_TAG_ADDR(0x11,0x01)
867c35d236eSmrg#	define LBRF_DepthWidth15   0x03  /* only permedia */
868c35d236eSmrg#	define LBRF_DepthWidth16   0x00
869c35d236eSmrg#	define LBRF_DepthWidth24   0x01
870c35d236eSmrg#	define LBRF_DepthWidth32   0x02
871c35d236eSmrg
872c35d236eSmrg#	define LBRF_StencilWidth0  (0 << 2)
873c35d236eSmrg#	define LBRF_StencilWidth4  (1 << 2)
874c35d236eSmrg#	define LBRF_StencilWidth8  (2 << 2)
875c35d236eSmrg
876c35d236eSmrg#	define LBRF_StencilPos16   (0 << 4)
877c35d236eSmrg#	define LBRF_StencilPos20   (1 << 4)
878c35d236eSmrg#	define LBRF_StencilPos24   (2 << 4)
879c35d236eSmrg#	define LBRF_StencilPos28   (3 << 4)
880c35d236eSmrg#	define LBRF_StencilPos32   (4 << 4)
881c35d236eSmrg
882c35d236eSmrg#	define LBRF_FrameCount0    (0 << 7)
883c35d236eSmrg#	define LBRF_FrameCount4    (1 << 7)
884c35d236eSmrg#	define LBRF_FrameCount8    (2 << 7)
885c35d236eSmrg
886c35d236eSmrg#	define LBRF_FrameCountPos16  (0 << 9)
887c35d236eSmrg#	define LBRF_FrameCountPos20  (1 << 9)
888c35d236eSmrg#	define LBRF_FrameCountPos24  (2 << 9)
889c35d236eSmrg#	define LBRF_FrameCountPos28  (3 << 9)
890c35d236eSmrg#	define LBRF_FrameCountPos32  (4 << 9)
891c35d236eSmrg#	define LBRF_FrameCountPos36  (5 << 9)
892c35d236eSmrg#	define LBRF_FrameCountPos40  (6 << 9)
893c35d236eSmrg
894c35d236eSmrg#	define LBRF_GIDWidth0 (0 << 12)
895c35d236eSmrg#	define LBRF_GIDWidth4 (1 << 12)
896c35d236eSmrg
897c35d236eSmrg#	define LBRF_GIDPos16  (0 << 13)
898c35d236eSmrg#	define LBRF_GIDPos20  (1 << 13)
899c35d236eSmrg#	define LBRF_GIDPos24  (2 << 13)
900c35d236eSmrg#	define LBRF_GIDPos28  (3 << 13)
901c35d236eSmrg#	define LBRF_GIDPos32  (4 << 13)
902c35d236eSmrg#	define LBRF_GIDPos36  (5 << 13)
903c35d236eSmrg#	define LBRF_GIDPos40  (6 << 13)
904c35d236eSmrg#	define LBRF_GIDPos44  (7 << 13)
905c35d236eSmrg#	define LBRF_GIDPos48  (8 << 13)
906c35d236eSmrg
907c35d236eSmrg#	define LBRF_Compact32  (1 << 17)
908c35d236eSmrg
909c35d236eSmrg
910c35d236eSmrg
911c35d236eSmrg#define LBSourceOffset						GLINT_TAG_ADDR(0x11,0x02)
912c35d236eSmrg#define LBStencil						GLINT_TAG_ADDR(0x11,0x05)
913c35d236eSmrg#define LBDepth							GLINT_TAG_ADDR(0x11,0x06)
914c35d236eSmrg#define LBWindowBase						GLINT_TAG_ADDR(0x11,0x07)
915c35d236eSmrg#define LBWriteMode						GLINT_TAG_ADDR(0x11,0x08)
916c35d236eSmrg#	define LBWM_WriteEnable				0x1
917c35d236eSmrg#	define LBWM_UpLoad_LBDepth				0x2
918c35d236eSmrg#	define LBWM_UpLoad_LBStencil				0x4
919c35d236eSmrg
920c35d236eSmrg#define LBWriteFormat						GLINT_TAG_ADDR(0x11,0x09)
921c35d236eSmrg
922c35d236eSmrg
923c35d236eSmrg#define TextureData						GLINT_TAG_ADDR(0x11,0x0d)
924c35d236eSmrg#define TextureDownloadOffset					GLINT_TAG_ADDR(0x11,0x0e)
925c35d236eSmrg#define LBWindowOffset						GLINT_TAG_ADDR(0x11,0x0f)
926c35d236eSmrg
927c35d236eSmrg#define GLINTWindow						GLINT_TAG_ADDR(0x13,0x00)
928c35d236eSmrg#	define GWIN_UnitEnable          (1 << 0)
929c35d236eSmrg#	define GWIN_ForceLBUpdate       (1 << 3)
930c35d236eSmrg#	define GWIN_LBUpdateSourceREG   (1 << 4)
931c35d236eSmrg#	define GWIN_LBUpdateSourceLB    (0 << 4)
932c35d236eSmrg#	define GWIN_StencilFCP          (1 << 17)
933c35d236eSmrg#	define GWIN_DepthFCP            (1 << 18)
934c35d236eSmrg#	define GWIN_OverrideWriteFilter (1 << 19)
935c35d236eSmrg
936c35d236eSmrg	/* ??? is this needed, set by permedia (2) modules */
937c35d236eSmrg#	define GWIN_DisableLBUpdate    0x40000
938c35d236eSmrg
939c35d236eSmrg#define StencilMode						GLINT_TAG_ADDR(0x13,0x01)
940c35d236eSmrg#define StencilData						GLINT_TAG_ADDR(0x13,0x02)
941c35d236eSmrg#define GLINTStencil						GLINT_TAG_ADDR(0x13,0x03)
942c35d236eSmrg#define DepthMode						GLINT_TAG_ADDR(0x13,0x04)
943c35d236eSmrg	/* 0:				*/
944c35d236eSmrg	/* WriteDisable			*/
945c35d236eSmrg	/* SrcCompFragment		*/
946c35d236eSmrg	/* CompFuncNEVER		*/
947c35d236eSmrg	/* UNIT_DISABLE			*/
948c35d236eSmrg
949c35d236eSmrg#	define DPM_WriteEnable					1 << 1
950c35d236eSmrg#	define DPM_SrcCompLBData				1 << 2
951c35d236eSmrg#	define DPM_SrcCompDregister				2 << 2
952c35d236eSmrg#	define DPM_SrcCompLBSourceData				3 << 2
953c35d236eSmrg#	define DPM_CompFuncLESS				1 << 4
954c35d236eSmrg#	define DPM_CompFuncEQUAL				2 << 4
955c35d236eSmrg#	define DPM_CompFuncLESS_OR_EQ				3 << 4
956c35d236eSmrg#	define DPM_CompFuncGREATER				4 << 4
957c35d236eSmrg#	define DPM_CompFuncNOT_EQ				5 << 4
958c35d236eSmrg#	define DPM_CompFuncGREATER_OR_EQ			6 << 4
959c35d236eSmrg#	define DPM_CompFuncALWAYS				7 << 4
960c35d236eSmrg
961c35d236eSmrg#define GLINTDepth						GLINT_TAG_ADDR(0x13,0x05)
962c35d236eSmrg#define ZStartU							GLINT_TAG_ADDR(0x13,0x06)
963c35d236eSmrg#define ZStartL							GLINT_TAG_ADDR(0x13,0x07)
964c35d236eSmrg#define dZdxU							GLINT_TAG_ADDR(0x13,0x08)
965c35d236eSmrg#define dZdxL							GLINT_TAG_ADDR(0x13,0x09)
966c35d236eSmrg#define dZdyDomU						GLINT_TAG_ADDR(0x13,0x0a)
967c35d236eSmrg#define dZdyDomL						GLINT_TAG_ADDR(0x13,0x0b)
968c35d236eSmrg#define FastClearDepth						GLINT_TAG_ADDR(0x13,0x0c)
969c35d236eSmrg
970c35d236eSmrg#define FBReadMode						GLINT_TAG_ADDR(0x15,0x00)
971c35d236eSmrg	/* 0:				*/
972c35d236eSmrg	/* SrcNoRead			*/
973c35d236eSmrg	/* DstNoRead			*/
974c35d236eSmrg	/* DataFBDefault		*/
975c35d236eSmrg	/* WinTopLeft			*/
976c35d236eSmrg	/* ScanlineInterval1 		*/
977c35d236eSmrg
978c35d236eSmrg#	define FBRM_SrcEnable					1 << 9
979c35d236eSmrg#	define FBRM_DstEnable					1 << 10
980c35d236eSmrg#	define FBRM_DataFBColor				1 << 15
981c35d236eSmrg#	define FBRM_WinBottomLeft				1 << 16
982c35d236eSmrg#	define FBRM_Packed					1 << 19
983c35d236eSmrg#	define FBRM_ScanlineInt2				1 << 23
984c35d236eSmrg#	define FBRM_ScanlineInt4				2 << 23
985c35d236eSmrg#	define FBRM_ScanlineInt8				3 << 23
986c35d236eSmrg
987c35d236eSmrg
988c35d236eSmrg#define FBSourceOffset						GLINT_TAG_ADDR(0x15,0x01)
989c35d236eSmrg#define FBPixelOffset						GLINT_TAG_ADDR(0x15,0x02)
990c35d236eSmrg#define FBColor							GLINT_TAG_ADDR(0x15,0x03)
991c35d236eSmrg#define FBData							GLINT_TAG_ADDR(0x15,0x04)
992c35d236eSmrg#define FBSourceData						GLINT_TAG_ADDR(0x15,0x05)
993c35d236eSmrg
994c35d236eSmrg#define FBWindowBase						GLINT_TAG_ADDR(0x15,0x06)
995c35d236eSmrg#define FBWriteMode						GLINT_TAG_ADDR(0x15,0x07)
996c35d236eSmrg	/* 0:			*/
997c35d236eSmrg	/* FBWM_NoColorUpload	*/
998c35d236eSmrg	/* FBWM_WriteDisable	*/
999c35d236eSmrg#	define FBWM_WriteEnable				1
1000c35d236eSmrg#	define FBWM_UploadColor				1 << 3
1001c35d236eSmrg/* Permedia3 extensions */
1002c35d236eSmrg#	define FBWM_Enable0					1 << 12
1003c35d236eSmrg
1004c35d236eSmrg#define FBHardwareWriteMask					GLINT_TAG_ADDR(0x15,0x08)
1005c35d236eSmrg#define FBBlockColor						GLINT_TAG_ADDR(0x15,0x09)
1006c35d236eSmrg#define FBReadPixel						GLINT_TAG_ADDR(0x15,0x0a) /* PM */
1007c35d236eSmrg#define PatternRamMode						GLINT_TAG_ADDR(0x15,0x0f)
1008c35d236eSmrg
1009c35d236eSmrg#define PatternRamData0						GLINT_TAG_ADDR(0x16,0x00)
1010c35d236eSmrg#define PatternRamData1						GLINT_TAG_ADDR(0x16,0x01)
1011c35d236eSmrg#define PatternRamData2						GLINT_TAG_ADDR(0x16,0x02)
1012c35d236eSmrg#define PatternRamData3						GLINT_TAG_ADDR(0x16,0x03)
1013c35d236eSmrg#define PatternRamData4						GLINT_TAG_ADDR(0x16,0x04)
1014c35d236eSmrg#define PatternRamData5						GLINT_TAG_ADDR(0x16,0x05)
1015c35d236eSmrg#define PatternRamData6						GLINT_TAG_ADDR(0x16,0x06)
1016c35d236eSmrg#define PatternRamData7						GLINT_TAG_ADDR(0x16,0x07)
1017c35d236eSmrg
1018c35d236eSmrg#define FilterMode						GLINT_TAG_ADDR(0x18,0x00)
1019c35d236eSmrg	/* 0:				*/
1020c35d236eSmrg	/* CullDepthTags		*/
1021c35d236eSmrg	/* CullDepthData		*/
1022c35d236eSmrg	/* CullStencilTags		*/
1023c35d236eSmrg	/* CullStencilData		*/
1024c35d236eSmrg	/* CullColorTag			*/
1025c35d236eSmrg	/* CullColorData		*/
1026c35d236eSmrg	/* CullSyncTag			*/
1027c35d236eSmrg	/* CullSyncData			*/
1028c35d236eSmrg	/* CullStatisticTag		*/
1029c35d236eSmrg	/* CullStatisticData		*/
1030c35d236eSmrg
1031c35d236eSmrg#	define FM_PassDepthTags					0x0010
1032c35d236eSmrg#	define FM_PassDepthData					0x0020
1033c35d236eSmrg#	define FM_PassStencilTags					0x0040
1034c35d236eSmrg#	define FM_PassStencilData					0x0080
1035c35d236eSmrg#	define FM_PassColorTag						0x0100
1036c35d236eSmrg#	define FM_PassColorData					0x0200
1037c35d236eSmrg#	define FM_PassSyncTag						0x0400
1038c35d236eSmrg#	define FM_PassSyncData						0x0800
1039c35d236eSmrg#	define FM_PassStatisticTag					0x1000
1040c35d236eSmrg#	define FM_PassStatisticData					0x2000
1041c35d236eSmrg
1042c35d236eSmrg#define	Sync_tag							0x0188
1043c35d236eSmrg
1044c35d236eSmrg#define StatisticMode						GLINT_TAG_ADDR(0x18,0x01)
1045c35d236eSmrg#define MinRegion						GLINT_TAG_ADDR(0x18,0x02)
1046c35d236eSmrg#define MaxRegion						GLINT_TAG_ADDR(0x18,0x03)
1047c35d236eSmrg#define ResetPickResult						GLINT_TAG_ADDR(0x18,0x04)
1048c35d236eSmrg#define MitHitRegion						GLINT_TAG_ADDR(0x18,0x05)
1049c35d236eSmrg#define MaxHitRegion						GLINT_TAG_ADDR(0x18,0x06)
1050c35d236eSmrg#define PickResult						GLINT_TAG_ADDR(0x18,0x07)
1051c35d236eSmrg#define GlintSync						GLINT_TAG_ADDR(0x18,0x08)
1052c35d236eSmrg
1053c35d236eSmrg#define FBBlockColorU						GLINT_TAG_ADDR(0x18,0x0d)
1054c35d236eSmrg#define FBBlockColorL						GLINT_TAG_ADDR(0x18,0x0e)
1055c35d236eSmrg#define SuspendUntilFrameBlank					GLINT_TAG_ADDR(0x18,0x0f)
1056c35d236eSmrg
1057c35d236eSmrg#define KsRStart						GLINT_TAG_ADDR(0x19,0x00)
1058c35d236eSmrg#define dKsRdx							GLINT_TAG_ADDR(0x19,0x01)
1059c35d236eSmrg#define dKsRdyDom						GLINT_TAG_ADDR(0x19,0x02)
1060c35d236eSmrg#define KsGStart						GLINT_TAG_ADDR(0x19,0x03)
1061c35d236eSmrg#define dKsGdx							GLINT_TAG_ADDR(0x19,0x04)
1062c35d236eSmrg#define dKsGdyDom						GLINT_TAG_ADDR(0x19,0x05)
1063c35d236eSmrg#define KsBStart						GLINT_TAG_ADDR(0x19,0x06)
1064c35d236eSmrg#define dKsBdx							GLINT_TAG_ADDR(0x19,0x07)
1065c35d236eSmrg#define dKsBdyDom						GLINT_TAG_ADDR(0x19,0x08)
1066c35d236eSmrg
1067c35d236eSmrg#define KdRStart						GLINT_TAG_ADDR(0x1A,0x00)
1068c35d236eSmrg#define dKdRdx							GLINT_TAG_ADDR(0x1A,0x01)
1069c35d236eSmrg#define dKdRdyDom						GLINT_TAG_ADDR(0x1A,0x02)
1070c35d236eSmrg#define KdGStart						GLINT_TAG_ADDR(0x1A,0x03)
1071c35d236eSmrg#define dKdGdx							GLINT_TAG_ADDR(0x1A,0x04)
1072c35d236eSmrg#define dKdGdyDom						GLINT_TAG_ADDR(0x1A,0x05)
1073c35d236eSmrg#define KdBStart						GLINT_TAG_ADDR(0x1A,0x06)
1074c35d236eSmrg#define dKdBdx							GLINT_TAG_ADDR(0x1A,0x07)
1075c35d236eSmrg#define dKdBdyDom						GLINT_TAG_ADDR(0x1A,0x08)
1076c35d236eSmrg
1077c35d236eSmrg#define FBSourceBase						GLINT_TAG_ADDR(0x1B,0x00)
1078c35d236eSmrg#define FBSourceDelta						GLINT_TAG_ADDR(0x1B,0x01)
1079c35d236eSmrg#define Config							GLINT_TAG_ADDR(0x1B,0x02)
1080c35d236eSmrg#define		CFBRM_SrcEnable		1<<0
1081c35d236eSmrg#define		CFBRM_DstEnable		1<<1
1082c35d236eSmrg#define		CFBRM_Packed		1<<2
1083c35d236eSmrg#define		CWM_Enable		1<<3
1084c35d236eSmrg#define		CCDDA_Enable		1<<4
1085c35d236eSmrg#define		CLogOp_Enable		1<<5
1086c35d236eSmrg#define ContextDump                                             GLINT_TAG_ADDR(0x1B,0x08)
1087c35d236eSmrg#define ContextRestore                                          GLINT_TAG_ADDR(0x1B,0x09)
1088c35d236eSmrg#define ContextData                                             GLINT_TAG_ADDR(0x1B,0x0a)
1089c35d236eSmrg
1090c35d236eSmrg#define TexelLUT0						GLINT_TAG_ADDR(0x1D,0x00)
1091c35d236eSmrg#define TexelLUT1						GLINT_TAG_ADDR(0x1D,0x01)
1092c35d236eSmrg#define TexelLUT2						GLINT_TAG_ADDR(0x1D,0x02)
1093c35d236eSmrg#define TexelLUT3						GLINT_TAG_ADDR(0x1D,0x03)
1094c35d236eSmrg#define TexelLUT4						GLINT_TAG_ADDR(0x1D,0x04)
1095c35d236eSmrg#define TexelLUT5						GLINT_TAG_ADDR(0x1D,0x05)
1096c35d236eSmrg#define TexelLUT6						GLINT_TAG_ADDR(0x1D,0x06)
1097c35d236eSmrg#define TexelLUT7						GLINT_TAG_ADDR(0x1D,0x07)
1098c35d236eSmrg#define TexelLUT8						GLINT_TAG_ADDR(0x1D,0x08)
1099c35d236eSmrg#define TexelLUT9						GLINT_TAG_ADDR(0x1D,0x09)
1100c35d236eSmrg#define TexelLUT10						GLINT_TAG_ADDR(0x1D,0x0A)
1101c35d236eSmrg#define TexelLUT11						GLINT_TAG_ADDR(0x1D,0x0B)
1102c35d236eSmrg#define TexelLUT12						GLINT_TAG_ADDR(0x1D,0x0C)
1103c35d236eSmrg#define TexelLUT13						GLINT_TAG_ADDR(0x1D,0x0D)
1104c35d236eSmrg#define TexelLUT14						GLINT_TAG_ADDR(0x1D,0x0E)
1105c35d236eSmrg#define TexelLUT15						GLINT_TAG_ADDR(0x1D,0x0F)
1106c35d236eSmrg
1107c35d236eSmrg#define YUVMode                                                 GLINT_TAG_ADDR(0x1E,0x00)
1108c35d236eSmrg#define ChromaUpper                                             GLINT_TAG_ADDR(0x1E,0x01)
1109c35d236eSmrg#define ChromaLower                                             GLINT_TAG_ADDR(0x1E,0x02)
1110c35d236eSmrg#define ChromaTestMode                                          GLINT_TAG_ADDR(0x1E,0x03)
1111c35d236eSmrg
1112c35d236eSmrg
1113c35d236eSmrg/******************************
1114c35d236eSmrg * GLINT Delta Core Registers *
1115c35d236eSmrg ******************************/
1116c35d236eSmrg
1117c35d236eSmrg#define V0FixedTag	GLINT_TAG_ADDR(0x20,0x00)
1118c35d236eSmrg#define V1FixedTag	GLINT_TAG_ADDR(0x21,0x00)
1119c35d236eSmrg#define V2FixedTag	GLINT_TAG_ADDR(0x22,0x00)
1120c35d236eSmrg#define V0FloatTag	GLINT_TAG_ADDR(0x23,0x00)
1121c35d236eSmrg#define V1FloatTag	GLINT_TAG_ADDR(0x24,0x00)
1122c35d236eSmrg#define V2FloatTag	GLINT_TAG_ADDR(0x25,0x00)
1123c35d236eSmrg
1124c35d236eSmrg#define VPAR_s		0x00
1125c35d236eSmrg#define VPAR_t		0x08
1126c35d236eSmrg#define VPAR_q		0x10
1127c35d236eSmrg#define VPAR_Ks		0x18
1128c35d236eSmrg#define VPAR_Kd		0x20
1129c35d236eSmrg
1130c35d236eSmrg/* have changed colors in ramdac !
1131c35d236eSmrg#define VPAR_R		0x28
1132c35d236eSmrg#define VPAR_G		0x30
1133c35d236eSmrg#define VPAR_B		0x38
1134c35d236eSmrg#define VPAR_A		0x40
1135c35d236eSmrg*/
1136c35d236eSmrg#define VPAR_B		0x28
1137c35d236eSmrg#define VPAR_G		0x30
1138c35d236eSmrg#define VPAR_R		0x38
1139c35d236eSmrg#define VPAR_A		0x40
1140c35d236eSmrg
1141c35d236eSmrg#define VPAR_f		0x48
1142c35d236eSmrg
1143c35d236eSmrg#define VPAR_x		0x50
1144c35d236eSmrg#define VPAR_y		0x58
1145c35d236eSmrg#define VPAR_z		0x60
1146c35d236eSmrg
1147c35d236eSmrg#define DeltaModeTag						GLINT_TAG_ADDR(0x26,0x00)
1148c35d236eSmrg	/* 0:				*/
1149c35d236eSmrg	/* GLINT_300SX			*/
1150c35d236eSmrg
1151c35d236eSmrg	/* DeltaMode Register Bit Field Assignments */
1152c35d236eSmrg#	define DM_GLINT_300SX					0x0000
1153c35d236eSmrg#	define DM_GLINT_500TX					0x0001
1154c35d236eSmrg#	define DM_PERMEDIA					0x0002
1155c35d236eSmrg#	define DM_Depth_16BPP					(1 << 2)
1156c35d236eSmrg#	define DM_Depth_24BPP					(2 << 2)
1157c35d236eSmrg#	define DM_Depth_32BPP					(3 << 2)
1158c35d236eSmrg#	define DM_FogEnable					0x0010
1159c35d236eSmrg#	define DM_TextureEnable				0x0020
1160c35d236eSmrg#	define DM_SmoothShadingEnable				0x0040
1161c35d236eSmrg#	define DM_DepthEnable					0x0080
1162c35d236eSmrg#	define DM_SpecularTextureEnable			0x0100
1163c35d236eSmrg#	define DM_DiffuseTextureEnable				0x0200
1164c35d236eSmrg#	define DM_SubPixelCorrectionEnable			0x0400
1165c35d236eSmrg#	define DM_DiamondExit					0x0800
1166c35d236eSmrg#	define DM_NoDraw					0x1000
1167c35d236eSmrg#	define DM_ClampEnable					0x2000
1168c35d236eSmrg#	define DM_ClampedTexParMode				0x4000
1169c35d236eSmrg#	define DM_NormalizedTexParMode				0xC000
1170c35d236eSmrg
1171c35d236eSmrg
1172c35d236eSmrg#	define DDCMD_AreaStrippleEnable                        0x0001
1173c35d236eSmrg#	define DDCMD_LineStrippleEnable                        0x0002
1174c35d236eSmrg#	define DDCMD_ResetLineStripple                         1 << 2
1175c35d236eSmrg#	define DDCMD_FastFillEnable                            1 << 3
1176c35d236eSmrg        /*  2 Bits reserved */
1177c35d236eSmrg#	define DDCMD_PrimitiveType_Point                       2 << 6
1178c35d236eSmrg#	define DDCMD_PrimitiveType_Line                        0 << 6
1179c35d236eSmrg#	define DDCMD_PrimitiveType_Trapezoid                   1 << 6
1180c35d236eSmrg#	define DDCMD_AntialiasEnable				1 << 8
1181c35d236eSmrg#	define DDCMD_AntialiasingQuality			1 << 9
1182c35d236eSmrg#	define DDCMD_UsePointTable                             1 << 10
1183c35d236eSmrg#	define DDCMD_SyncOnBitMask                             1 << 11
1184c35d236eSmrg#	define DDCMD_SyncOnHostDate                            1 << 12
1185c35d236eSmrg#	define DDCMD_TextureEnable			        1 << 13
1186c35d236eSmrg#	define DDCMD_FogEnable                                 1 << 14
1187c35d236eSmrg#	define DDCMD_CoverageEnable                            1 << 15
1188c35d236eSmrg#	define DDCMD_SubPixelCorrectionEnable                  1 << 16
1189c35d236eSmrg
1190c35d236eSmrg
1191c35d236eSmrg
1192c35d236eSmrg#define DrawTriangle						GLINT_TAG_ADDR(0x26,0x01)
1193c35d236eSmrg#define RepeatTriangle						GLINT_TAG_ADDR(0x26,0x02)
1194c35d236eSmrg#define DrawLine01						GLINT_TAG_ADDR(0x26,0x03)
1195c35d236eSmrg#define DrawLine10						GLINT_TAG_ADDR(0x26,0x04)
1196c35d236eSmrg#define RepeatLine						GLINT_TAG_ADDR(0x26,0x05)
1197c35d236eSmrg#define BroadcastMask						GLINT_TAG_ADDR(0x26,0x0F)
1198c35d236eSmrg
1199c35d236eSmrg/* Permedia 3 - Accelerator Extensions */
1200c35d236eSmrg#define FillRectanglePosition					0x8348
1201c35d236eSmrg#define FillRender2D						0x8350
1202c35d236eSmrg#define FBDstReadBufAddr0					0xAE80
1203c35d236eSmrg#define FBDstReadBufOffset0					0xAEA0
1204c35d236eSmrg#define FBDstReadBufWidth0					0xAEC0
1205c35d236eSmrg#define FBDstReadMode						0xAEE0
1206c35d236eSmrg#define		FBDRM_Enable0		1<<8
1207c35d236eSmrg#define		FBDRM_Blocking		1<<24
1208c35d236eSmrg#define FBDstReadEnables					0xAEE8
1209c35d236eSmrg#define FBSrcReadMode						0xAF00
1210c35d236eSmrg#define		FBSRM_Blocking		1<<11
1211c35d236eSmrg#define FBSrcReadBufAddr					0xAF08
1212c35d236eSmrg#define FBSrcReadBufOffset0					0xAF10
1213c35d236eSmrg#define FBSrcReadBufWidth					0xAF18
1214c35d236eSmrg#define FBWriteBufAddr0						0xB000
1215c35d236eSmrg#define FBWriteBufOffset0					0xB020
1216c35d236eSmrg#define FBWriteBufWidth0					0xB040
1217c35d236eSmrg#define FBBlockColorBack					0xB0A0
1218c35d236eSmrg#define ForegroundColor						0xB0C0
1219c35d236eSmrg#define BackgroundColor						0xB0C8
1220c35d236eSmrg#define RectanglePosition					0xB600
1221c35d236eSmrg#define Render2D						0xB640
1222c35d236eSmrg
1223c35d236eSmrg/*  Colorformats */
1224c35d236eSmrg#define BGR555  1
1225c35d236eSmrg#define BGR565  16
1226c35d236eSmrg#define CI8     14
1227c35d236eSmrg#define CI4     15
1228c35d236eSmrg
1229c35d236eSmrg#ifdef DEBUG
1230c35d236eSmrg#define GLINT_WRITE_REG(v,r)					\
1231c35d236eSmrg	GLINT_VERB_WRITE_REG(pGlint,v,r,__FILE__,__LINE__)
1232c35d236eSmrg#define GLINT_READ_REG(r)					\
1233c35d236eSmrg	GLINT_VERB_READ_REG(pGlint,r,__FILE__,__LINE__)
1234c35d236eSmrg#else
1235c35d236eSmrg
1236c35d236eSmrg#define GLINT_WRITE_REG(v,r) \
1237c35d236eSmrg	MMIO_OUT32(pGlint->IOBase + pGlint->IOOffset,(unsigned long)(r), (v))
1238c35d236eSmrg#define GLINT_READ_REG(r) \
1239c35d236eSmrg	MMIO_IN32(pGlint->IOBase + pGlint->IOOffset,(unsigned long)(r))
1240c35d236eSmrg
1241c35d236eSmrg#endif /* DEBUG */
1242c35d236eSmrg
1243c35d236eSmrg#define GLINT_WAIT(n)						\
1244c35d236eSmrgdo{								\
1245c35d236eSmrg	if (pGlint->InFifoSpace>=(n))				\
1246c35d236eSmrg	    pGlint->InFifoSpace -= (n);				\
1247c35d236eSmrg	else {							\
1248c35d236eSmrg	    int tmp;						\
1249c35d236eSmrg	    while((tmp=GLINT_READ_REG(InFIFOSpace))<(n));	\
1250c35d236eSmrg	    /* Clamp value due to bugs in PM3 */		\
1251c35d236eSmrg	    if (tmp > pGlint->FIFOSize)				\
1252c35d236eSmrg		tmp = pGlint->FIFOSize;				\
1253c35d236eSmrg	    pGlint->InFifoSpace = tmp - (n);			\
1254c35d236eSmrg	}							\
1255c35d236eSmrg}while(0)
1256c35d236eSmrg
1257c35d236eSmrg#define GLINTDACDelay(x) do {                                   \
1258c35d236eSmrg        int delay = x;                                          \
12594f6cd06fSmrg        unsigned char tmp;                                      \
12604f6cd06fSmrg	while(delay--){tmp = GLINT_READ_REG(InFIFOSpace);};     \
1261c35d236eSmrg	} while(0)
1262c35d236eSmrg
1263c35d236eSmrg#define GLINT_MASK_WRITE_REG(v,m,r)				\
1264c35d236eSmrg	GLINT_WRITE_REG((GLINT_READ_REG(r)&(m))|(v),r)
1265c35d236eSmrg
1266c35d236eSmrg#define GLINT_SLOW_WRITE_REG(v,r)				\
1267c35d236eSmrgdo{								\
1268c35d236eSmrg	mem_barrier();						\
1269c35d236eSmrg	GLINT_WAIT(pGlint->FIFOSize);		     		\
1270c35d236eSmrg	mem_barrier();						\
1271c35d236eSmrg        GLINT_WRITE_REG(v,r);					\
1272c35d236eSmrg}while(0)
1273c35d236eSmrg
1274c35d236eSmrg#define GLINT_SET_INDEX(index)					\
1275c35d236eSmrgdo{								\
1276c35d236eSmrg	GLINT_SLOW_WRITE_REG(((index)>>8)&0xff,PM2VDACIndexRegHigh);	\
1277c35d236eSmrg	GLINT_SLOW_WRITE_REG((index)&0xff,PM2VDACIndexRegLow);	\
1278c35d236eSmrg} while(0)
1279c35d236eSmrg
1280c35d236eSmrg#define REPLICATE(r)						\
1281c35d236eSmrg{								\
1282c35d236eSmrg	if (pScrn->bitsPerPixel == 16) {			\
1283c35d236eSmrg		r &= 0xFFFF;					\
1284c35d236eSmrg		r |= (r<<16);					\
1285c35d236eSmrg	} else							\
1286c35d236eSmrg	if (pScrn->bitsPerPixel == 8) { 			\
1287c35d236eSmrg		r &= 0xFF;					\
1288c35d236eSmrg		r |= (r<<8);					\
1289c35d236eSmrg		r |= (r<<16);					\
1290c35d236eSmrg	}							\
1291c35d236eSmrg}
1292c35d236eSmrg
1293c35d236eSmrg#define LOADROP(rop)						\
1294c35d236eSmrg{								\
1295c35d236eSmrg	if (pGlint->ROP != rop)	{				\
1296c35d236eSmrg		GLINT_WRITE_REG(rop<<1|UNIT_ENABLE, LogicalOpMode);	\
1297c35d236eSmrg		pGlint->ROP = rop;				\
1298c35d236eSmrg	}							\
1299c35d236eSmrg}
13001fb744b4Smrg
1301c35d236eSmrg#define CHECKCLIPPING						\
1302c35d236eSmrg{								\
1303c35d236eSmrg	if (pGlint->ClippingOn) {				\
1304c35d236eSmrg		pGlint->ClippingOn = FALSE;			\
1305c35d236eSmrg		GLINT_WAIT(1);					\
1306c35d236eSmrg		GLINT_WRITE_REG(0, ScissorMode);		\
1307c35d236eSmrg	}							\
1308c35d236eSmrg}
1309c35d236eSmrg
1310a3890ad9Smacallan#define DO_PLANEMASK(p)						\
1311c35d236eSmrg{ 								\
1312a3890ad9Smacallan	if (p != pGlint->planemask) {				\
1313a3890ad9Smacallan		CARD32 pm = p;					\
1314a3890ad9Smacallan		pGlint->planemask = p;				\
1315a3890ad9Smacallan		REPLICATE(pm); 					\
1316a3890ad9Smacallan		GLINT_WRITE_REG(pm, FBHardwareWriteMask);	\
1317c35d236eSmrg	}							\
1318c35d236eSmrg}
1319c35d236eSmrg
1320c35d236eSmrg/* Permedia Save/Restore functions */
1321c35d236eSmrg
1322c35d236eSmrg#define STOREREG(address,value) 				\
1323c35d236eSmrg    	pReg->glintRegs[address >> 3] = value;
1324c35d236eSmrg
1325c35d236eSmrg#define SAVEREG(address) 					\
1326c35d236eSmrg    	pReg->glintRegs[address >> 3] = GLINT_READ_REG(address);
1327c35d236eSmrg
1328c35d236eSmrg#define RESTOREREG(address) 					\
1329c35d236eSmrg    	GLINT_SLOW_WRITE_REG(pReg->glintRegs[address >> 3], address);
1330c35d236eSmrg
1331c35d236eSmrg#define STOREDAC(address,value)					\
1332c35d236eSmrg    	pReg->DacRegs[address] = value;
1333c35d236eSmrg
1334c35d236eSmrg#define P2VOUT(address)						\
1335c35d236eSmrg    Permedia2vOutIndReg(pScrn, address, 0x00, pReg->DacRegs[address]);
1336c35d236eSmrg
1337c35d236eSmrg#define P2VIN(address)						\
1338c35d236eSmrg    pReg->DacRegs[address] = Permedia2vInIndReg(pScrn, address);
1339c35d236eSmrg
1340c35d236eSmrg/* RamDac Save/Restore functions, used by external DAC's */
1341c35d236eSmrg
1342c35d236eSmrg#define STORERAMDAC(address,value)				\
1343c35d236eSmrg    	ramdacReg->DacRegs[address] = value;
1344c35d236eSmrg
1345c35d236eSmrg/* Multi Chip access */
1346c35d236eSmrg
1347c35d236eSmrg#define ACCESSCHIP1()						\
1348c35d236eSmrg    pGlint->IOOffset = 0;
1349c35d236eSmrg
1350c35d236eSmrg#define ACCESSCHIP2()						\
1351c35d236eSmrg    pGlint->IOOffset = 0x10000;
1352c35d236eSmrg
1353c35d236eSmrg#endif
1354