i128init.c revision 50806d53
1/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/i128/i128init.c,v 1.5 2000/11/03 00:50:53 robin Exp $ */ 2/* 3 * Copyright 1995-2000 by Robin Cutshaw <robin@XFree86.Org> 4 * Copyright 1998 by Number Nine Visual Technology, Inc. 5 * 6 * Permission to use, copy, modify, distribute, and sell this software and its 7 * documentation for any purpose is hereby granted without fee, provided that 8 * the above copyright notice appear in all copies and that both that 9 * copyright notice and this permission notice appear in supporting 10 * documentation, and that the name of Robin Cutshaw not be used in 11 * advertising or publicity pertaining to distribution of the software without 12 * specific, written prior permission. Robin Cutshaw and Number Nine make no 13 * representations about the suitability of this software for any purpose. It 14 * is provided "as is" without express or implied warranty. 15 * 16 * ROBIN CUTSHAW AND NUMBER NINE DISCLAIM ALL WARRANTIES WITH REGARD TO THIS 17 * SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND 18 * FITNESS, IN NO EVENT SHALL ROBIN CUTSHAW OR NUMBER NINE BE LIABLE FOR 19 * ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 20 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN 21 * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING 22 * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 23 * 24 */ 25 26#ifdef HAVE_CONFIG_H 27#include "config.h" 28#endif 29 30/* $XConsortium: $ */ 31 32 33#include "xf86.h" 34#include "xf86_ansic.h" 35#include "xf86PciInfo.h" 36#include "xf86Pci.h" 37 38#include "i128.h" 39#include "i128reg.h" 40#include "Ti302X.h" 41#include "IBMRGB.h" 42 43static void I128SavePalette(I128Ptr pI128); 44static void I128RestorePalette(I128Ptr pI128); 45 46 47void 48I128SaveState(ScrnInfoPtr pScrn) 49{ 50 I128Ptr pI128 = I128PTR(pScrn); 51 I128RegPtr iR = &pI128->RegRec; 52 53 if (pI128->Debug) 54 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "I128SaveState start\n"); 55 56 if (pI128->Debug) { 57 unsigned long tmp1 = inl(iR->iobase + 0x1C); 58 unsigned long tmp2 = inl(iR->iobase + 0x20); 59 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "I128SaveState saving, config1/2 = 0x%lx/0x%lx\n", tmp1, tmp2); 60 I128DumpActiveRegisters(pScrn); 61 } 62 63 /* iobase is filled in during the device probe (as well as config 1&2)*/ 64 65 if ((pI128->io.id&0x7) > 0) { 66 iR->vga_ctl = inl(iR->iobase + 0x30); 67 } 68 69 iR->i128_base_g[INT_VCNT] = pI128->mem.rbase_g[INT_VCNT]; /* 0x0020 */ 70 iR->i128_base_g[INT_HCNT] = pI128->mem.rbase_g[INT_HCNT]; /* 0x0024 */ 71 iR->i128_base_g[DB_ADR] = pI128->mem.rbase_g[DB_ADR]; /* 0x0028 */ 72 iR->i128_base_g[DB_PTCH] = pI128->mem.rbase_g[DB_PTCH]; /* 0x002C */ 73 iR->i128_base_g[CRT_HAC] = pI128->mem.rbase_g[CRT_HAC]; /* 0x0030 */ 74 iR->i128_base_g[CRT_HBL] = pI128->mem.rbase_g[CRT_HBL]; /* 0x0034 */ 75 iR->i128_base_g[CRT_HFP] = pI128->mem.rbase_g[CRT_HFP]; /* 0x0038 */ 76 iR->i128_base_g[CRT_HS] = pI128->mem.rbase_g[CRT_HS]; /* 0x003C */ 77 iR->i128_base_g[CRT_VAC] = pI128->mem.rbase_g[CRT_VAC]; /* 0x0040 */ 78 iR->i128_base_g[CRT_VBL] = pI128->mem.rbase_g[CRT_VBL]; /* 0x0044 */ 79 iR->i128_base_g[CRT_VFP] = pI128->mem.rbase_g[CRT_VFP]; /* 0x0048 */ 80 iR->i128_base_g[CRT_VS] = pI128->mem.rbase_g[CRT_VS]; /* 0x004C */ 81 iR->i128_base_g[CRT_LCNT] = pI128->mem.rbase_g[CRT_LCNT]; /* 0x0050 */ 82 iR->i128_base_g[CRT_ZOOM] = pI128->mem.rbase_g[CRT_ZOOM]; /* 0x0054 */ 83 iR->i128_base_g[CRT_1CON] = pI128->mem.rbase_g[CRT_1CON]; /* 0x0058 */ 84 iR->i128_base_g[CRT_2CON] = pI128->mem.rbase_g[CRT_2CON]; /* 0x005C */ 85 86 iR->i128_base_w[MW0_CTRL] = pI128->mem.rbase_w[MW0_CTRL]; /* 0x0000 */ 87 iR->i128_base_w[MW0_SZ] = pI128->mem.rbase_w[MW0_SZ]; /* 0x0008 */ 88 iR->i128_base_w[MW0_PGE] = pI128->mem.rbase_w[MW0_PGE]; /* 0x000C */ 89 iR->i128_base_w[MW0_ORG] = pI128->mem.rbase_w[MW0_ORG]; /* 0x0010 */ 90 iR->i128_base_w[MW0_MSRC] = pI128->mem.rbase_w[MW0_MSRC]; /* 0x0018 */ 91 iR->i128_base_w[MW0_WKEY] = pI128->mem.rbase_w[MW0_WKEY]; /* 0x001C */ 92 iR->i128_base_w[MW0_KDAT] = pI128->mem.rbase_w[MW0_KDAT]; /* 0x0020 */ 93 iR->i128_base_w[MW0_MASK] = pI128->mem.rbase_w[MW0_MASK]; /* 0x0024 */ 94 95 if (pI128->RamdacType == TI3025_DAC) { 96 pI128->mem.rbase_g[INDEX_TI] = TI_CURS_CONTROL; MB; 97 iR->Ti302X[TI_CURS_CONTROL] = pI128->mem.rbase_g[DATA_TI]; 98 pI128->mem.rbase_g[INDEX_TI] = TI_TRUE_COLOR_CONTROL; MB; 99 iR->Ti302X[TI_TRUE_COLOR_CONTROL] = pI128->mem.rbase_g[DATA_TI]; 100 pI128->mem.rbase_g[INDEX_TI] = TI_VGA_SWITCH_CONTROL; MB; 101 iR->Ti302X[TI_VGA_SWITCH_CONTROL] = pI128->mem.rbase_g[DATA_TI]; 102 pI128->mem.rbase_g[INDEX_TI] = TI_MUX_CONTROL_1; MB; 103 iR->Ti302X[TI_MUX_CONTROL_1] = pI128->mem.rbase_g[DATA_TI]; 104 pI128->mem.rbase_g[INDEX_TI] = TI_MUX_CONTROL_2; MB; 105 iR->Ti302X[TI_MUX_CONTROL_2] = pI128->mem.rbase_g[DATA_TI]; 106 pI128->mem.rbase_g[INDEX_TI] = TI_INPUT_CLOCK_SELECT; MB; 107 iR->Ti302X[TI_INPUT_CLOCK_SELECT] = pI128->mem.rbase_g[DATA_TI]; 108 pI128->mem.rbase_g[INDEX_TI] = TI_OUTPUT_CLOCK_SELECT; MB; 109 iR->Ti302X[TI_OUTPUT_CLOCK_SELECT] = pI128->mem.rbase_g[DATA_TI]; 110 pI128->mem.rbase_g[INDEX_TI] = TI_PALETTE_PAGE; MB; 111 iR->Ti302X[TI_PALETTE_PAGE] = pI128->mem.rbase_g[DATA_TI]; 112 pI128->mem.rbase_g[INDEX_TI] = TI_GENERAL_CONTROL; MB; 113 iR->Ti302X[TI_GENERAL_CONTROL] = pI128->mem.rbase_g[DATA_TI]; 114 pI128->mem.rbase_g[INDEX_TI] = TI_MISC_CONTROL; MB; 115 iR->Ti302X[TI_MISC_CONTROL] = pI128->mem.rbase_g[DATA_TI]; 116 pI128->mem.rbase_g[INDEX_TI] = TI_AUXILIARY_CONTROL; MB; 117 iR->Ti302X[TI_AUXILIARY_CONTROL] = pI128->mem.rbase_g[DATA_TI]; 118 pI128->mem.rbase_g[INDEX_TI] = TI_GENERAL_IO_CONTROL; MB; 119 iR->Ti302X[TI_GENERAL_IO_CONTROL] = pI128->mem.rbase_g[DATA_TI]; 120 pI128->mem.rbase_g[INDEX_TI] = TI_GENERAL_IO_DATA; MB; 121 iR->Ti302X[TI_GENERAL_IO_DATA] = pI128->mem.rbase_g[DATA_TI]; 122 pI128->mem.rbase_g[INDEX_TI] = TI_MCLK_DCLK_CONTROL; MB; 123 iR->Ti302X[TI_MCLK_DCLK_CONTROL] = pI128->mem.rbase_g[DATA_TI]; 124 pI128->mem.rbase_g[INDEX_TI] = TI_COLOR_KEY_CONTROL; MB; 125 iR->Ti302X[TI_COLOR_KEY_CONTROL] = pI128->mem.rbase_g[DATA_TI]; 126 127 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; 128 pI128->mem.rbase_g[DATA_TI] = 0x00; MB; 129 pI128->mem.rbase_g[INDEX_TI] = TI_PIXEL_CLOCK_PLL_DATA; MB; 130 iR->Ti3025[0] = pI128->mem.rbase_g[DATA_TI]; 131 132 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; 133 pI128->mem.rbase_g[DATA_TI] = 0x01; MB; 134 pI128->mem.rbase_g[INDEX_TI] = TI_PIXEL_CLOCK_PLL_DATA; MB; 135 iR->Ti3025[1] = pI128->mem.rbase_g[DATA_TI]; 136 137 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; 138 pI128->mem.rbase_g[DATA_TI] = 0x02; MB; 139 pI128->mem.rbase_g[INDEX_TI] = TI_PIXEL_CLOCK_PLL_DATA; MB; 140 iR->Ti3025[2] = pI128->mem.rbase_g[DATA_TI]; 141 142 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; 143 pI128->mem.rbase_g[DATA_TI] = 0x00; MB; 144 pI128->mem.rbase_g[INDEX_TI] = TI_MCLK_PLL_DATA; MB; 145 iR->Ti3025[3] = pI128->mem.rbase_g[DATA_TI]; 146 147 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; 148 pI128->mem.rbase_g[DATA_TI] = 0x01; MB; 149 pI128->mem.rbase_g[INDEX_TI] = TI_MCLK_PLL_DATA; MB; 150 iR->Ti3025[4] = pI128->mem.rbase_g[DATA_TI]; 151 152 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; 153 pI128->mem.rbase_g[DATA_TI] = 0x02; MB; 154 pI128->mem.rbase_g[INDEX_TI] = TI_MCLK_PLL_DATA; MB; 155 iR->Ti3025[5] = pI128->mem.rbase_g[DATA_TI]; 156 157 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; 158 pI128->mem.rbase_g[DATA_TI] = 0x00; MB; 159 pI128->mem.rbase_g[INDEX_TI] = TI_LOOP_CLOCK_PLL_DATA; MB; 160 iR->Ti3025[6] = pI128->mem.rbase_g[DATA_TI]; 161 162 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; 163 pI128->mem.rbase_g[DATA_TI] = 0x01; MB; 164 pI128->mem.rbase_g[INDEX_TI] = TI_LOOP_CLOCK_PLL_DATA; MB; 165 iR->Ti3025[7] = pI128->mem.rbase_g[DATA_TI]; 166 167 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; 168 pI128->mem.rbase_g[DATA_TI] = 0x02; MB; 169 pI128->mem.rbase_g[INDEX_TI] = TI_LOOP_CLOCK_PLL_DATA; MB; 170 iR->Ti3025[8] = pI128->mem.rbase_g[DATA_TI]; 171 } else if ((pI128->RamdacType == IBM526_DAC) || 172 (pI128->RamdacType == IBM528_DAC) || 173 (pI128->RamdacType == SILVER_HAMMER_DAC)) { 174 CARD32 i; 175 176 for (i=0; i<0x94; i++) { 177 pI128->mem.rbase_g[IDXL_I] = i; MB; 178 iR->IBMRGB[i] = pI128->mem.rbase_g[DATA_I]; 179 } 180 } 181 182 I128SavePalette(pI128); 183 184 if (pI128->Debug) 185 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "I128SaveState complete\n"); 186 187} 188 189 190void 191I128RestoreState(ScrnInfoPtr pScrn) 192{ 193 I128Ptr pI128 = I128PTR(pScrn); 194 I128RegPtr iR = &pI128->RegRec; 195 196 if (pI128->Debug) 197 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "I128RestoreState start\n"); 198 199 if (pI128->RamdacType == TI3025_DAC) { 200 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; 201 pI128->mem.rbase_g[DATA_TI] = 0x00; MB; 202 pI128->mem.rbase_g[INDEX_TI] = TI_PIXEL_CLOCK_PLL_DATA; MB; 203 pI128->mem.rbase_g[DATA_TI] = iR->Ti3025[0]; MB; 204 205 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; 206 pI128->mem.rbase_g[DATA_TI] = 0x01; MB; 207 pI128->mem.rbase_g[INDEX_TI] = TI_PIXEL_CLOCK_PLL_DATA; MB; 208 pI128->mem.rbase_g[DATA_TI] = iR->Ti3025[1]; MB; 209 210 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; 211 pI128->mem.rbase_g[DATA_TI] = 0x02; MB; 212 pI128->mem.rbase_g[INDEX_TI] = TI_PIXEL_CLOCK_PLL_DATA; MB; 213 pI128->mem.rbase_g[DATA_TI] = iR->Ti3025[2]; MB; 214 215 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; 216 pI128->mem.rbase_g[DATA_TI] = 0x00; MB; 217 pI128->mem.rbase_g[INDEX_TI] = TI_MCLK_PLL_DATA; MB; 218 pI128->mem.rbase_g[DATA_TI] = iR->Ti3025[3]; MB; 219 220 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; 221 pI128->mem.rbase_g[DATA_TI] = 0x01; MB; 222 pI128->mem.rbase_g[INDEX_TI] = TI_MCLK_PLL_DATA; MB; 223 pI128->mem.rbase_g[DATA_TI] = iR->Ti3025[4]; MB; 224 225 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; 226 pI128->mem.rbase_g[DATA_TI] = 0x02; MB; 227 pI128->mem.rbase_g[INDEX_TI] = TI_MCLK_PLL_DATA; MB; 228 pI128->mem.rbase_g[DATA_TI] = iR->Ti3025[5]; MB; 229 230 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; 231 pI128->mem.rbase_g[DATA_TI] = 0x00; MB; 232 pI128->mem.rbase_g[INDEX_TI] = TI_LOOP_CLOCK_PLL_DATA; MB; 233 pI128->mem.rbase_g[DATA_TI] = iR->Ti3025[6]; MB; 234 235 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; 236 pI128->mem.rbase_g[DATA_TI] = 0x01; MB; 237 pI128->mem.rbase_g[INDEX_TI] = TI_LOOP_CLOCK_PLL_DATA; MB; 238 pI128->mem.rbase_g[DATA_TI] = iR->Ti3025[7]; MB; 239 240 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB; 241 pI128->mem.rbase_g[DATA_TI] = 0x02; MB; 242 pI128->mem.rbase_g[INDEX_TI] = TI_LOOP_CLOCK_PLL_DATA; MB; 243 pI128->mem.rbase_g[DATA_TI] = iR->Ti3025[8]; MB; 244 245 pI128->mem.rbase_g[INDEX_TI] = TI_CURS_CONTROL; MB; 246 pI128->mem.rbase_g[DATA_TI] = iR->Ti302X[TI_CURS_CONTROL];MB; 247 pI128->mem.rbase_g[INDEX_TI] = TI_TRUE_COLOR_CONTROL; MB; 248 pI128->mem.rbase_g[DATA_TI] = iR->Ti302X[TI_TRUE_COLOR_CONTROL]; MB; 249 pI128->mem.rbase_g[INDEX_TI] = TI_VGA_SWITCH_CONTROL; MB; 250 pI128->mem.rbase_g[DATA_TI] = iR->Ti302X[TI_VGA_SWITCH_CONTROL]; MB; 251 pI128->mem.rbase_g[INDEX_TI] = TI_MUX_CONTROL_1; MB; 252 pI128->mem.rbase_g[DATA_TI] = iR->Ti302X[TI_MUX_CONTROL_1];MB; 253 pI128->mem.rbase_g[INDEX_TI] = TI_MUX_CONTROL_2; MB; 254 pI128->mem.rbase_g[DATA_TI] = iR->Ti302X[TI_MUX_CONTROL_2];MB; 255 pI128->mem.rbase_g[INDEX_TI] = TI_INPUT_CLOCK_SELECT; MB; 256 pI128->mem.rbase_g[DATA_TI] = iR->Ti302X[TI_INPUT_CLOCK_SELECT]; MB; 257 pI128->mem.rbase_g[INDEX_TI] = TI_OUTPUT_CLOCK_SELECT; MB; 258 pI128->mem.rbase_g[DATA_TI] = iR->Ti302X[TI_OUTPUT_CLOCK_SELECT];MB; 259 pI128->mem.rbase_g[INDEX_TI] = TI_PALETTE_PAGE; MB; 260 pI128->mem.rbase_g[DATA_TI] = iR->Ti302X[TI_PALETTE_PAGE];MB; 261 pI128->mem.rbase_g[INDEX_TI] = TI_GENERAL_CONTROL; MB; 262 pI128->mem.rbase_g[DATA_TI] = iR->Ti302X[TI_GENERAL_CONTROL]; MB; 263 pI128->mem.rbase_g[INDEX_TI] = TI_MISC_CONTROL; MB; 264 pI128->mem.rbase_g[DATA_TI] = iR->Ti302X[TI_MISC_CONTROL];MB; 265 pI128->mem.rbase_g[INDEX_TI] = TI_AUXILIARY_CONTROL; MB; 266 pI128->mem.rbase_g[DATA_TI] = iR->Ti302X[TI_AUXILIARY_CONTROL]; MB; 267 pI128->mem.rbase_g[INDEX_TI] = TI_GENERAL_IO_CONTROL; MB; 268 pI128->mem.rbase_g[DATA_TI] = iR->Ti302X[TI_GENERAL_IO_CONTROL]; MB; 269 pI128->mem.rbase_g[INDEX_TI] = TI_GENERAL_IO_DATA; MB; 270 pI128->mem.rbase_g[DATA_TI] = iR->Ti302X[TI_GENERAL_IO_DATA]; MB; 271 pI128->mem.rbase_g[INDEX_TI] = TI_MCLK_DCLK_CONTROL; MB; 272 pI128->mem.rbase_g[DATA_TI] = iR->Ti302X[TI_MCLK_DCLK_CONTROL]; MB; 273 pI128->mem.rbase_g[INDEX_TI] = TI_COLOR_KEY_CONTROL; MB; 274 pI128->mem.rbase_g[DATA_TI] = iR->Ti302X[TI_COLOR_KEY_CONTROL]; MB; 275 } else if ((pI128->RamdacType == IBM526_DAC) || 276 (pI128->RamdacType == IBM528_DAC) || 277 (pI128->RamdacType == SILVER_HAMMER_DAC)) { 278 CARD32 i; 279 280 if (pI128->Debug) { 281 unsigned long tmp1 = inl(iR->iobase + 0x1C); 282 unsigned long tmp2 = inl(iR->iobase + 0x20); 283 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "I128RestoreState restoring, config1/2 = 0x%lx/0x%lx\n", tmp1, tmp2); 284 I128DumpActiveRegisters(pScrn); 285 } 286 287 for (i=0; i<0x94; i++) { 288 if ((i == IBMRGB_sysclk_vco_div) || 289 (i == IBMRGB_sysclk_ref_div)) 290 continue; 291 pI128->mem.rbase_g[IDXL_I] = i; MB; 292 pI128->mem.rbase_g[DATA_I] = iR->IBMRGB[i]; MB; 293 } 294 295 pI128->mem.rbase_g[IDXL_I] = IBMRGB_sysclk_ref_div; MB; 296 pI128->mem.rbase_g[DATA_I] = 297 iR->IBMRGB[IBMRGB_sysclk_ref_div]; MB; 298 pI128->mem.rbase_g[IDXL_I] = IBMRGB_sysclk_vco_div; MB; 299 pI128->mem.rbase_g[DATA_I] = 300 iR->IBMRGB[IBMRGB_sysclk_vco_div]; MB; 301 usleep(50000); 302 } 303 304 /* iobase is filled in during the device probe (as well as config 1&2)*/ 305 306 if (((pI128->io.id&0x7) > 0) || 307 (pI128->Chipset == PCI_CHIP_I128_T2R) || 308 (pI128->Chipset == PCI_CHIP_I128_T2R4)) { 309 outl(iR->iobase + 0x30, iR->vga_ctl); 310 } 311 312 I128RestorePalette(pI128); 313 314 pI128->mem.rbase_w[MW0_CTRL] = iR->i128_base_w[MW0_CTRL]; /* 0x0000 */ 315 pI128->mem.rbase_w[MW0_SZ] = iR->i128_base_w[MW0_SZ]; /* 0x0008 */ 316 pI128->mem.rbase_w[MW0_PGE] = iR->i128_base_w[MW0_PGE]; /* 0x000C */ 317 pI128->mem.rbase_w[MW0_ORG] = iR->i128_base_w[MW0_ORG]; /* 0x0010 */ 318 pI128->mem.rbase_w[MW0_MSRC] = iR->i128_base_w[MW0_MSRC]; /* 0x0018 */ 319 pI128->mem.rbase_w[MW0_WKEY] = iR->i128_base_w[MW0_WKEY]; /* 0x001C */ 320 pI128->mem.rbase_w[MW0_KDAT] = iR->i128_base_w[MW0_KDAT]; /* 0x0020 */ 321 pI128->mem.rbase_w[MW0_MASK] = iR->i128_base_w[MW0_MASK]; /* 0x0024 */ 322 MB; 323 324 pI128->mem.rbase_g[INT_VCNT] = iR->i128_base_g[INT_VCNT]; /* 0x0020 */ 325 pI128->mem.rbase_g[INT_HCNT] = iR->i128_base_g[INT_HCNT]; /* 0x0024 */ 326 pI128->mem.rbase_g[DB_ADR] = iR->i128_base_g[DB_ADR]; /* 0x0028 */ 327 pI128->mem.rbase_g[DB_PTCH] = iR->i128_base_g[DB_PTCH]; /* 0x002C */ 328 pI128->mem.rbase_g[CRT_HAC] = iR->i128_base_g[CRT_HAC]; /* 0x0030 */ 329 pI128->mem.rbase_g[CRT_HBL] = iR->i128_base_g[CRT_HBL]; /* 0x0034 */ 330 pI128->mem.rbase_g[CRT_HFP] = iR->i128_base_g[CRT_HFP]; /* 0x0038 */ 331 pI128->mem.rbase_g[CRT_HS] = iR->i128_base_g[CRT_HS]; /* 0x003C */ 332 pI128->mem.rbase_g[CRT_VAC] = iR->i128_base_g[CRT_VAC]; /* 0x0040 */ 333 pI128->mem.rbase_g[CRT_VBL] = iR->i128_base_g[CRT_VBL]; /* 0x0044 */ 334 pI128->mem.rbase_g[CRT_VFP] = iR->i128_base_g[CRT_VFP]; /* 0x0048 */ 335 pI128->mem.rbase_g[CRT_VS] = iR->i128_base_g[CRT_VS]; /* 0x004C */ 336 pI128->mem.rbase_g[CRT_LCNT] = iR->i128_base_g[CRT_LCNT]; /* 0x0050 */ 337 pI128->mem.rbase_g[CRT_ZOOM] = iR->i128_base_g[CRT_ZOOM]; /* 0x0054 */ 338 pI128->mem.rbase_g[CRT_1CON] = iR->i128_base_g[CRT_1CON]; /* 0x0058 */ 339 pI128->mem.rbase_g[CRT_2CON] = iR->i128_base_g[CRT_2CON]; /* 0x005C */ 340 MB; 341 342 if (pI128->Debug) { 343 unsigned long tmp1 = inl(iR->iobase + 0x1C); 344 unsigned long tmp2 = inl(iR->iobase + 0x20); 345 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "I128RestoreState resetting config1/2 from 0x%lx/0x%lx to 0x%lx/0x%lx\n", tmp1, tmp2, (unsigned long)iR->config1, (unsigned long)iR->config2); 346 I128DumpActiveRegisters(pScrn); 347 } 348 349 if (pI128->MemoryType == I128_MEMORY_SGRAM) { 350 outl(iR->iobase + 0x24, iR->sgram & 0x7FFFFFFF); 351 outl(iR->iobase + 0x24, iR->sgram | 0x80000000); 352 } 353 354 outl(iR->iobase + 0x20, iR->config2); 355 outl(iR->iobase + 0x1C, iR->config1); 356 357 if (pI128->Debug) 358 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "I128RestoreState complete\n"); 359} 360 361 362Bool 363I128Init(ScrnInfoPtr pScrn, DisplayModePtr mode) 364{ 365 I128Ptr pI128; 366 I128RegPtr iR; 367 int pitch_multiplier, iclock; 368 Bool ret; 369 CARD32 tmp; 370 int doubled = 1; 371 372 if (mode->Flags & V_DBLSCAN) 373 doubled = 2; 374 375 pI128 = I128PTR(pScrn); 376 iR = &pI128->RegRec; 377 pI128->HDisplay = mode->HDisplay; 378 379 if (pI128->Debug) 380 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "I128Init start\n"); 381 382 /* config 1 and 2 were saved in Probe() 383 * we reset here again in case there was a VT switch 384 */ 385 386 outl(iR->iobase + 0x1C, pI128->io.config1); 387 outl(iR->iobase + 0x20, pI128->io.config2); 388 389 if (pI128->MemoryType == I128_MEMORY_SGRAM) { 390 outl(iR->iobase + 0x24, pI128->io.sgram & 0x7FFFFFFF); 391 outl(iR->iobase + 0x24, pI128->io.sgram | 0x80000000); 392 } 393 394 395 if (pI128->bitsPerPixel == 32) pitch_multiplier = 4; 396 else if (pI128->bitsPerPixel == 16) pitch_multiplier = 2; 397 else pitch_multiplier = 1; 398 399 if (pI128->RamdacType == TI3025_DAC) 400 iclock = 4; 401 else if (pI128->RamdacType == IBM528_DAC) 402 iclock = 128 / pI128->bitsPerPixel; 403 else if (pI128->RamdacType == SILVER_HAMMER_DAC) 404 iclock = 64 / pI128->bitsPerPixel; 405 else if ((pI128->MemoryType == I128_MEMORY_DRAM) || 406 (pI128->MemoryType == I128_MEMORY_SGRAM)) 407 iclock = 32 / pI128->bitsPerPixel; /* IBM526 DAC 32b bus */ 408 else 409 iclock = 64 / pI128->bitsPerPixel; /* IBM524/526 DAC */ 410 411 pI128->mem.rbase_g[INT_VCNT] = 0x00; 412 pI128->mem.rbase_g[INT_HCNT] = 0x00; 413 pI128->mem.rbase_g[DB_ADR] = pI128->displayOffset; 414 pI128->mem.rbase_g[DB_PTCH] = pI128->displayWidth * pitch_multiplier; 415 pI128->mem.rbase_g[CRT_HAC] = mode->HDisplay/iclock; 416 pI128->mem.rbase_g[CRT_HBL] = (mode->HTotal - mode->HDisplay)/iclock; 417 pI128->mem.rbase_g[CRT_HFP] = (mode->HSyncStart - mode->HDisplay)/iclock; 418 pI128->mem.rbase_g[CRT_HS] = (mode->HSyncEnd - mode->HSyncStart)/iclock; 419 pI128->mem.rbase_g[CRT_VAC] = mode->VDisplay * doubled; 420 pI128->mem.rbase_g[CRT_VBL] = (mode->VTotal - mode->VDisplay) * doubled; 421 pI128->mem.rbase_g[CRT_VFP] = (mode->VSyncStart - mode->VDisplay)* doubled; 422 pI128->mem.rbase_g[CRT_VS] = (mode->VSyncEnd - mode->VSyncStart) * doubled; 423 tmp = 0x00000070; 424 if (pI128->Chipset == PCI_CHIP_I128_T2R) 425 tmp |= 0x00000100; 426 if (pI128->Chipset == PCI_CHIP_I128_T2R4) { 427 if (pI128->FlatPanel) 428 tmp |= 0x00000100; /* Turn on digital flat panel */ 429 else 430 tmp &= 0xfffffeff; /* Turn off digital flat panel */ 431 } 432 if (pI128->DACSyncOnGreen || (mode->Flags & V_CSYNC)) 433 tmp |= 0x00000004; 434 pI128->mem.rbase_g[CRT_1CON] = tmp; 435 if ((pI128->MemoryType == I128_MEMORY_DRAM) || 436 (pI128->MemoryType == I128_MEMORY_SGRAM)) 437 tmp = 0x20000100; 438 else if (pI128->MemoryType == I128_MEMORY_WRAM) 439 tmp = 0x00040100; 440 else { 441 tmp = 0x00040101; 442 if (pI128->MemorySize == 2048) 443 tmp |= 0x00000002; 444 if ((pI128->displayWidth & (pI128->displayWidth-1)) || 445 ((pI128->displayWidth * pI128->bitsPerPixel) > 32768L)) 446 tmp |= 0x01000000; /* split transfer */ 447 } 448 pI128->mem.rbase_g[CRT_2CON] = tmp; 449 if (mode->Flags & V_DBLSCAN) 450 pI128->DoubleScan = TRUE; 451 else 452 pI128->DoubleScan = FALSE; 453 pI128->mem.rbase_g[CRT_ZOOM] = (pI128->DoubleScan ? 0x00000001 : 0x00000000); 454 455 pI128->mem.rbase_w[MW0_CTRL] = 0x00000000; 456 switch (pI128->MemorySize) { 457 case 2048: 458 pI128->mem.rbase_w[MW0_SZ] = 0x00000009; 459 break; 460 case 8192: 461 pI128->mem.rbase_w[MW0_SZ] = 0x0000000B; 462 break; 463 case 8192+4096: 464 /* no break */ 465 case 16384: 466 pI128->mem.rbase_w[MW0_SZ] = 0x0000000C; 467 break; 468 case 16384+4096: 469 /* no break */ 470 case 16384+8192: 471 /* no break */ 472 case 16384+8192+4096: 473 /* no break */ 474 case 32768: 475 pI128->mem.rbase_w[MW0_SZ] = 0x0000000D; 476 break; 477 case 4096: 478 /* no break */ 479 default: 480 pI128->mem.rbase_w[MW0_SZ] = 0x0000000A;/* default 4MB */ 481 break; 482 } 483 pI128->mem.rbase_w[MW0_PGE] = 0x00000000; 484 pI128->mem.rbase_w[MW0_ORG] = 0x00000000; 485 pI128->mem.rbase_w[MW0_MSRC] = 0x00000000; 486 pI128->mem.rbase_w[MW0_WKEY] = 0x00000000; 487 pI128->mem.rbase_w[MW0_KDAT] = 0x00000000; 488 pI128->mem.rbase_w[MW0_MASK] = 0xFFFFFFFF; 489 MB; 490 491 if ((pI128->io.id&0x7) > 0 || pI128->Chipset == PCI_CHIP_I128_T2R 492 || pI128->Chipset == PCI_CHIP_I128_T2R4) { 493 494 pI128->io.vga_ctl &= 0x0000FF00; 495 pI128->io.vga_ctl |= 0x00000082; 496 if (pI128->FlatPanel && (mode->Flags & V_DBLSCAN)) 497 pI128->io.vga_ctl |= 0x00000020; /* Stretch horizontally */ 498 outl(iR->iobase + 0x30, pI128->io.vga_ctl); 499 500 if (pI128->Chipset == PCI_CHIP_I128_T2R4) { 501 outl(iR->iobase + 0x24, 0x211BF030); 502 usleep(5000); 503 outl(iR->iobase + 0x24, 0xA11BF030); 504 } else if (pI128->MemoryType == I128_MEMORY_SGRAM) { 505 outl(iR->iobase + 0x24, 0x21089030); 506 usleep(5000); 507 outl(iR->iobase + 0x24, 0xA1089030); 508 } 509 } 510 511 ret = pI128->ProgramDAC(pScrn, mode); 512 513 pI128->InitCursorFlag = TRUE; 514 pI128->Initialized = 1; 515 516 if (pI128->Debug) 517 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "I128Init complete\n"); 518 519 return(ret); 520} 521 522 523static void 524I128SavePalette(I128Ptr pI128) 525{ 526 short i; 527 528 pI128->mem.rbase_g[PEL_MASK] = 0xff; MB; 529 530 if (!pI128->LUTSaved) { 531 pI128->mem.rbase_g[RD_ADR] = 0x00; MB; 532 for (i=0; i<256; i++) { 533 pI128->lutorig[i].r = pI128->mem.rbase_g[PAL_DAT]; MB; 534 pI128->lutorig[i].g = pI128->mem.rbase_g[PAL_DAT]; MB; 535 pI128->lutorig[i].b = pI128->mem.rbase_g[PAL_DAT]; MB; 536 } 537 pI128->LUTSaved = TRUE; 538 } 539 540} 541 542 543static void 544I128RestorePalette(I128Ptr pI128) 545{ 546 int i; 547 /* restore the LUT */ 548 549 pI128->mem.rbase_g[PEL_MASK] = 0xff; MB; 550 pI128->mem.rbase_g[WR_ADR] = 0x00; MB; 551 552 for (i=0; i<256; i++) { 553 pI128->mem.rbase_g[PAL_DAT] = pI128->lutorig[i].r; MB; 554 pI128->mem.rbase_g[PAL_DAT] = pI128->lutorig[i].g; MB; 555 pI128->mem.rbase_g[PAL_DAT] = pI128->lutorig[i].b; MB; 556 } 557} 558 559 560void 561I128LoadPalette(ScrnInfoPtr pScrn, int numColors, int *indices, LOCO *colors, 562 VisualPtr pVisual) 563{ 564 I128Ptr pI128; 565 566 if (pVisual->nplanes != 8) 567 return; 568 569 pI128 = I128PTR(pScrn); 570 571 pI128->mem.rbase_g[PEL_MASK] = 0xff; MB; 572 573 while (numColors--) { 574 pI128->mem.rbase_g[WR_ADR] = *indices; MB; 575 pI128->mem.rbase_g[PAL_DAT] = colors[*indices].red; MB; 576 pI128->mem.rbase_g[PAL_DAT] = colors[*indices].green; MB; 577 pI128->mem.rbase_g[PAL_DAT] = colors[*indices].blue; MB; 578 indices++; 579 } 580} 581