1428d7b3dSmrg/* i810_common.h -- common header definitions for I810 2D/3D/DRM suite
2428d7b3dSmrg *
3428d7b3dSmrg * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
4428d7b3dSmrg * All Rights Reserved.
5428d7b3dSmrg *
6428d7b3dSmrg * Permission is hereby granted, free of charge, to any person obtaining a
7428d7b3dSmrg * copy of this software and associated documentation files (the "Software"),
8428d7b3dSmrg * to deal in the Software without restriction, including without limitation
9428d7b3dSmrg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10428d7b3dSmrg * and/or sell copies of the Software, and to permit persons to whom the
11428d7b3dSmrg * Software is furnished to do so, subject to the following conditions:
12428d7b3dSmrg *
13428d7b3dSmrg * The above copyright notice and this permission notice (including the next
14428d7b3dSmrg * paragraph) shall be included in all copies or substantial portions of the
15428d7b3dSmrg * Software.
16428d7b3dSmrg *
17428d7b3dSmrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18428d7b3dSmrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19428d7b3dSmrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20428d7b3dSmrg * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21428d7b3dSmrg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22428d7b3dSmrg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23428d7b3dSmrg * DEALINGS IN THE SOFTWARE.
24428d7b3dSmrg *
25428d7b3dSmrg * Converted to common header format:
26428d7b3dSmrg *   Jens Owen <jens@tungstengraphics.com>
27428d7b3dSmrg *
28428d7b3dSmrg *
29428d7b3dSmrg */
30428d7b3dSmrg
31428d7b3dSmrg/* WARNING: If you change any of these defines, make sure to change
32428d7b3dSmrg * the kernel include file as well (i810_drm.h)
33428d7b3dSmrg */
34428d7b3dSmrg
35428d7b3dSmrg#ifndef _I810_COMMON_H_
36428d7b3dSmrg#define _I810_COMMON_H_
37428d7b3dSmrg
38428d7b3dSmrg/* Provide substitutes for gcc's __FUNCTION__ on other compilers */
39428d7b3dSmrg#if !defined(__GNUC__) && !defined(__FUNCTION__)
40428d7b3dSmrg# if defined(__STDC__) && (__STDC_VERSION__>=199901L) /* C99 */
41428d7b3dSmrg#  define __FUNCTION__ __func__
42428d7b3dSmrg# else
43428d7b3dSmrg#  define __FUNCTION__ ""
44428d7b3dSmrg# endif
45428d7b3dSmrg#endif
46428d7b3dSmrg
47428d7b3dSmrg#define PFX __FILE__,__LINE__,__FUNCTION__
48428d7b3dSmrg#define FUNCTION_NAME __FUNCTION__
49428d7b3dSmrg
50428d7b3dSmrg#define KB(x) ((x) * 1024)
51428d7b3dSmrg#define MB(x) ((x) * KB(1024))
52428d7b3dSmrg
53428d7b3dSmrg#define ALIGN(i,m) (((i) + (m) - 1) & ~((m) - 1))
54428d7b3dSmrg
55428d7b3dSmrg/* Using usleep() makes things noticably slow. */
56428d7b3dSmrg#if 0
57428d7b3dSmrg#define DELAY(x) usleep(x)
58428d7b3dSmrg#else
59428d7b3dSmrg#define DELAY(x) do {;} while (0)
60428d7b3dSmrg#endif
61428d7b3dSmrg
62428d7b3dSmrg#define PrintErrorState I810PrintErrorState
63428d7b3dSmrg#define WaitRingFunc I810WaitLpRing
64428d7b3dSmrg#define RecPtr pI810
65428d7b3dSmrg
66428d7b3dSmrgstatic inline void memset_volatile(volatile void *b, int c, size_t len)
67428d7b3dSmrg{
68428d7b3dSmrg    unsigned i;
69428d7b3dSmrg
70428d7b3dSmrg    for (i = 0; i < len; i++)
71428d7b3dSmrg	((volatile char *)b)[i] = c;
72428d7b3dSmrg}
73428d7b3dSmrg
74428d7b3dSmrgstatic inline void memcpy_volatile(volatile void *dst, const void *src,
75428d7b3dSmrg				   size_t len)
76428d7b3dSmrg{
77428d7b3dSmrg    unsigned i;
78428d7b3dSmrg
79428d7b3dSmrg    for (i = 0; i < len; i++)
80428d7b3dSmrg	((volatile char *)dst)[i] = ((const volatile char *)src)[i];
81428d7b3dSmrg}
82428d7b3dSmrg
83428d7b3dSmrg/* Memory mapped register access macros */
84428d7b3dSmrg#define INREG8(addr)        *(volatile uint8_t *)(RecPtr->MMIOBase + (addr))
85428d7b3dSmrg#define INREG16(addr)       *(volatile uint16_t *)(RecPtr->MMIOBase + (addr))
86428d7b3dSmrg#define INREG(addr)         *(volatile uint32_t *)(RecPtr->MMIOBase + (addr))
87428d7b3dSmrg#define INGTT(addr)         *(volatile uint32_t *)(RecPtr->GTTBase + (addr))
88428d7b3dSmrg#define POSTING_READ(addr)  (void)INREG(addr)
89428d7b3dSmrg
90428d7b3dSmrg#define OUTREG8(addr, val) do {						\
91428d7b3dSmrg   *(volatile uint8_t *)(RecPtr->MMIOBase  + (addr)) = (val);		\
92428d7b3dSmrg   if (I810_DEBUG&DEBUG_VERBOSE_OUTREG) {				\
93428d7b3dSmrg      ErrorF("OUTREG8(0x%lx, 0x%lx) in %s\n", (unsigned long)(addr),	\
94428d7b3dSmrg		(unsigned long)(val), FUNCTION_NAME);			\
95428d7b3dSmrg   }									\
96428d7b3dSmrg} while (0)
97428d7b3dSmrg
98428d7b3dSmrg#define OUTREG16(addr, val) do {					\
99428d7b3dSmrg   *(volatile uint16_t *)(RecPtr->MMIOBase + (addr)) = (val);		\
100428d7b3dSmrg   if (I810_DEBUG&DEBUG_VERBOSE_OUTREG) {				\
101428d7b3dSmrg      ErrorF("OUTREG16(0x%lx, 0x%lx) in %s\n", (unsigned long)(addr),	\
102428d7b3dSmrg		(unsigned long)(val), FUNCTION_NAME);			\
103428d7b3dSmrg   }									\
104428d7b3dSmrg} while (0)
105428d7b3dSmrg
106428d7b3dSmrg#define OUTREG(addr, val) do {						\
107428d7b3dSmrg   *(volatile uint32_t *)(RecPtr->MMIOBase + (addr)) = (val);		\
108428d7b3dSmrg   if (I810_DEBUG&DEBUG_VERBOSE_OUTREG) {				\
109428d7b3dSmrg      ErrorF("OUTREG(0x%lx, 0x%lx) in %s\n", (unsigned long)(addr),	\
110428d7b3dSmrg		(unsigned long)(val), FUNCTION_NAME);			\
111428d7b3dSmrg   }									\
112428d7b3dSmrg} while (0)
113428d7b3dSmrg
114428d7b3dSmrg/* To remove all debugging, make sure I810_DEBUG is defined as a
115428d7b3dSmrg * preprocessor symbol, and equal to zero.
116428d7b3dSmrg */
117428d7b3dSmrg#if 1
118428d7b3dSmrg#define I810_DEBUG 0
119428d7b3dSmrg#endif
120428d7b3dSmrg#ifndef I810_DEBUG
121428d7b3dSmrg#warning "Debugging enabled - expect reduced performance"
122428d7b3dSmrgextern int I810_DEBUG;
123428d7b3dSmrg#endif
124428d7b3dSmrg
125428d7b3dSmrg#define DEBUG_VERBOSE_ACCEL  0x1
126428d7b3dSmrg#define DEBUG_VERBOSE_SYNC   0x2
127428d7b3dSmrg#define DEBUG_VERBOSE_VGA    0x4
128428d7b3dSmrg#define DEBUG_VERBOSE_RING   0x8
129428d7b3dSmrg#define DEBUG_VERBOSE_OUTREG 0x10
130428d7b3dSmrg#define DEBUG_VERBOSE_MEMORY 0x20
131428d7b3dSmrg#define DEBUG_VERBOSE_CURSOR 0x40
132428d7b3dSmrg#define DEBUG_ALWAYS_SYNC    0x80
133428d7b3dSmrg#define DEBUG_VERBOSE_DRI    0x100
134428d7b3dSmrg#define DEBUG_VERBOSE_BIOS   0x200
135428d7b3dSmrg
136428d7b3dSmrg/* Size of the mmio region.
137428d7b3dSmrg */
138428d7b3dSmrg#define I810_REG_SIZE 0x80000
139428d7b3dSmrg
140428d7b3dSmrg#define GTT_PAGE_SIZE			KB(4)
141428d7b3dSmrg#define PRIMARY_RINGBUFFER_SIZE		KB(128)
142428d7b3dSmrg#define MIN_SCRATCH_BUFFER_SIZE		KB(16)
143428d7b3dSmrg#define MAX_SCRATCH_BUFFER_SIZE		KB(64)
144428d7b3dSmrg#define HWCURSOR_SIZE			GTT_PAGE_SIZE
145428d7b3dSmrg#define HWCURSOR_SIZE_ARGB		GTT_PAGE_SIZE * 4
146428d7b3dSmrg
147428d7b3dSmrg/* Use a 64x64 HW cursor */
148428d7b3dSmrg#define I810_CURSOR_X			64
149428d7b3dSmrg#define I810_CURSOR_Y			I810_CURSOR_X
150428d7b3dSmrg
151428d7b3dSmrg#define PIPE_NAME(n)			('A' + (n))
152428d7b3dSmrg
153428d7b3dSmrgextern struct pci_device *
154428d7b3dSmrgintel_host_bridge (void);
155428d7b3dSmrg
156428d7b3dSmrg/**
157428d7b3dSmrg * Hints to CreatePixmap to tell the driver how the pixmap is going to be
158428d7b3dSmrg * used.
159428d7b3dSmrg *
160428d7b3dSmrg * Compare to CREATE_PIXMAP_USAGE_* in the server.
161428d7b3dSmrg */
162428d7b3dSmrgenum {
163428d7b3dSmrg	INTEL_CREATE_PIXMAP_TILING_X = 0x10000000,
164428d7b3dSmrg	INTEL_CREATE_PIXMAP_TILING_Y,
165428d7b3dSmrg	INTEL_CREATE_PIXMAP_TILING_NONE,
166428d7b3dSmrg};
167428d7b3dSmrg
168428d7b3dSmrg#ifndef _I810_DEFINES_
169428d7b3dSmrg#define _I810_DEFINES_
170428d7b3dSmrg#define I810_USE_BATCH 1
171428d7b3dSmrg
172428d7b3dSmrg#define I810_DMA_BUF_ORDER     12
173428d7b3dSmrg#define I810_DMA_BUF_SZ        (1<<I810_DMA_BUF_ORDER)
174428d7b3dSmrg#define I810_DMA_BUF_NR        256
175428d7b3dSmrg
176428d7b3dSmrg#define I810_NR_SAREA_CLIPRECTS 8
177428d7b3dSmrg
178428d7b3dSmrg/* Each region is a minimum of 64k, and there are at most 64 of them.
179428d7b3dSmrg */
180428d7b3dSmrg#define I810_NR_TEX_REGIONS 64
181428d7b3dSmrg#define I810_LOG_MIN_TEX_REGION_SIZE 16
182428d7b3dSmrg
183428d7b3dSmrg/* Destbuffer state
184428d7b3dSmrg *    - backbuffer linear offset and pitch -- invarient in the current dri
185428d7b3dSmrg *    - zbuffer linear offset and pitch -- also invarient
186428d7b3dSmrg *    - drawing origin in back and depth buffers.
187428d7b3dSmrg *
188428d7b3dSmrg * Keep the depth/back buffer state here to acommodate private buffers
189428d7b3dSmrg * in the future.
190428d7b3dSmrg */
191428d7b3dSmrg#define I810_DESTREG_DI0  0		/* CMD_OP_DESTBUFFER_INFO (2 dwords) */
192428d7b3dSmrg#define I810_DESTREG_DI1  1
193428d7b3dSmrg#define I810_DESTREG_DV0  2		/* GFX_OP_DESTBUFFER_VARS (2 dwords) */
194428d7b3dSmrg#define I810_DESTREG_DV1  3
195428d7b3dSmrg#define I810_DESTREG_DR0  4		/* GFX_OP_DRAWRECT_INFO (4 dwords) */
196428d7b3dSmrg#define I810_DESTREG_DR1  5
197428d7b3dSmrg#define I810_DESTREG_DR2  6
198428d7b3dSmrg#define I810_DESTREG_DR3  7
199428d7b3dSmrg#define I810_DESTREG_DR4  8
200428d7b3dSmrg#define I810_DEST_SETUP_SIZE 10
201428d7b3dSmrg
202428d7b3dSmrg/* Context state
203428d7b3dSmrg */
204428d7b3dSmrg#define I810_CTXREG_CF0   0		/* GFX_OP_COLOR_FACTOR */
205428d7b3dSmrg#define I810_CTXREG_CF1   1
206428d7b3dSmrg#define I810_CTXREG_ST0   2		/* GFX_OP_STIPPLE */
207428d7b3dSmrg#define I810_CTXREG_ST1   3
208428d7b3dSmrg#define I810_CTXREG_VF    4		/* GFX_OP_VERTEX_FMT */
209428d7b3dSmrg#define I810_CTXREG_MT    5		/* GFX_OP_MAP_TEXELS */
210428d7b3dSmrg#define I810_CTXREG_MC0   6		/* GFX_OP_MAP_COLOR_STAGES - stage 0 */
211428d7b3dSmrg#define I810_CTXREG_MC1   7		/* GFX_OP_MAP_COLOR_STAGES - stage 1 */
212428d7b3dSmrg#define I810_CTXREG_MC2   8		/* GFX_OP_MAP_COLOR_STAGES - stage 2 */
213428d7b3dSmrg#define I810_CTXREG_MA0   9		/* GFX_OP_MAP_ALPHA_STAGES - stage 0 */
214428d7b3dSmrg#define I810_CTXREG_MA1   10		/* GFX_OP_MAP_ALPHA_STAGES - stage 1 */
215428d7b3dSmrg#define I810_CTXREG_MA2   11		/* GFX_OP_MAP_ALPHA_STAGES - stage 2 */
216428d7b3dSmrg#define I810_CTXREG_SDM   12		/* GFX_OP_SRC_DEST_MONO */
217428d7b3dSmrg#define I810_CTXREG_FOG   13		/* GFX_OP_FOG_COLOR */
218428d7b3dSmrg#define I810_CTXREG_B1    14		/* GFX_OP_BOOL_1 */
219428d7b3dSmrg#define I810_CTXREG_B2    15		/* GFX_OP_BOOL_2 */
220428d7b3dSmrg#define I810_CTXREG_LCS   16		/* GFX_OP_LINEWIDTH_CULL_SHADE_MODE */
221428d7b3dSmrg#define I810_CTXREG_PV    17		/* GFX_OP_PV_RULE -- Invarient! */
222428d7b3dSmrg#define I810_CTXREG_ZA    18		/* GFX_OP_ZBIAS_ALPHAFUNC */
223428d7b3dSmrg#define I810_CTXREG_AA    19		/* GFX_OP_ANTIALIAS */
224428d7b3dSmrg#define I810_CTX_SETUP_SIZE 20
225428d7b3dSmrg
226428d7b3dSmrg/* Texture state (per tex unit)
227428d7b3dSmrg */
228428d7b3dSmrg#define I810_TEXREG_MI0  0		/* GFX_OP_MAP_INFO (4 dwords) */
229428d7b3dSmrg#define I810_TEXREG_MI1  1
230428d7b3dSmrg#define I810_TEXREG_MI2  2
231428d7b3dSmrg#define I810_TEXREG_MI3  3
232428d7b3dSmrg#define I810_TEXREG_MF   4		/* GFX_OP_MAP_FILTER */
233428d7b3dSmrg#define I810_TEXREG_MLC  5		/* GFX_OP_MAP_LOD_CTL */
234428d7b3dSmrg#define I810_TEXREG_MLL  6		/* GFX_OP_MAP_LOD_LIMITS */
235428d7b3dSmrg#define I810_TEXREG_MCS  7		/* GFX_OP_MAP_COORD_SETS ??? */
236428d7b3dSmrg#define I810_TEX_SETUP_SIZE 8
237428d7b3dSmrg
238428d7b3dSmrg/* Driver specific DRM command indices
239428d7b3dSmrg * NOTE: these are not OS specific, but they are driver specific
240428d7b3dSmrg */
241428d7b3dSmrg#define DRM_I810_INIT                     0x00
242428d7b3dSmrg#define DRM_I810_VERTEX                   0x01
243428d7b3dSmrg#define DRM_I810_CLEAR                    0x02
244428d7b3dSmrg#define DRM_I810_FLUSH                    0x03
245428d7b3dSmrg#define DRM_I810_GETAGE                   0x04
246428d7b3dSmrg#define DRM_I810_GETBUF                   0x05
247428d7b3dSmrg#define DRM_I810_SWAP                     0x06
248428d7b3dSmrg#define DRM_I810_COPY                     0x07
249428d7b3dSmrg#define DRM_I810_DOCOPY                   0x08
250428d7b3dSmrg#define DRM_I810_OV0INFO                  0x09
251428d7b3dSmrg#define DRM_I810_FSTATUS                  0x0a
252428d7b3dSmrg#define DRM_I810_OV0FLIP                  0x0b
253428d7b3dSmrg#define DRM_I810_MC                       0x0c
254428d7b3dSmrg#define DRM_I810_RSTATUS                  0x0d
255428d7b3dSmrg#define DRM_I810_FLIP                     0x0e
256428d7b3dSmrg
257428d7b3dSmrg#endif
258428d7b3dSmrg
259428d7b3dSmrgtypedef enum _drmI810Initfunc {
260428d7b3dSmrg	I810_INIT_DMA = 0x01,
261428d7b3dSmrg	I810_CLEANUP_DMA = 0x02,
262428d7b3dSmrg	I810_INIT_DMA_1_4 = 0x03
263428d7b3dSmrg} drmI810Initfunc;
264428d7b3dSmrg
265428d7b3dSmrgtypedef struct {
266428d7b3dSmrg   drmI810Initfunc func;
267428d7b3dSmrg   unsigned int mmio_offset;
268428d7b3dSmrg   unsigned int buffers_offset;
269428d7b3dSmrg   int sarea_priv_offset;
270428d7b3dSmrg   unsigned int ring_start;
271428d7b3dSmrg   unsigned int ring_end;
272428d7b3dSmrg   unsigned int ring_size;
273428d7b3dSmrg   unsigned int front_offset;
274428d7b3dSmrg   unsigned int back_offset;
275428d7b3dSmrg   unsigned int depth_offset;
276428d7b3dSmrg   unsigned int overlay_offset;
277428d7b3dSmrg   unsigned int overlay_physical;
278428d7b3dSmrg   unsigned int w;
279428d7b3dSmrg   unsigned int h;
280428d7b3dSmrg   unsigned int pitch;
281428d7b3dSmrg   unsigned int pitch_bits;
282428d7b3dSmrg} drmI810Init;
283428d7b3dSmrg
284428d7b3dSmrgtypedef struct {
285428d7b3dSmrg   void *virtual;
286428d7b3dSmrg   int request_idx;
287428d7b3dSmrg   int request_size;
288428d7b3dSmrg   int granted;
289428d7b3dSmrg} drmI810DMA;
290428d7b3dSmrg
291428d7b3dSmrg/* Flags for clear ioctl
292428d7b3dSmrg */
293428d7b3dSmrg#define I810_FRONT   0x1
294428d7b3dSmrg#define I810_BACK    0x2
295428d7b3dSmrg#define I810_DEPTH   0x4
296428d7b3dSmrg
297428d7b3dSmrgtypedef struct {
298428d7b3dSmrg   int clear_color;
299428d7b3dSmrg   int clear_depth;
300428d7b3dSmrg   int flags;
301428d7b3dSmrg} drmI810Clear;
302428d7b3dSmrg
303428d7b3dSmrgtypedef struct {
304428d7b3dSmrg   int idx;				/* buffer index */
305428d7b3dSmrg   int used;				/* nr bytes in use */
306428d7b3dSmrg   int discard;				/* client is finished with the buffer? */
307428d7b3dSmrg} drmI810Vertex;
308428d7b3dSmrg
309428d7b3dSmrg/* Flags for vertex ioctl
310428d7b3dSmrg */
311428d7b3dSmrg#define PR_TRIANGLES         (0x0<<18)
312428d7b3dSmrg#define PR_TRISTRIP_0        (0x1<<18)
313428d7b3dSmrg#define PR_TRISTRIP_1        (0x2<<18)
314428d7b3dSmrg#define PR_TRIFAN            (0x3<<18)
315428d7b3dSmrg#define PR_POLYGON           (0x4<<18)
316428d7b3dSmrg#define PR_LINES             (0x5<<18)
317428d7b3dSmrg#define PR_LINESTRIP         (0x6<<18)
318428d7b3dSmrg#define PR_RECTS             (0x7<<18)
319428d7b3dSmrg#define PR_MASK              (0x7<<18)
320428d7b3dSmrg
321428d7b3dSmrg#endif
322