i810_common.h revision 428d7b3d
17ec681f3Smrg/* i810_common.h -- common header definitions for I810 2D/3D/DRM suite 27ec681f3Smrg * 37ec681f3Smrg * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 47ec681f3Smrg * All Rights Reserved. 57ec681f3Smrg * 67ec681f3Smrg * Permission is hereby granted, free of charge, to any person obtaining a 77ec681f3Smrg * copy of this software and associated documentation files (the "Software"), 87ec681f3Smrg * to deal in the Software without restriction, including without limitation 97ec681f3Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 107ec681f3Smrg * and/or sell copies of the Software, and to permit persons to whom the 117ec681f3Smrg * Software is furnished to do so, subject to the following conditions: 127ec681f3Smrg * 137ec681f3Smrg * The above copyright notice and this permission notice (including the next 147ec681f3Smrg * paragraph) shall be included in all copies or substantial portions of the 157ec681f3Smrg * Software. 167ec681f3Smrg * 177ec681f3Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 187ec681f3Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 197ec681f3Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 207ec681f3Smrg * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 217ec681f3Smrg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 227ec681f3Smrg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 237ec681f3Smrg * DEALINGS IN THE SOFTWARE. 247ec681f3Smrg * 257ec681f3Smrg * Converted to common header format: 267ec681f3Smrg * Jens Owen <jens@tungstengraphics.com> 277ec681f3Smrg * 287ec681f3Smrg * 297ec681f3Smrg */ 307ec681f3Smrg 317ec681f3Smrg/* WARNING: If you change any of these defines, make sure to change 327ec681f3Smrg * the kernel include file as well (i810_drm.h) 337ec681f3Smrg */ 347ec681f3Smrg 357ec681f3Smrg#ifndef _I810_COMMON_H_ 367ec681f3Smrg#define _I810_COMMON_H_ 377ec681f3Smrg 387ec681f3Smrg/* Provide substitutes for gcc's __FUNCTION__ on other compilers */ 397ec681f3Smrg#if !defined(__GNUC__) && !defined(__FUNCTION__) 407ec681f3Smrg# if defined(__STDC__) && (__STDC_VERSION__>=199901L) /* C99 */ 417ec681f3Smrg# define __FUNCTION__ __func__ 427ec681f3Smrg# else 437ec681f3Smrg# define __FUNCTION__ "" 447ec681f3Smrg# endif 457ec681f3Smrg#endif 467ec681f3Smrg 477ec681f3Smrg#define PFX __FILE__,__LINE__,__FUNCTION__ 487ec681f3Smrg#define FUNCTION_NAME __FUNCTION__ 497ec681f3Smrg 507ec681f3Smrg#define KB(x) ((x) * 1024) 517ec681f3Smrg#define MB(x) ((x) * KB(1024)) 527ec681f3Smrg 537ec681f3Smrg#define ALIGN(i,m) (((i) + (m) - 1) & ~((m) - 1)) 547ec681f3Smrg 557ec681f3Smrg/* Using usleep() makes things noticably slow. */ 567ec681f3Smrg#if 0 577ec681f3Smrg#define DELAY(x) usleep(x) 587ec681f3Smrg#else 597ec681f3Smrg#define DELAY(x) do {;} while (0) 607ec681f3Smrg#endif 617ec681f3Smrg 627ec681f3Smrg#define PrintErrorState I810PrintErrorState 637ec681f3Smrg#define WaitRingFunc I810WaitLpRing 647ec681f3Smrg#define RecPtr pI810 657ec681f3Smrg 667ec681f3Smrgstatic inline void memset_volatile(volatile void *b, int c, size_t len) 677ec681f3Smrg{ 687ec681f3Smrg unsigned i; 697ec681f3Smrg 707ec681f3Smrg for (i = 0; i < len; i++) 717ec681f3Smrg ((volatile char *)b)[i] = c; 727ec681f3Smrg} 737ec681f3Smrg 747ec681f3Smrgstatic inline void memcpy_volatile(volatile void *dst, const void *src, 757ec681f3Smrg size_t len) 767ec681f3Smrg{ 777ec681f3Smrg unsigned i; 787ec681f3Smrg 797ec681f3Smrg for (i = 0; i < len; i++) 807ec681f3Smrg ((volatile char *)dst)[i] = ((const volatile char *)src)[i]; 817ec681f3Smrg} 827ec681f3Smrg 837ec681f3Smrg/* Memory mapped register access macros */ 847ec681f3Smrg#define INREG8(addr) *(volatile uint8_t *)(RecPtr->MMIOBase + (addr)) 857ec681f3Smrg#define INREG16(addr) *(volatile uint16_t *)(RecPtr->MMIOBase + (addr)) 867ec681f3Smrg#define INREG(addr) *(volatile uint32_t *)(RecPtr->MMIOBase + (addr)) 877ec681f3Smrg#define INGTT(addr) *(volatile uint32_t *)(RecPtr->GTTBase + (addr)) 887ec681f3Smrg#define POSTING_READ(addr) (void)INREG(addr) 897ec681f3Smrg 907ec681f3Smrg#define OUTREG8(addr, val) do { \ 917ec681f3Smrg *(volatile uint8_t *)(RecPtr->MMIOBase + (addr)) = (val); \ 927ec681f3Smrg if (I810_DEBUG&DEBUG_VERBOSE_OUTREG) { \ 937ec681f3Smrg ErrorF("OUTREG8(0x%lx, 0x%lx) in %s\n", (unsigned long)(addr), \ 947ec681f3Smrg (unsigned long)(val), FUNCTION_NAME); \ 957ec681f3Smrg } \ 967ec681f3Smrg} while (0) 977ec681f3Smrg 987ec681f3Smrg#define OUTREG16(addr, val) do { \ 997ec681f3Smrg *(volatile uint16_t *)(RecPtr->MMIOBase + (addr)) = (val); \ 1007ec681f3Smrg if (I810_DEBUG&DEBUG_VERBOSE_OUTREG) { \ 1017ec681f3Smrg ErrorF("OUTREG16(0x%lx, 0x%lx) in %s\n", (unsigned long)(addr), \ 1027ec681f3Smrg (unsigned long)(val), FUNCTION_NAME); \ 1037ec681f3Smrg } \ 1047ec681f3Smrg} while (0) 1057ec681f3Smrg 1067ec681f3Smrg#define OUTREG(addr, val) do { \ 1077ec681f3Smrg *(volatile uint32_t *)(RecPtr->MMIOBase + (addr)) = (val); \ 1087ec681f3Smrg if (I810_DEBUG&DEBUG_VERBOSE_OUTREG) { \ 1097ec681f3Smrg ErrorF("OUTREG(0x%lx, 0x%lx) in %s\n", (unsigned long)(addr), \ 1107ec681f3Smrg (unsigned long)(val), FUNCTION_NAME); \ 1117ec681f3Smrg } \ 1127ec681f3Smrg} while (0) 1137ec681f3Smrg 1147ec681f3Smrg/* To remove all debugging, make sure I810_DEBUG is defined as a 1157ec681f3Smrg * preprocessor symbol, and equal to zero. 1167ec681f3Smrg */ 1177ec681f3Smrg#if 1 1187ec681f3Smrg#define I810_DEBUG 0 1197ec681f3Smrg#endif 1207ec681f3Smrg#ifndef I810_DEBUG 1217ec681f3Smrg#warning "Debugging enabled - expect reduced performance" 1227ec681f3Smrgextern int I810_DEBUG; 1237ec681f3Smrg#endif 1247ec681f3Smrg 1257ec681f3Smrg#define DEBUG_VERBOSE_ACCEL 0x1 1267ec681f3Smrg#define DEBUG_VERBOSE_SYNC 0x2 1277ec681f3Smrg#define DEBUG_VERBOSE_VGA 0x4 1287ec681f3Smrg#define DEBUG_VERBOSE_RING 0x8 1297ec681f3Smrg#define DEBUG_VERBOSE_OUTREG 0x10 1307ec681f3Smrg#define DEBUG_VERBOSE_MEMORY 0x20 1317ec681f3Smrg#define DEBUG_VERBOSE_CURSOR 0x40 1327ec681f3Smrg#define DEBUG_ALWAYS_SYNC 0x80 1337ec681f3Smrg#define DEBUG_VERBOSE_DRI 0x100 1347ec681f3Smrg#define DEBUG_VERBOSE_BIOS 0x200 1357ec681f3Smrg 1367ec681f3Smrg/* Size of the mmio region. 1377ec681f3Smrg */ 1387ec681f3Smrg#define I810_REG_SIZE 0x80000 1397ec681f3Smrg 1407ec681f3Smrg#define GTT_PAGE_SIZE KB(4) 1417ec681f3Smrg#define PRIMARY_RINGBUFFER_SIZE KB(128) 1427ec681f3Smrg#define MIN_SCRATCH_BUFFER_SIZE KB(16) 1437ec681f3Smrg#define MAX_SCRATCH_BUFFER_SIZE KB(64) 1447ec681f3Smrg#define HWCURSOR_SIZE GTT_PAGE_SIZE 1457ec681f3Smrg#define HWCURSOR_SIZE_ARGB GTT_PAGE_SIZE * 4 1467ec681f3Smrg 1477ec681f3Smrg/* Use a 64x64 HW cursor */ 1487ec681f3Smrg#define I810_CURSOR_X 64 1497ec681f3Smrg#define I810_CURSOR_Y I810_CURSOR_X 1507ec681f3Smrg 1517ec681f3Smrg#define PIPE_NAME(n) ('A' + (n)) 1527ec681f3Smrg 1537ec681f3Smrgextern struct pci_device * 1547ec681f3Smrgintel_host_bridge (void); 1557ec681f3Smrg 1567ec681f3Smrg/** 1577ec681f3Smrg * Hints to CreatePixmap to tell the driver how the pixmap is going to be 1587ec681f3Smrg * used. 1597ec681f3Smrg * 1607ec681f3Smrg * Compare to CREATE_PIXMAP_USAGE_* in the server. 1617ec681f3Smrg */ 1627ec681f3Smrgenum { 1637ec681f3Smrg INTEL_CREATE_PIXMAP_TILING_X = 0x10000000, 1647ec681f3Smrg INTEL_CREATE_PIXMAP_TILING_Y, 1657ec681f3Smrg INTEL_CREATE_PIXMAP_TILING_NONE, 1667ec681f3Smrg}; 1677ec681f3Smrg 1687ec681f3Smrg#ifndef _I810_DEFINES_ 1697ec681f3Smrg#define _I810_DEFINES_ 1707ec681f3Smrg#define I810_USE_BATCH 1 1717ec681f3Smrg 1727ec681f3Smrg#define I810_DMA_BUF_ORDER 12 1737ec681f3Smrg#define I810_DMA_BUF_SZ (1<<I810_DMA_BUF_ORDER) 1747ec681f3Smrg#define I810_DMA_BUF_NR 256 1757ec681f3Smrg 1767ec681f3Smrg#define I810_NR_SAREA_CLIPRECTS 8 1777ec681f3Smrg 1787ec681f3Smrg/* Each region is a minimum of 64k, and there are at most 64 of them. 1797ec681f3Smrg */ 180#define I810_NR_TEX_REGIONS 64 181#define I810_LOG_MIN_TEX_REGION_SIZE 16 182 183/* Destbuffer state 184 * - backbuffer linear offset and pitch -- invarient in the current dri 185 * - zbuffer linear offset and pitch -- also invarient 186 * - drawing origin in back and depth buffers. 187 * 188 * Keep the depth/back buffer state here to acommodate private buffers 189 * in the future. 190 */ 191#define I810_DESTREG_DI0 0 /* CMD_OP_DESTBUFFER_INFO (2 dwords) */ 192#define I810_DESTREG_DI1 1 193#define I810_DESTREG_DV0 2 /* GFX_OP_DESTBUFFER_VARS (2 dwords) */ 194#define I810_DESTREG_DV1 3 195#define I810_DESTREG_DR0 4 /* GFX_OP_DRAWRECT_INFO (4 dwords) */ 196#define I810_DESTREG_DR1 5 197#define I810_DESTREG_DR2 6 198#define I810_DESTREG_DR3 7 199#define I810_DESTREG_DR4 8 200#define I810_DEST_SETUP_SIZE 10 201 202/* Context state 203 */ 204#define I810_CTXREG_CF0 0 /* GFX_OP_COLOR_FACTOR */ 205#define I810_CTXREG_CF1 1 206#define I810_CTXREG_ST0 2 /* GFX_OP_STIPPLE */ 207#define I810_CTXREG_ST1 3 208#define I810_CTXREG_VF 4 /* GFX_OP_VERTEX_FMT */ 209#define I810_CTXREG_MT 5 /* GFX_OP_MAP_TEXELS */ 210#define I810_CTXREG_MC0 6 /* GFX_OP_MAP_COLOR_STAGES - stage 0 */ 211#define I810_CTXREG_MC1 7 /* GFX_OP_MAP_COLOR_STAGES - stage 1 */ 212#define I810_CTXREG_MC2 8 /* GFX_OP_MAP_COLOR_STAGES - stage 2 */ 213#define I810_CTXREG_MA0 9 /* GFX_OP_MAP_ALPHA_STAGES - stage 0 */ 214#define I810_CTXREG_MA1 10 /* GFX_OP_MAP_ALPHA_STAGES - stage 1 */ 215#define I810_CTXREG_MA2 11 /* GFX_OP_MAP_ALPHA_STAGES - stage 2 */ 216#define I810_CTXREG_SDM 12 /* GFX_OP_SRC_DEST_MONO */ 217#define I810_CTXREG_FOG 13 /* GFX_OP_FOG_COLOR */ 218#define I810_CTXREG_B1 14 /* GFX_OP_BOOL_1 */ 219#define I810_CTXREG_B2 15 /* GFX_OP_BOOL_2 */ 220#define I810_CTXREG_LCS 16 /* GFX_OP_LINEWIDTH_CULL_SHADE_MODE */ 221#define I810_CTXREG_PV 17 /* GFX_OP_PV_RULE -- Invarient! */ 222#define I810_CTXREG_ZA 18 /* GFX_OP_ZBIAS_ALPHAFUNC */ 223#define I810_CTXREG_AA 19 /* GFX_OP_ANTIALIAS */ 224#define I810_CTX_SETUP_SIZE 20 225 226/* Texture state (per tex unit) 227 */ 228#define I810_TEXREG_MI0 0 /* GFX_OP_MAP_INFO (4 dwords) */ 229#define I810_TEXREG_MI1 1 230#define I810_TEXREG_MI2 2 231#define I810_TEXREG_MI3 3 232#define I810_TEXREG_MF 4 /* GFX_OP_MAP_FILTER */ 233#define I810_TEXREG_MLC 5 /* GFX_OP_MAP_LOD_CTL */ 234#define I810_TEXREG_MLL 6 /* GFX_OP_MAP_LOD_LIMITS */ 235#define I810_TEXREG_MCS 7 /* GFX_OP_MAP_COORD_SETS ??? */ 236#define I810_TEX_SETUP_SIZE 8 237 238/* Driver specific DRM command indices 239 * NOTE: these are not OS specific, but they are driver specific 240 */ 241#define DRM_I810_INIT 0x00 242#define DRM_I810_VERTEX 0x01 243#define DRM_I810_CLEAR 0x02 244#define DRM_I810_FLUSH 0x03 245#define DRM_I810_GETAGE 0x04 246#define DRM_I810_GETBUF 0x05 247#define DRM_I810_SWAP 0x06 248#define DRM_I810_COPY 0x07 249#define DRM_I810_DOCOPY 0x08 250#define DRM_I810_OV0INFO 0x09 251#define DRM_I810_FSTATUS 0x0a 252#define DRM_I810_OV0FLIP 0x0b 253#define DRM_I810_MC 0x0c 254#define DRM_I810_RSTATUS 0x0d 255#define DRM_I810_FLIP 0x0e 256 257#endif 258 259typedef enum _drmI810Initfunc { 260 I810_INIT_DMA = 0x01, 261 I810_CLEANUP_DMA = 0x02, 262 I810_INIT_DMA_1_4 = 0x03 263} drmI810Initfunc; 264 265typedef struct { 266 drmI810Initfunc func; 267 unsigned int mmio_offset; 268 unsigned int buffers_offset; 269 int sarea_priv_offset; 270 unsigned int ring_start; 271 unsigned int ring_end; 272 unsigned int ring_size; 273 unsigned int front_offset; 274 unsigned int back_offset; 275 unsigned int depth_offset; 276 unsigned int overlay_offset; 277 unsigned int overlay_physical; 278 unsigned int w; 279 unsigned int h; 280 unsigned int pitch; 281 unsigned int pitch_bits; 282} drmI810Init; 283 284typedef struct { 285 void *virtual; 286 int request_idx; 287 int request_size; 288 int granted; 289} drmI810DMA; 290 291/* Flags for clear ioctl 292 */ 293#define I810_FRONT 0x1 294#define I810_BACK 0x2 295#define I810_DEPTH 0x4 296 297typedef struct { 298 int clear_color; 299 int clear_depth; 300 int flags; 301} drmI810Clear; 302 303typedef struct { 304 int idx; /* buffer index */ 305 int used; /* nr bytes in use */ 306 int discard; /* client is finished with the buffer? */ 307} drmI810Vertex; 308 309/* Flags for vertex ioctl 310 */ 311#define PR_TRIANGLES (0x0<<18) 312#define PR_TRISTRIP_0 (0x1<<18) 313#define PR_TRISTRIP_1 (0x2<<18) 314#define PR_TRIFAN (0x3<<18) 315#define PR_POLYGON (0x4<<18) 316#define PR_LINES (0x5<<18) 317#define PR_LINESTRIP (0x6<<18) 318#define PR_RECTS (0x7<<18) 319#define PR_MASK (0x7<<18) 320 321#endif 322