1428d7b3dSmrg 2428d7b3dSmrg#ifndef _I810_DRI_ 3428d7b3dSmrg#define _I810_DRI_ 4428d7b3dSmrg 5428d7b3dSmrg#include "xf86drm.h" 6428d7b3dSmrg#include "i810_common.h" 7428d7b3dSmrg 8428d7b3dSmrg#define I810_MAX_DRAWABLES 256 9428d7b3dSmrg 10428d7b3dSmrg#define I810_MAJOR_VERSION 1 11428d7b3dSmrg#define I810_MINOR_VERSION 7 12428d7b3dSmrg#define I810_PATCHLEVEL 4 13428d7b3dSmrg 14428d7b3dSmrgtypedef struct { 15428d7b3dSmrg drm_handle_t regs; 16428d7b3dSmrg drmSize regsSize; 17428d7b3dSmrg 18428d7b3dSmrg drmSize backbufferSize; 19428d7b3dSmrg drm_handle_t backbuffer; 20428d7b3dSmrg 21428d7b3dSmrg drmSize depthbufferSize; 22428d7b3dSmrg drm_handle_t depthbuffer; 23428d7b3dSmrg 24428d7b3dSmrg drm_handle_t textures; 25428d7b3dSmrg int textureSize; 26428d7b3dSmrg 27428d7b3dSmrg drm_handle_t agp_buffers; 28428d7b3dSmrg drmSize agp_buf_size; 29428d7b3dSmrg 30428d7b3dSmrg int deviceID; 31428d7b3dSmrg int width; 32428d7b3dSmrg int height; 33428d7b3dSmrg int mem; 34428d7b3dSmrg int cpp; 35428d7b3dSmrg int bitsPerPixel; 36428d7b3dSmrg int fbOffset; 37428d7b3dSmrg int fbStride; 38428d7b3dSmrg 39428d7b3dSmrg int backOffset; 40428d7b3dSmrg int depthOffset; 41428d7b3dSmrg 42428d7b3dSmrg int auxPitch; 43428d7b3dSmrg int auxPitchBits; 44428d7b3dSmrg 45428d7b3dSmrg int logTextureGranularity; 46428d7b3dSmrg int textureOffset; 47428d7b3dSmrg 48428d7b3dSmrg /* For non-dma direct rendering. 49428d7b3dSmrg */ 50428d7b3dSmrg int ringOffset; 51428d7b3dSmrg int ringSize; 52428d7b3dSmrg 53428d7b3dSmrg drmBufMapPtr drmBufs; 54428d7b3dSmrg int irq; 55428d7b3dSmrg unsigned int sarea_priv_offset; 56428d7b3dSmrg 57428d7b3dSmrg} I810DRIRec, *I810DRIPtr; 58428d7b3dSmrg 59428d7b3dSmrg/* WARNING: Do not change the SAREA structure without changing the kernel 60428d7b3dSmrg * as well */ 61428d7b3dSmrg 62428d7b3dSmrg#define I810_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */ 63428d7b3dSmrg#define I810_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */ 64428d7b3dSmrg#define I810_UPLOAD_CTX 0x4 65428d7b3dSmrg#define I810_UPLOAD_BUFFERS 0x8 66428d7b3dSmrg#define I810_UPLOAD_TEX0 0x10 67428d7b3dSmrg#define I810_UPLOAD_TEX1 0x20 68428d7b3dSmrg#define I810_UPLOAD_CLIPRECTS 0x40 69428d7b3dSmrg 70428d7b3dSmrgtypedef struct { 71428d7b3dSmrg unsigned char next, prev; /* indices to form a circular LRU */ 72428d7b3dSmrg unsigned char in_use; /* owned by a client, or free? */ 73428d7b3dSmrg int age; /* tracked by clients to update local LRU's */ 74428d7b3dSmrg} I810TexRegionRec, *I810TexRegionPtr; 75428d7b3dSmrg 76428d7b3dSmrgtypedef struct { 77428d7b3dSmrg unsigned int ContextState[I810_CTX_SETUP_SIZE]; 78428d7b3dSmrg unsigned int BufferState[I810_DEST_SETUP_SIZE]; 79428d7b3dSmrg unsigned int TexState[2][I810_TEX_SETUP_SIZE]; 80428d7b3dSmrg unsigned int dirty; 81428d7b3dSmrg 82428d7b3dSmrg unsigned int nbox; 83428d7b3dSmrg drm_clip_rect_t boxes[I810_NR_SAREA_CLIPRECTS]; 84428d7b3dSmrg 85428d7b3dSmrg /* Maintain an LRU of contiguous regions of texture space. If 86428d7b3dSmrg * you think you own a region of texture memory, and it has an 87428d7b3dSmrg * age different to the one you set, then you are mistaken and 88428d7b3dSmrg * it has been stolen by another client. If global texAge 89428d7b3dSmrg * hasn't changed, there is no need to walk the list. 90428d7b3dSmrg * 91428d7b3dSmrg * These regions can be used as a proxy for the fine-grained 92428d7b3dSmrg * texture information of other clients - by maintaining them 93428d7b3dSmrg * in the same lru which is used to age their own textures, 94428d7b3dSmrg * clients have an approximate lru for the whole of global 95428d7b3dSmrg * texture space, and can make informed decisions as to which 96428d7b3dSmrg * areas to kick out. There is no need to choose whether to 97428d7b3dSmrg * kick out your own texture or someone else's - simply eject 98428d7b3dSmrg * them all in LRU order. 99428d7b3dSmrg */ 100428d7b3dSmrg 101428d7b3dSmrg drmTextureRegion texList[I810_NR_TEX_REGIONS + 1]; 102428d7b3dSmrg 103428d7b3dSmrg /* Last elt is sentinal */ 104428d7b3dSmrg int texAge; /* last time texture was uploaded */ 105428d7b3dSmrg 106428d7b3dSmrg int last_enqueue; /* last time a buffer was enqueued */ 107428d7b3dSmrg int last_dispatch; /* age of the most recently dispatched buffer */ 108428d7b3dSmrg int last_quiescent; /* */ 109428d7b3dSmrg 110428d7b3dSmrg int ctxOwner; /* last context to upload state */ 111428d7b3dSmrg 112428d7b3dSmrg int vertex_prim; 113428d7b3dSmrg 114428d7b3dSmrg int pf_enabled; /* is pageflipping allowed? */ 115428d7b3dSmrg int pf_active; /* is pageflipping active right now? */ 116428d7b3dSmrg int pf_current_page; /* which buffer is being displayed? */ 117428d7b3dSmrg 118428d7b3dSmrg 119428d7b3dSmrg} I810SAREARec, *I810SAREAPtr; 120428d7b3dSmrg 121428d7b3dSmrgtypedef struct { 122428d7b3dSmrg /* Nothing here yet */ 123428d7b3dSmrg int dummy; 124428d7b3dSmrg} I810ConfigPrivRec, *I810ConfigPrivPtr; 125428d7b3dSmrg 126428d7b3dSmrgtypedef struct { 127428d7b3dSmrg /* Nothing here yet */ 128428d7b3dSmrg int dummy; 129428d7b3dSmrg} I810DRIContextRec, *I810DRIContextPtr; 130428d7b3dSmrg 131428d7b3dSmrg#endif 132