1428d7b3dSmrg/************************************************************************** 2428d7b3dSmrg 3428d7b3dSmrgCopyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. 4428d7b3dSmrgCopyright © 2002 David Dawes 5428d7b3dSmrg 6428d7b3dSmrgAll Rights Reserved. 7428d7b3dSmrg 8428d7b3dSmrgPermission is hereby granted, free of charge, to any person obtaining a 9428d7b3dSmrgcopy of this software and associated documentation files (the 10428d7b3dSmrg"Software"), to deal in the Software without restriction, including 11428d7b3dSmrgwithout limitation the rights to use, copy, modify, merge, publish, 12428d7b3dSmrgdistribute, sub license, and/or sell copies of the Software, and to 13428d7b3dSmrgpermit persons to whom the Software is furnished to do so, subject to 14428d7b3dSmrgthe following conditions: 15428d7b3dSmrg 16428d7b3dSmrgThe above copyright notice and this permission notice (including the 17428d7b3dSmrgnext paragraph) shall be included in all copies or substantial portions 18428d7b3dSmrgof the Software. 19428d7b3dSmrg 20428d7b3dSmrgTHE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21428d7b3dSmrgOR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22428d7b3dSmrgMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23428d7b3dSmrgIN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 24428d7b3dSmrgANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25428d7b3dSmrgTORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26428d7b3dSmrgSOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27428d7b3dSmrg 28428d7b3dSmrg**************************************************************************/ 29428d7b3dSmrg 30428d7b3dSmrg#ifndef _INTEL_BATCHBUFFER_H 31428d7b3dSmrg#define _INTEL_BATCHBUFFER_H 32428d7b3dSmrg 33428d7b3dSmrg#define BATCH_RESERVED 16 34428d7b3dSmrg 35428d7b3dSmrg 36428d7b3dSmrgvoid intel_batch_init(ScrnInfoPtr scrn); 37428d7b3dSmrgvoid intel_batch_teardown(ScrnInfoPtr scrn); 38428d7b3dSmrgvoid intel_batch_emit_flush(ScrnInfoPtr scrn); 39428d7b3dSmrgvoid intel_batch_submit(ScrnInfoPtr scrn); 40428d7b3dSmrg 41428d7b3dSmrgstatic inline int intel_batch_space(intel_screen_private *intel) 42428d7b3dSmrg{ 43428d7b3dSmrg return (intel->batch_bo->size - BATCH_RESERVED) - (4*intel->batch_used); 44428d7b3dSmrg} 45428d7b3dSmrg 46428d7b3dSmrgstatic inline int intel_vertex_space(intel_screen_private *intel) 47428d7b3dSmrg{ 48428d7b3dSmrg return intel->vertex_bo ? intel->vertex_bo->size - (4*intel->vertex_used) : 0; 49428d7b3dSmrg} 50428d7b3dSmrg 51428d7b3dSmrgstatic inline void 52428d7b3dSmrgintel_batch_require_space(ScrnInfoPtr scrn, intel_screen_private *intel, int sz) 53428d7b3dSmrg{ 54428d7b3dSmrg assert(sz < intel->batch_bo->size - 8); 55428d7b3dSmrg if (intel_batch_space(intel) < sz) 56428d7b3dSmrg intel_batch_submit(scrn); 57428d7b3dSmrg} 58428d7b3dSmrg 59428d7b3dSmrgstatic inline void intel_batch_start_atomic(ScrnInfoPtr scrn, int sz) 60428d7b3dSmrg{ 61428d7b3dSmrg intel_screen_private *intel = intel_get_screen_private(scrn); 62428d7b3dSmrg 63428d7b3dSmrg assert(!intel->in_batch_atomic); 64428d7b3dSmrg 65428d7b3dSmrg if (intel->current_batch != RENDER_BATCH) { 66428d7b3dSmrg if (intel->current_batch && intel->context_switch) 67428d7b3dSmrg intel->context_switch(intel, RENDER_BATCH); 68428d7b3dSmrg } 69428d7b3dSmrg 70428d7b3dSmrg intel_batch_require_space(scrn, intel, sz * 4); 71428d7b3dSmrg intel->current_batch = RENDER_BATCH; 72428d7b3dSmrg 73428d7b3dSmrg intel->in_batch_atomic = TRUE; 74428d7b3dSmrg intel->batch_atomic_limit = intel->batch_used + sz; 75428d7b3dSmrg} 76428d7b3dSmrg 77428d7b3dSmrgstatic inline void intel_batch_end_atomic(ScrnInfoPtr scrn) 78428d7b3dSmrg{ 79428d7b3dSmrg intel_screen_private *intel = intel_get_screen_private(scrn); 80428d7b3dSmrg 81428d7b3dSmrg assert(intel->in_batch_atomic); 82428d7b3dSmrg assert(intel->batch_used <= intel->batch_atomic_limit); 83428d7b3dSmrg intel->in_batch_atomic = FALSE; 84428d7b3dSmrg} 85428d7b3dSmrg 86428d7b3dSmrgstatic inline void intel_batch_emit_dword(intel_screen_private *intel, uint32_t dword) 87428d7b3dSmrg{ 88428d7b3dSmrg intel->batch_ptr[intel->batch_used++] = dword; 89428d7b3dSmrg} 90428d7b3dSmrg 91428d7b3dSmrgstatic inline void intel_batch_align(intel_screen_private *intel, uint32_t align) 92428d7b3dSmrg{ 93428d7b3dSmrg uint32_t delta; 94428d7b3dSmrg 95428d7b3dSmrg align /= 4; 96428d7b3dSmrg assert(align); 97428d7b3dSmrg 98428d7b3dSmrg if ((delta = intel->batch_used & (align - 1))) { 99428d7b3dSmrg delta = align - delta; 100428d7b3dSmrg memset (intel->batch_ptr + intel->batch_used, 0, 4*delta); 101428d7b3dSmrg intel->batch_used += delta; 102428d7b3dSmrg } 103428d7b3dSmrg} 104428d7b3dSmrg 105428d7b3dSmrgstatic inline void 106428d7b3dSmrgintel_batch_emit_reloc(intel_screen_private *intel, 107428d7b3dSmrg dri_bo * bo, 108428d7b3dSmrg uint32_t read_domains, 109428d7b3dSmrg uint32_t write_domains, uint32_t delta, int needs_fence) 110428d7b3dSmrg{ 111428d7b3dSmrg uint64_t offset; 112428d7b3dSmrg 113428d7b3dSmrg if (needs_fence) 114428d7b3dSmrg drm_intel_bo_emit_reloc_fence(intel->batch_bo, 115428d7b3dSmrg intel->batch_used * 4, 116428d7b3dSmrg bo, delta, 117428d7b3dSmrg read_domains, write_domains); 118428d7b3dSmrg else 119428d7b3dSmrg drm_intel_bo_emit_reloc(intel->batch_bo, intel->batch_used * 4, 120428d7b3dSmrg bo, delta, 121428d7b3dSmrg read_domains, write_domains); 122428d7b3dSmrg 123428d7b3dSmrg offset = bo->offset64 + delta; 124428d7b3dSmrg 125428d7b3dSmrg intel_batch_emit_dword(intel, offset); 126428d7b3dSmrg if (INTEL_INFO(intel)->gen >= 0100) 127428d7b3dSmrg intel_batch_emit_dword(intel, offset >> 32); 128428d7b3dSmrg} 129428d7b3dSmrg 130428d7b3dSmrgstatic inline void 131428d7b3dSmrgintel_batch_mark_pixmap_domains(intel_screen_private *intel, 132428d7b3dSmrg struct intel_uxa_pixmap *priv, 133428d7b3dSmrg uint32_t read_domains, uint32_t write_domain) 134428d7b3dSmrg{ 135428d7b3dSmrg assert (read_domains); 136428d7b3dSmrg assert (write_domain == 0 || write_domain == read_domains); 137428d7b3dSmrg 138428d7b3dSmrg if (list_is_empty(&priv->batch)) 139428d7b3dSmrg list_add(&priv->batch, &intel->batch_pixmaps); 140428d7b3dSmrg 141428d7b3dSmrg priv->dirty |= write_domain != 0; 142428d7b3dSmrg priv->busy = 1; 143428d7b3dSmrg 144428d7b3dSmrg intel->needs_flush |= write_domain != 0; 145428d7b3dSmrg} 146428d7b3dSmrg 147428d7b3dSmrgstatic inline void 148428d7b3dSmrgintel_batch_emit_reloc_pixmap(intel_screen_private *intel, PixmapPtr pixmap, 149428d7b3dSmrg uint32_t read_domains, uint32_t write_domain, 150428d7b3dSmrg uint32_t delta, int needs_fence) 151428d7b3dSmrg{ 152428d7b3dSmrg struct intel_uxa_pixmap *priv = intel_uxa_get_pixmap_private(pixmap); 153428d7b3dSmrg 154428d7b3dSmrg intel_batch_mark_pixmap_domains(intel, priv, read_domains, write_domain); 155428d7b3dSmrg 156428d7b3dSmrg intel_batch_emit_reloc(intel, priv->bo, 157428d7b3dSmrg read_domains, write_domain, 158428d7b3dSmrg delta, needs_fence); 159428d7b3dSmrg} 160428d7b3dSmrg 161428d7b3dSmrg#define ALIGN_BATCH(align) intel_batch_align(intel, align); 162428d7b3dSmrg#define OUT_BATCH(dword) intel_batch_emit_dword(intel, dword) 163428d7b3dSmrg 164428d7b3dSmrg#define OUT_RELOC(bo, read_domains, write_domains, delta) \ 165428d7b3dSmrg intel_batch_emit_reloc(intel, bo, read_domains, write_domains, delta, 0) 166428d7b3dSmrg 167428d7b3dSmrg#define OUT_RELOC_FENCED(bo, read_domains, write_domains, delta) \ 168428d7b3dSmrg intel_batch_emit_reloc(intel, bo, read_domains, write_domains, delta, 1) 169428d7b3dSmrg 170428d7b3dSmrg#define OUT_RELOC_PIXMAP(pixmap, reads, write, delta) \ 171428d7b3dSmrg intel_batch_emit_reloc_pixmap(intel, pixmap, reads, write, delta, 0) 172428d7b3dSmrg 173428d7b3dSmrg#define OUT_RELOC_PIXMAP_FENCED(pixmap, reads, write, delta) \ 174428d7b3dSmrg intel_batch_emit_reloc_pixmap(intel, pixmap, reads, write, delta, 1) 175428d7b3dSmrg 176428d7b3dSmrgunion intfloat { 177428d7b3dSmrg float f; 178428d7b3dSmrg unsigned int ui; 179428d7b3dSmrg}; 180428d7b3dSmrg 181428d7b3dSmrg#define OUT_BATCH_F(x) do { \ 182428d7b3dSmrg union intfloat tmp; \ 183428d7b3dSmrg tmp.f = (float)(x); \ 184428d7b3dSmrg OUT_BATCH(tmp.ui); \ 185428d7b3dSmrg} while(0) 186428d7b3dSmrg 187428d7b3dSmrg#define __BEGIN_BATCH(n,batch_idx) \ 188428d7b3dSmrgdo { \ 189428d7b3dSmrg if (intel->batch_emitting != 0) \ 190428d7b3dSmrg FatalError("%s: BEGIN_BATCH called without closing " \ 191428d7b3dSmrg "ADVANCE_BATCH\n", __FUNCTION__); \ 192428d7b3dSmrg assert(!intel->in_batch_atomic); \ 193428d7b3dSmrg if (intel->current_batch != batch_idx) { \ 194428d7b3dSmrg if (intel->current_batch && intel->context_switch) \ 195428d7b3dSmrg intel->context_switch(intel, batch_idx); \ 196428d7b3dSmrg } \ 197428d7b3dSmrg intel_batch_require_space(scrn, intel, (n) * 4); \ 198428d7b3dSmrg intel->current_batch = batch_idx; \ 199428d7b3dSmrg intel->batch_emitting = (n); \ 200428d7b3dSmrg intel->batch_emit_start = intel->batch_used; \ 201428d7b3dSmrg} while (0) 202428d7b3dSmrg 203428d7b3dSmrg#define BEGIN_BATCH(n) __BEGIN_BATCH(n,RENDER_BATCH) 204428d7b3dSmrg#define BEGIN_BATCH_BLT(n) __BEGIN_BATCH(n,BLT_BATCH) 205428d7b3dSmrg 206428d7b3dSmrg#define ADVANCE_BATCH() do { \ 207428d7b3dSmrg if (intel->batch_emitting == 0) \ 208428d7b3dSmrg FatalError("%s: ADVANCE_BATCH called with no matching " \ 209428d7b3dSmrg "BEGIN_BATCH\n", __FUNCTION__); \ 210428d7b3dSmrg if (intel->batch_used > \ 211428d7b3dSmrg intel->batch_emit_start + intel->batch_emitting) \ 212428d7b3dSmrg FatalError("%s: ADVANCE_BATCH: exceeded allocation %d/%d\n ", \ 213428d7b3dSmrg __FUNCTION__, \ 214428d7b3dSmrg intel->batch_used - intel->batch_emit_start, \ 215428d7b3dSmrg intel->batch_emitting); \ 216428d7b3dSmrg if (intel->batch_used < intel->batch_emit_start + \ 217428d7b3dSmrg intel->batch_emitting) \ 218428d7b3dSmrg FatalError("%s: ADVANCE_BATCH: under-used allocation %d/%d\n ", \ 219428d7b3dSmrg __FUNCTION__, \ 220428d7b3dSmrg intel->batch_used - intel->batch_emit_start, \ 221428d7b3dSmrg intel->batch_emitting); \ 222428d7b3dSmrg intel->batch_emitting = 0; \ 223428d7b3dSmrg} while (0) 224428d7b3dSmrg 225428d7b3dSmrgvoid intel_next_vertex(intel_screen_private *intel); 226428d7b3dSmrgstatic inline void intel_vertex_emit(intel_screen_private *intel, float v) 227428d7b3dSmrg{ 228428d7b3dSmrg intel->vertex_ptr[intel->vertex_used++] = v; 229428d7b3dSmrg} 230428d7b3dSmrg#define OUT_VERTEX(v) intel_vertex_emit(intel, v) 231428d7b3dSmrg 232428d7b3dSmrg#endif /* _INTEL_BATCHBUFFER_H */ 233