1428d7b3dSmrg/***************************************************************************
2428d7b3dSmrg
3428d7b3dSmrgCopyright 2000 Intel Corporation.  All Rights Reserved.
4428d7b3dSmrg
5428d7b3dSmrgPermission is hereby granted, free of charge, to any person obtaining a
6428d7b3dSmrgcopy of this software and associated documentation files (the
7428d7b3dSmrg"Software"), to deal in the Software without restriction, including
8428d7b3dSmrgwithout limitation the rights to use, copy, modify, merge, publish,
9428d7b3dSmrgdistribute, sub license, and/or sell copies of the Software, and to
10428d7b3dSmrgpermit persons to whom the Software is furnished to do so, subject to
11428d7b3dSmrgthe following conditions:
12428d7b3dSmrg
13428d7b3dSmrgThe above copyright notice and this permission notice (including the
14428d7b3dSmrgnext paragraph) shall be included in all copies or substantial portions
15428d7b3dSmrgof the Software.
16428d7b3dSmrg
17428d7b3dSmrgTHE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18428d7b3dSmrgOR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19428d7b3dSmrgMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20428d7b3dSmrgIN NO EVENT SHALL INTEL, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
21428d7b3dSmrgDAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22428d7b3dSmrgOTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR
23428d7b3dSmrgTHE USE OR OTHER DEALINGS IN THE SOFTWARE.
24428d7b3dSmrg
25428d7b3dSmrg**************************************************************************/
26428d7b3dSmrg
27428d7b3dSmrg#ifndef _INTEL_VIDEO_H_
28428d7b3dSmrg#define _INTEL_VIDEO_H_
29428d7b3dSmrg
30428d7b3dSmrg#include "xf86.h"
31428d7b3dSmrg#include "xf86_OSproc.h"
32428d7b3dSmrg
33428d7b3dSmrgtypedef struct {
34428d7b3dSmrg	uint32_t YBufOffset;
35428d7b3dSmrg	uint32_t UBufOffset;
36428d7b3dSmrg	uint32_t VBufOffset;
37428d7b3dSmrg
38428d7b3dSmrg	int brightness;
39428d7b3dSmrg	int contrast;
40428d7b3dSmrg	int saturation;
41428d7b3dSmrg	xf86CrtcPtr desired_crtc;
42428d7b3dSmrg
43428d7b3dSmrg	RegionRec clip;
44428d7b3dSmrg	uint32_t colorKey;
45428d7b3dSmrg
46428d7b3dSmrg	uint32_t gamma0;
47428d7b3dSmrg	uint32_t gamma1;
48428d7b3dSmrg	uint32_t gamma2;
49428d7b3dSmrg	uint32_t gamma3;
50428d7b3dSmrg	uint32_t gamma4;
51428d7b3dSmrg	uint32_t gamma5;
52428d7b3dSmrg
53428d7b3dSmrg	/* only used by the overlay */
54428d7b3dSmrg	uint32_t videoStatus;
55428d7b3dSmrg	Time offTime;
56428d7b3dSmrg	Time freeTime;
57428d7b3dSmrg	/** YUV data buffers */
58428d7b3dSmrg	drm_intel_bo *buf, *old_buf[2];
59428d7b3dSmrg	Bool reusable;
60428d7b3dSmrg
61428d7b3dSmrg	Bool textured;
62428d7b3dSmrg	Rotation rotation;	/* should remove intel->rotation later */
63428d7b3dSmrg
64428d7b3dSmrg	int SyncToVblank;	/* -1: auto, 0: off, 1: on */
65428d7b3dSmrg} intel_adaptor_private;
66428d7b3dSmrg
67428d7b3dSmrg#define OFF_DELAY	250	/* milliseconds */
68428d7b3dSmrg
69428d7b3dSmrg#define OFF_TIMER	0x01
70428d7b3dSmrg#define CLIENT_VIDEO_ON	0x02
71428d7b3dSmrg
72428d7b3dSmrgstatic inline intel_adaptor_private *
73428d7b3dSmrgintel_get_adaptor_private(intel_screen_private *intel)
74428d7b3dSmrg{
75428d7b3dSmrg	return intel->adaptor->pPortPrivates[0].ptr;
76428d7b3dSmrg}
77428d7b3dSmrg
78428d7b3dSmrgint is_planar_fourcc(int id);
79428d7b3dSmrg
80428d7b3dSmrgvoid intel_video_block_handler(intel_screen_private *intel);
81428d7b3dSmrg
82428d7b3dSmrgint intel_video_query_image_attributes(ScrnInfoPtr, int, unsigned short *,
83428d7b3dSmrg                                       unsigned short *, int *, int *);
84428d7b3dSmrg
85428d7b3dSmrgBool
86428d7b3dSmrgintel_video_copy_data(ScrnInfoPtr scrn, intel_adaptor_private *adaptor_priv,
87428d7b3dSmrg                      short width, short height, int *dstPitch, int *dstPitch2,
88428d7b3dSmrg                      int top, int left, int npixels, int nlines,
89428d7b3dSmrg                      int id, unsigned char *buf);
90428d7b3dSmrg
91428d7b3dSmrgBool
92428d7b3dSmrgintel_clip_video_helper(ScrnInfoPtr scrn,
93428d7b3dSmrg			intel_adaptor_private *adaptor_priv,
94428d7b3dSmrg			xf86CrtcPtr * crtc_ret,
95428d7b3dSmrg			BoxPtr dst,
96428d7b3dSmrg			short src_x, short src_y,
97428d7b3dSmrg			short drw_x, short drw_y,
98428d7b3dSmrg			short src_w, short src_h,
99428d7b3dSmrg			short drw_w, short drw_h,
100428d7b3dSmrg			int id,
101428d7b3dSmrg			int *top, int* left, int* npixels, int *nlines,
102428d7b3dSmrg			RegionPtr reg, INT32 width, INT32 height);
103428d7b3dSmrg
104428d7b3dSmrgvoid
105428d7b3dSmrgintel_free_video_buffers(intel_adaptor_private *adaptor_priv);
106428d7b3dSmrg
107428d7b3dSmrgint
108428d7b3dSmrgintel_video_get_port_attribute(ScrnInfoPtr scrn,
109428d7b3dSmrg                               Atom attribute, INT32 * value, pointer data);
110428d7b3dSmrg
111428d7b3dSmrgvoid
112428d7b3dSmrgintel_video_query_best_size(ScrnInfoPtr, Bool,
113428d7b3dSmrg                            short, short, short, short, unsigned int *,
114428d7b3dSmrg                            unsigned int *, pointer);
115428d7b3dSmrg
116428d7b3dSmrgvoid
117428d7b3dSmrgintel_setup_dst_params(ScrnInfoPtr scrn, intel_adaptor_private *adaptor_priv, short width,
118428d7b3dSmrg		       short height, int *dstPitch, int *dstPitch2, int *size,
119428d7b3dSmrg		       int id);
120428d7b3dSmrg
121428d7b3dSmrgvoid intel_video_stop_video(ScrnInfoPtr scrn, pointer data, Bool shutdown);
122428d7b3dSmrg
123428d7b3dSmrgextern Atom intel_xv_Brightness, intel_xv_Contrast, intel_xv_Saturation, intel_xv_ColorKey, intel_xv_Pipe;
124428d7b3dSmrgextern Atom intel_xv_Gamma0, intel_xv_Gamma1, intel_xv_Gamma2, intel_xv_Gamma3, intel_xv_Gamma4, intel_xv_Gamma5;
125428d7b3dSmrgextern Atom intel_xv_SyncToVblank;
126428d7b3dSmrg
127428d7b3dSmrg#define MAKE_ATOM(a) MakeAtom(a, sizeof(a) - 1, TRUE)
128428d7b3dSmrg
129428d7b3dSmrg/* Limits for the overlay/textured video source sizes.  The documented hardware
130428d7b3dSmrg * limits are 2048x2048 or better for overlay and both of our textured video
131428d7b3dSmrg * implementations.  Additionally, on the 830 and 845, larger sizes resulted in
132428d7b3dSmrg * the card hanging, so we keep the limits lower there.
133428d7b3dSmrg */
134428d7b3dSmrg#define IMAGE_MAX_WIDTH		2048
135428d7b3dSmrg#define IMAGE_MAX_HEIGHT	2048
136428d7b3dSmrg#define IMAGE_MAX_WIDTH_LEGACY	1024
137428d7b3dSmrg#define IMAGE_MAX_HEIGHT_LEGACY	1088
138428d7b3dSmrg
139428d7b3dSmrgextern const XF86VideoEncodingRec intel_xv_dummy_encoding[1];
140428d7b3dSmrg
141428d7b3dSmrg#define NUM_FORMATS 3
142428d7b3dSmrg
143428d7b3dSmrgextern XF86VideoFormatRec intel_xv_formats[NUM_FORMATS];
144428d7b3dSmrg
145428d7b3dSmrg#define NUM_ATTRIBUTES 5
146428d7b3dSmrg
147428d7b3dSmrgextern XF86AttributeRec intel_xv_attributes[NUM_ATTRIBUTES];
148428d7b3dSmrg
149428d7b3dSmrg#define GAMMA_ATTRIBUTES 6
150428d7b3dSmrg
151428d7b3dSmrgextern XF86AttributeRec intel_xv_gamma_attributes[GAMMA_ATTRIBUTES];
152428d7b3dSmrg
153428d7b3dSmrg#ifdef INTEL_XVMC
154428d7b3dSmrg#define NUM_IMAGES 5
155428d7b3dSmrg#define XVMC_IMAGE 1
156428d7b3dSmrg#else
157428d7b3dSmrg#define NUM_IMAGES 4
158428d7b3dSmrg#define XVMC_IMAGE 0
159428d7b3dSmrg#endif
160428d7b3dSmrg
161428d7b3dSmrgextern XF86ImageRec intel_xv_images[NUM_IMAGES];
162428d7b3dSmrg
163428d7b3dSmrg#endif /* _INTEL_VIDEO_H_ */
164