1428d7b3dSmrg/*
2428d7b3dSmrg * Copyright © 2007 Intel Corporation
3428d7b3dSmrg *
4428d7b3dSmrg * Permission is hereby granted, free of charge, to any person obtaining a
5428d7b3dSmrg * copy of this software and associated documentation files (the "Software"),
6428d7b3dSmrg * to deal in the Software without restriction, including without limitation
7428d7b3dSmrg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8428d7b3dSmrg * and/or sell copies of the Software, and to permit persons to whom the
9428d7b3dSmrg * Software is furnished to do so, subject to the following conditions:
10428d7b3dSmrg *
11428d7b3dSmrg * The above copyright notice and this permission notice (including the next
12428d7b3dSmrg * paragraph) shall be included in all copies or substantial portions of the
13428d7b3dSmrg * Software.
14428d7b3dSmrg *
15428d7b3dSmrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16428d7b3dSmrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17428d7b3dSmrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18428d7b3dSmrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19428d7b3dSmrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20428d7b3dSmrg * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21428d7b3dSmrg * SOFTWARE.
22428d7b3dSmrg *
23428d7b3dSmrg * Authors:
24428d7b3dSmrg *    Zhenyu Wang <zhenyu.z.wang@intel.com>
25428d7b3dSmrg *
26428d7b3dSmrg */
27428d7b3dSmrg#ifndef I830_HWMC_H
28428d7b3dSmrg#define I830_HWMC_H
29428d7b3dSmrg
30428d7b3dSmrg#define INTEL_XVMC_LIBNAME	"IntelXvMC"
31428d7b3dSmrg#define INTEL_XVMC_MAJOR	0
32428d7b3dSmrg#define INTEL_XVMC_MINOR	1
33428d7b3dSmrg#define INTEL_XVMC_PATCHLEVEL	0
34428d7b3dSmrg
35428d7b3dSmrg#define FOURCC_XVMC     (('C' << 24) + ('M' << 16) + ('V' << 8) + 'X')
36428d7b3dSmrg
37428d7b3dSmrg/*
38428d7b3dSmrg * Commands that client submits through XvPutImage:
39428d7b3dSmrg */
40428d7b3dSmrg
41428d7b3dSmrg#define INTEL_XVMC_COMMAND_DISPLAY      0x00
42428d7b3dSmrg#define INTEL_XVMC_COMMAND_UNDISPLAY    0x01
43428d7b3dSmrg
44428d7b3dSmrg/* hw xvmc support type */
45428d7b3dSmrg#define XVMC_I915_MPEG2_MC	0x01
46428d7b3dSmrg#define XVMC_I965_MPEG2_MC	0x02
47428d7b3dSmrg#define XVMC_I945_MPEG2_VLD	0x04
48428d7b3dSmrg#define XVMC_I965_MPEG2_VLD	0x08
49428d7b3dSmrg
50428d7b3dSmrgstruct intel_xvmc_hw_context {
51428d7b3dSmrg	unsigned int type;
52428d7b3dSmrg	union {
53428d7b3dSmrg		struct {
54428d7b3dSmrg			unsigned int use_phys_addr : 1;
55428d7b3dSmrg		} i915;
56428d7b3dSmrg		struct {
57428d7b3dSmrg			unsigned int is_g4x:1;
58428d7b3dSmrg			unsigned int is_965_q:1;
59428d7b3dSmrg			unsigned int is_igdng:1;
60428d7b3dSmrg		} i965;
61428d7b3dSmrg	};
62428d7b3dSmrg};
63428d7b3dSmrg
64428d7b3dSmrg/* Intel private XvMC command to DDX driver */
65428d7b3dSmrgstruct intel_xvmc_command {
66428d7b3dSmrg	uint32_t handle;
67428d7b3dSmrg};
68428d7b3dSmrg
69428d7b3dSmrg#ifdef _INTEL_XVMC_SERVER_
70428d7b3dSmrg#include <xf86xvmc.h>
71428d7b3dSmrg
72428d7b3dSmrgextern Bool intel_xvmc_adaptor_init(ScreenPtr);
73428d7b3dSmrg#endif
74428d7b3dSmrg
75428d7b3dSmrg#endif
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