1fa225cbcSrjs/*
2fa225cbcSrjs * Copyright © 2007 Intel Corporation
3fa225cbcSrjs *
4fa225cbcSrjs * Permission is hereby granted, free of charge, to any person obtaining a
5fa225cbcSrjs * copy of this software and associated documentation files (the "Software"),
6fa225cbcSrjs * to deal in the Software without restriction, including without limitation
7fa225cbcSrjs * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8fa225cbcSrjs * and/or sell copies of the Software, and to permit persons to whom the
9fa225cbcSrjs * Software is furnished to do so, subject to the following conditions:
10fa225cbcSrjs *
11fa225cbcSrjs * The above copyright notice and this permission notice (including the next
12fa225cbcSrjs * paragraph) shall be included in all copies or substantial portions of the
13fa225cbcSrjs * Software.
14fa225cbcSrjs *
15fa225cbcSrjs * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16fa225cbcSrjs * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17fa225cbcSrjs * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18fa225cbcSrjs * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19fa225cbcSrjs * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20fa225cbcSrjs * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21fa225cbcSrjs * SOFTWARE.
22fa225cbcSrjs *
23fa225cbcSrjs * Authors:
24fa225cbcSrjs *    Zhenyu Wang <zhenyu.z.wang@intel.com>
25fa225cbcSrjs *
26fa225cbcSrjs */
27fa225cbcSrjs#ifndef I830_HWMC_H
28fa225cbcSrjs#define I830_HWMC_H
29fa225cbcSrjs
30fa225cbcSrjs#define INTEL_XVMC_LIBNAME	"IntelXvMC"
31fa225cbcSrjs#define INTEL_XVMC_MAJOR	0
32fa225cbcSrjs#define INTEL_XVMC_MINOR	1
33fa225cbcSrjs#define INTEL_XVMC_PATCHLEVEL	0
34fa225cbcSrjs
35fa225cbcSrjs#define FOURCC_XVMC     (('C' << 24) + ('M' << 16) + ('V' << 8) + 'X')
36fa225cbcSrjs
37fa225cbcSrjs/*
38fa225cbcSrjs * Commands that client submits through XvPutImage:
39fa225cbcSrjs */
40fa225cbcSrjs
41fa225cbcSrjs#define INTEL_XVMC_COMMAND_DISPLAY      0x00
42fa225cbcSrjs#define INTEL_XVMC_COMMAND_UNDISPLAY    0x01
43fa225cbcSrjs
44fa225cbcSrjs/* hw xvmc support type */
45fa225cbcSrjs#define XVMC_I915_MPEG2_MC	0x01
46fa225cbcSrjs#define XVMC_I965_MPEG2_MC	0x02
47fa225cbcSrjs#define XVMC_I945_MPEG2_VLD	0x04
48fa225cbcSrjs#define XVMC_I965_MPEG2_VLD	0x08
49fa225cbcSrjs
50fa225cbcSrjs/* supported surface types */
51fa225cbcSrjsenum {
52fa225cbcSrjs    SURFACE_TYPE_MPEG2_MPML = FOURCC_XVMC, /* mpeg2 MP@ML */
53fa225cbcSrjs    SURFACE_TYPE_MPEG1_MPML,		   /* mpeg1 MP@ML */
54fa225cbcSrjs    SURFACE_TYPE_MAX
55fa225cbcSrjs};
56fa225cbcSrjs
57fa225cbcSrjs/* common header for context private */
58fa225cbcSrjsstruct hwmc_buffer
59fa225cbcSrjs{
60fa225cbcSrjs    drm_handle_t handle;
61fa225cbcSrjs    unsigned long offset;
62fa225cbcSrjs    unsigned long size;
63fa225cbcSrjs    unsigned long bus_addr;
64fa225cbcSrjs};
65fa225cbcSrjs
66fa225cbcSrjsstruct _intel_xvmc_common {
67fa225cbcSrjs    unsigned int type;
68fa225cbcSrjs    struct hwmc_buffer batchbuffer;
69fa225cbcSrjs    unsigned int kernel_exec_fencing:1;
70fa225cbcSrjs};
71fa225cbcSrjs
72fa225cbcSrjs/* Intel private XvMC command to DDX driver */
73fa225cbcSrjsstruct intel_xvmc_command {
74fa225cbcSrjs    unsigned int command;
75fa225cbcSrjs    unsigned int ctxNo;
76fa225cbcSrjs    unsigned int srfNo;
77fa225cbcSrjs    unsigned int subPicNo;
78fa225cbcSrjs    unsigned int flags;
79fa225cbcSrjs    unsigned int real_id;
80fa225cbcSrjs    uint32_t handle;
81fa225cbcSrjs    unsigned int pad[5];
82fa225cbcSrjs};
83fa225cbcSrjs
84fa225cbcSrjs#ifdef _INTEL_XVMC_SERVER_
85fa225cbcSrjs#include <xf86xvmc.h>
86fa225cbcSrjs
87fa225cbcSrjsstruct intel_xvmc_driver {
88fa225cbcSrjs    char *name;
89fa225cbcSrjs    XF86MCAdaptorPtr adaptor;
90fa225cbcSrjs    unsigned int flag;
91fa225cbcSrjs    i830_memory *batch;
92fa225cbcSrjs    drm_handle_t batch_handle;
93fa225cbcSrjs
94fa225cbcSrjs    /* more items for xvmv surface manage? */
95fa225cbcSrjs    Bool (*init)(ScrnInfoPtr, XF86VideoAdaptorPtr);
96fa225cbcSrjs    void (*fini)(ScrnInfoPtr);
97fa225cbcSrjs    void* devPrivate;
98fa225cbcSrjs};
99fa225cbcSrjs
100fa225cbcSrjsextern struct intel_xvmc_driver *xvmc_driver;
101fa225cbcSrjsextern struct intel_xvmc_driver i915_xvmc_driver;
102fa225cbcSrjsextern struct intel_xvmc_driver i965_xvmc_driver;
103fa225cbcSrjsextern struct intel_xvmc_driver vld_xvmc_driver;
104fa225cbcSrjs
105fa225cbcSrjsextern Bool intel_xvmc_probe(ScrnInfoPtr);
106fa225cbcSrjsextern Bool intel_xvmc_driver_init(ScreenPtr, XF86VideoAdaptorPtr);
107fa225cbcSrjsextern Bool intel_xvmc_screen_init(ScreenPtr);
108fa225cbcSrjsextern void intel_xvmc_finish(ScrnInfoPtr);
109fa225cbcSrjsextern int  intel_xvmc_put_image_size(ScrnInfoPtr);
110fa225cbcSrjsextern Bool intel_xvmc_init_batch(ScrnInfoPtr);
111fa225cbcSrjsextern void intel_xvmc_fini_batch(ScrnInfoPtr);
112fa225cbcSrjs#endif
113fa225cbcSrjs
114fa225cbcSrjs#endif
115