1fa225cbcSrjs/*
2fa225cbcSrjs * Copyright © 2009 Intel Corporation
3fa225cbcSrjs *
4fa225cbcSrjs * Permission is hereby granted, free of charge, to any person obtaining a
5fa225cbcSrjs * copy of this software and associated documentation files (the "Software"),
6fa225cbcSrjs * to deal in the Software without restriction, including without limitation
7fa225cbcSrjs * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8fa225cbcSrjs * and/or sell copies of the Software, and to permit persons to whom the
9fa225cbcSrjs * Software is furnished to do so, subject to the following conditions:
10fa225cbcSrjs *
11fa225cbcSrjs * The above copyright notice and this permission notice (including the next
12fa225cbcSrjs * paragraph) shall be included in all copies or substantial portions of the
13fa225cbcSrjs * Software.
14fa225cbcSrjs *
15fa225cbcSrjs * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16fa225cbcSrjs * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17fa225cbcSrjs * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18fa225cbcSrjs * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19fa225cbcSrjs * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20fa225cbcSrjs * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21fa225cbcSrjs * DEALINGS IN THE SOFTWARE.
22fa225cbcSrjs *
23fa225cbcSrjs * Authors:
24fa225cbcSrjs *    Zhenyu Wang <zhenyu.z.wang@intel.com>
25fa225cbcSrjs *    Wu Fengguang <fengguang.wu@intel.com>
26fa225cbcSrjs *
27fa225cbcSrjs */
28fa225cbcSrjs
29fa225cbcSrjs#include <stdio.h>
30fa225cbcSrjs#include <stdlib.h>
31fa225cbcSrjs#include <string.h>
32fa225cbcSrjs#include <stdarg.h>
33fa225cbcSrjs#include <sys/types.h>
34fa225cbcSrjs#include <sys/mman.h>
35fa225cbcSrjs#include <pciaccess.h>
36fa225cbcSrjs#include <err.h>
37fa225cbcSrjs#include <unistd.h>
38fa225cbcSrjs#include <fcntl.h>
39fa225cbcSrjs#include <getopt.h>
40fa225cbcSrjs
41fa225cbcSrjs
42fa225cbcSrjs#include "reg_dumper.h"
43fa225cbcSrjs#include "../i810_reg.h"
44fa225cbcSrjs
45fa225cbcSrjs#define dump_reg(reg, desc)					\
46fa225cbcSrjs    do {							\
47fa225cbcSrjs	    dword = INREG(reg);	  				\
48fa225cbcSrjs	    printf("%-18s 0x%08x  %s\n", # reg, dword, desc);	\
49fa225cbcSrjs    } while (0)
50fa225cbcSrjs
51fa225cbcSrjs#define BITSTO(n)		(n >= sizeof(long) * 8 ? ~0 : (1UL << (n)) - 1)
52fa225cbcSrjs#define BITMASK(high, low)	(BITSTO(high+1) & ~BITSTO(low))
53fa225cbcSrjs#define BITS(reg, high, low)	(((reg) & (BITMASK(high, low))) >> (low))
54fa225cbcSrjs#define BIT(reg, n)		BITS(reg, n, n)
55fa225cbcSrjs
56fa225cbcSrjs#define AUD_CONFIG		0x62000
57fa225cbcSrjs#define AUD_DEBUG		0x62010
58fa225cbcSrjs#define AUD_VID_DID		0x62020
59fa225cbcSrjs#define AUD_RID			0x62024
60fa225cbcSrjs#define AUD_SUBN_CNT		0x62028
61fa225cbcSrjs#define AUD_FUNC_GRP		0x62040
62fa225cbcSrjs#define AUD_SUBN_CNT2		0x62044
63fa225cbcSrjs#define AUD_GRP_CAP		0x62048
64fa225cbcSrjs#define AUD_PWRST		0x6204c
65fa225cbcSrjs#define AUD_SUPPWR		0x62050
66fa225cbcSrjs#define AUD_SID			0x62054
67fa225cbcSrjs#define AUD_OUT_CWCAP		0x62070
68fa225cbcSrjs#define AUD_OUT_PCMSIZE		0x62074
69fa225cbcSrjs#define AUD_OUT_STR		0x62078
70fa225cbcSrjs#define AUD_OUT_DIG_CNVT	0x6207c
71fa225cbcSrjs#define AUD_OUT_CH_STR		0x62080
72fa225cbcSrjs#define AUD_OUT_STR_DESC	0x62084
73fa225cbcSrjs#define AUD_PINW_CAP		0x620a0
74fa225cbcSrjs#define AUD_PIN_CAP		0x620a4
75fa225cbcSrjs#define AUD_PINW_CONNLNG	0x620a8
76fa225cbcSrjs#define AUD_PINW_CONNLST	0x620ac
77fa225cbcSrjs#define AUD_PINW_CNTR		0x620b0
78fa225cbcSrjs#define AUD_PINW_UNSOLRESP	0x620b8
79fa225cbcSrjs#define AUD_CNTL_ST		0x620b4
80fa225cbcSrjs#define AUD_PINW_CONFIG		0x620bc
81fa225cbcSrjs#define AUD_HDMIW_STATUS	0x620d4
82fa225cbcSrjs#define AUD_HDMIW_HDMIEDID	0x6210c
83fa225cbcSrjs#define AUD_HDMIW_INFOFR	0x62118
84fa225cbcSrjs#define AUD_CONV_CHCNT 		0x62120
85fa225cbcSrjs#define AUD_CTS_ENABLE		0x62128
86fa225cbcSrjs
87fa225cbcSrjs#define VIDEO_DIP_CTL		0x61170
88fa225cbcSrjs#define VIDEO_DIP_ENABLE	(1<<31)
89fa225cbcSrjs#define VIDEO_DIP_ENABLE_AVI	(1<<21)
90fa225cbcSrjs#define VIDEO_DIP_ENABLE_VENDOR	(1<<22)
91fa225cbcSrjs#define VIDEO_DIP_ENABLE_SPD	(1<<24)
92fa225cbcSrjs#define VIDEO_DIP_BUF_AVI	(0<<19)
93fa225cbcSrjs#define VIDEO_DIP_BUF_VENDOR	(1<<19)
94fa225cbcSrjs#define VIDEO_DIP_BUF_SPD	(3<<19)
95fa225cbcSrjs#define VIDEO_DIP_TRANS_ONCE	(0<<16)
96fa225cbcSrjs#define VIDEO_DIP_TRANS_1	(1<<16)
97fa225cbcSrjs#define VIDEO_DIP_TRANS_2	(2<<16)
98fa225cbcSrjs
99fa225cbcSrjs#define AUDIO_HOTPLUG_EN	(1<<24)
100fa225cbcSrjs
101fa225cbcSrjs#define min_t(type, x, y) ({                    \
102fa225cbcSrjs        type __min1 = (x);                      \
103fa225cbcSrjs        type __min2 = (y);                      \
104fa225cbcSrjs        __min1 < __min2 ? __min1: __min2; })
105fa225cbcSrjs
106fa225cbcSrjs#define OPNAME(names, index)   \
107fa225cbcSrjs               names[min_t(unsigned int, index, ARRAY_SIZE(names) - 1)]
108fa225cbcSrjs
109fa225cbcSrjsstatic char *pixel_clock[] = {
110fa225cbcSrjs	[0] = "25.2 / 1.001 MHz",
111fa225cbcSrjs	[1] = "25.2 MHz",
112fa225cbcSrjs	[2] = "27 MHz",
113fa225cbcSrjs	[3] = "27 * 1.001 MHz",
114fa225cbcSrjs	[4] = "54 MHz",
115fa225cbcSrjs	[5] = "54 * 1.001 MHz",
116fa225cbcSrjs	[6] = "74.25 / 1.001 MHz",
117fa225cbcSrjs	[7] = "74.25 MHz",
118fa225cbcSrjs	[8] = "148.5 / 1.001 MHz",
119fa225cbcSrjs	[9] = "148.5 MHz",
120fa225cbcSrjs	[10] = "Reserved",
121fa225cbcSrjs};
122fa225cbcSrjs
123fa225cbcSrjsstatic char *power_state[] = {
124fa225cbcSrjs	[0] = "D0",
125fa225cbcSrjs	[1] = "D1",
126fa225cbcSrjs	[2] = "D2",
127fa225cbcSrjs	[3] = "D3",
128fa225cbcSrjs};
129fa225cbcSrjs
130fa225cbcSrjsstatic char *stream_type[] = {
131fa225cbcSrjs	[0] = "default samples",
132fa225cbcSrjs	[1] = "one bit stream",
133fa225cbcSrjs	[2] = "DST stream",
134fa225cbcSrjs	[3] = "MLP stream",
135fa225cbcSrjs	[4] = "Reserved",
136fa225cbcSrjs};
137fa225cbcSrjs
138fa225cbcSrjsstatic char *dip_port[] = {
139fa225cbcSrjs	[0] = "Reserved",
140fa225cbcSrjs	[1] = "HDMI B",
141fa225cbcSrjs	[2] = "HDMI C",
142fa225cbcSrjs	[3] = "Reserved",
143fa225cbcSrjs};
144fa225cbcSrjs
145fa225cbcSrjsstatic char *dip_index[] = {
146fa225cbcSrjs	[0] = "Audio DIP",
147fa225cbcSrjs	[1] = "ACP DIP",
148fa225cbcSrjs	[2] = "ISRC1 DIP",
149fa225cbcSrjs	[3] = "ISRC2 DIP",
150fa225cbcSrjs	[4] = "Reserved",
151fa225cbcSrjs};
152fa225cbcSrjs
153fa225cbcSrjsstatic char *dip_trans[] = {
154fa225cbcSrjs	[0] = "disabled",
155fa225cbcSrjs	[1] = "reserved",
156fa225cbcSrjs	[2] = "send once",
157fa225cbcSrjs	[3] = "best effort",
158fa225cbcSrjs};
159fa225cbcSrjs
160fa225cbcSrjsstatic char *video_dip_index[] = {
161fa225cbcSrjs	[0] = "AVI DIP",
162fa225cbcSrjs	[1] = "Vendor-specific DIP",
163fa225cbcSrjs	[2] = "Reserved",
164fa225cbcSrjs	[3] = "Source Product Description DIP",
165fa225cbcSrjs};
166fa225cbcSrjs
167fa225cbcSrjsstatic char *video_dip_trans[] = {
168fa225cbcSrjs	[0] = "send once",
169fa225cbcSrjs	[1] = "send every vsync",
170fa225cbcSrjs	[2] = "send at least every other vsync",
171fa225cbcSrjs	[3] = "reserved",
172fa225cbcSrjs};
173fa225cbcSrjs
174fa225cbcSrjsstatic void do_self_tests(void)
175fa225cbcSrjs{
176fa225cbcSrjs    if (BIT(1, 0) != 1)
177fa225cbcSrjs	    exit(1);
178fa225cbcSrjs    if (BIT(0x80000000, 31) != 1)
179fa225cbcSrjs	    exit(2);
180fa225cbcSrjs    if (BITS(0xc0000000, 31, 30) != 3)
181fa225cbcSrjs	    exit(3);
182fa225cbcSrjs}
183fa225cbcSrjs
184fa225cbcSrjsint main(int argc, char **argv)
185fa225cbcSrjs{
186fa225cbcSrjs    I830Rec i830;
187fa225cbcSrjs    I830Ptr pI830 = &i830;
188fa225cbcSrjs    uint32_t dword;
189fa225cbcSrjs    int i;
190fa225cbcSrjs
191fa225cbcSrjs    do_self_tests();
192fa225cbcSrjs    intel_i830rec_init(pI830);
193fa225cbcSrjs
194fa225cbcSrjs    /* printf("%-18s   %8s  %s\n\n", "register name", "raw value", "description"); */
195fa225cbcSrjs
196fa225cbcSrjs#if 0 /* enable HDMI audio bits */
197fa225cbcSrjs    dump_reg(SDVOB,		"Digital Display Port B Control Register");
198fa225cbcSrjs    dword |= SDVO_ENABLE;
199fa225cbcSrjs    dword |= SDVO_BORDER_ENABLE;
200fa225cbcSrjs    dword |= SDVO_AUDIO_ENABLE;
201fa225cbcSrjs    dword |= SDVO_NULL_PACKETS_DURING_VSYNC;
202fa225cbcSrjs    OUTREG(SDVOB, dword);
203fa225cbcSrjs
204fa225cbcSrjs    dump_reg(PORT_HOTPLUG_EN,	"Hot Plug Detect Enable");
205fa225cbcSrjs    OUTREG(PORT_HOTPLUG_EN, dword | AUDIO_HOTPLUG_EN);
206fa225cbcSrjs
207fa225cbcSrjs    dump_reg(VIDEO_DIP_CTL,	"Video DIP Control");
208fa225cbcSrjs    dword &= ~( VIDEO_DIP_ENABLE_AVI |
209fa225cbcSrjs		VIDEO_DIP_ENABLE_VENDOR |
210fa225cbcSrjs		VIDEO_DIP_ENABLE_SPD);
211fa225cbcSrjs    OUTREG(VIDEO_DIP_CTL, dword);
212fa225cbcSrjs    dword |= VIDEO_DIP_ENABLE;
213fa225cbcSrjs    OUTREG(VIDEO_DIP_CTL, dword);
214fa225cbcSrjs#endif
215fa225cbcSrjs
216fa225cbcSrjs#if 0 /* disable HDMI audio bits */
217fa225cbcSrjs    dump_reg(SDVOB,		"Digital Display Port B Control Register");
218fa225cbcSrjs    dword &= ~SDVO_AUDIO_ENABLE;
219fa225cbcSrjs    dword &= ~SDVO_NULL_PACKETS_DURING_VSYNC;
220fa225cbcSrjs    OUTREG(SDVOB, dword);
221fa225cbcSrjs#endif
222fa225cbcSrjs
223fa225cbcSrjs    dump_reg(VIDEO_DIP_CTL,	"Video DIP Control");
224fa225cbcSrjs    dump_reg(SDVOB,		"Digital Display Port B Control Register");
225fa225cbcSrjs    dump_reg(SDVOC,		"Digital Display Port C Control Register");
226fa225cbcSrjs    dump_reg(PORT_HOTPLUG_EN,	"Hot Plug Detect Enable");
227fa225cbcSrjs
228fa225cbcSrjs    dump_reg(AUD_CONFIG,	"Audio Configuration");
229fa225cbcSrjs    dump_reg(AUD_DEBUG,		"Audio Debug");
230fa225cbcSrjs    dump_reg(AUD_VID_DID,	"Audio Vendor ID / Device ID");
231fa225cbcSrjs    dump_reg(AUD_RID,		"Audio Revision ID");
232fa225cbcSrjs    dump_reg(AUD_SUBN_CNT,	"Audio Subordinate Node Count");
233fa225cbcSrjs    dump_reg(AUD_FUNC_GRP,	"Audio Function Group Type");
234fa225cbcSrjs    dump_reg(AUD_SUBN_CNT2,	"Audio Subordinate Node Count");
235fa225cbcSrjs    dump_reg(AUD_GRP_CAP,	"Audio Function Group Capabilities");
236fa225cbcSrjs    dump_reg(AUD_PWRST,		"Audio Power State");
237fa225cbcSrjs    dump_reg(AUD_SUPPWR,	"Audio Supported Power States");
238fa225cbcSrjs    dump_reg(AUD_SID,		"Audio Root Node Subsystem ID");
239fa225cbcSrjs    dump_reg(AUD_OUT_CWCAP,	"Audio Output Converter Widget Capabilities");
240fa225cbcSrjs    dump_reg(AUD_OUT_PCMSIZE,	"Audio PCM Size and Rates");
241fa225cbcSrjs    dump_reg(AUD_OUT_STR,	"Audio Stream Formats");
242fa225cbcSrjs    dump_reg(AUD_OUT_DIG_CNVT,	"Audio Digital Converter");
243fa225cbcSrjs    dump_reg(AUD_OUT_CH_STR,	"Audio Channel ID and Stream ID");
244fa225cbcSrjs    dump_reg(AUD_OUT_STR_DESC,	"Audio Stream Descriptor Format");
245fa225cbcSrjs    dump_reg(AUD_PINW_CAP,	"Audio Pin Complex Widget Capabilities");
246fa225cbcSrjs    dump_reg(AUD_PIN_CAP,	"Audio Pin Capabilities");
247fa225cbcSrjs    dump_reg(AUD_PINW_CONNLNG,	"Audio Connection List Length");
248fa225cbcSrjs    dump_reg(AUD_PINW_CONNLST,	"Audio Connection List Entry");
249fa225cbcSrjs    dump_reg(AUD_PINW_CNTR,	"Audio Pin Widget Control");
250fa225cbcSrjs    dump_reg(AUD_PINW_UNSOLRESP,"Audio Unsolicited Response Enable");
251fa225cbcSrjs    dump_reg(AUD_CNTL_ST,	"Audio Control State Register");
252fa225cbcSrjs    dump_reg(AUD_PINW_CONFIG,	"Audio Configuration Default");
253fa225cbcSrjs    dump_reg(AUD_HDMIW_STATUS,	"Audio HDMI Status");
254fa225cbcSrjs    dump_reg(AUD_HDMIW_HDMIEDID,"Audio HDMI Data EDID Block");
255fa225cbcSrjs    dump_reg(AUD_HDMIW_INFOFR,	"Audio HDMI Widget Data Island Packet");
256fa225cbcSrjs    dump_reg(AUD_CONV_CHCNT,	"Audio Converter Channel Count");
257fa225cbcSrjs    dump_reg(AUD_CTS_ENABLE,	"Audio CTS Programming Enable");
258fa225cbcSrjs
259fa225cbcSrjs    printf("\nDetails:\n\n");
260fa225cbcSrjs
261fa225cbcSrjs    dword = INREG(AUD_VID_DID);
262fa225cbcSrjs    printf("AUD_VID_DID vendor id\t\t\t0x%x\n", dword >> 16);
263fa225cbcSrjs    printf("AUD_VID_DID device id\t\t\t0x%x\n", dword & 0xffff);
264fa225cbcSrjs
265fa225cbcSrjs    dword = INREG(AUD_RID);
266fa225cbcSrjs    printf("AUD_RID major revision\t\t\t0x%lx\n", BITS(dword, 23, 20));
267fa225cbcSrjs    printf("AUD_RID minor revision\t\t\t0x%lx\n", BITS(dword, 19, 16));
268fa225cbcSrjs    printf("AUD_RID revision id\t\t\t0x%lx\n",    BITS(dword, 15, 8));
269fa225cbcSrjs    printf("AUD_RID stepping id\t\t\t0x%lx\n",    BITS(dword, 7, 0));
270fa225cbcSrjs
271fa225cbcSrjs    dword = INREG(SDVOB);
272fa225cbcSrjs    printf("SDVOB enable\t\t\t\t%u\n",      !!(dword & SDVO_ENABLE));
273fa225cbcSrjs    printf("SDVOB HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI));
274fa225cbcSrjs    printf("SDVOB SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO));
275fa225cbcSrjs    printf("SDVOB null packets\t\t\t%u\n",  !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
276fa225cbcSrjs    printf("SDVOB audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
277fa225cbcSrjs
278fa225cbcSrjs    dword = INREG(SDVOC);
279fa225cbcSrjs    printf("SDVOC enable\t\t\t\t%u\n",      !!(dword & SDVO_ENABLE));
280fa225cbcSrjs    printf("SDVOC HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI));
281fa225cbcSrjs    printf("SDVOC SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO));
282fa225cbcSrjs    printf("SDVOC null packets\t\t\t%u\n",  !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
283fa225cbcSrjs    printf("SDVOC audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
284fa225cbcSrjs
285fa225cbcSrjs    dword = INREG(PORT_HOTPLUG_EN);
286fa225cbcSrjs    printf("PORT_HOTPLUG_EN DisplayPort/HDMI port B\t%ld\n", BIT(dword, 29)),
287fa225cbcSrjs    printf("PORT_HOTPLUG_EN DisplayPort/HDMI port C\t%ld\n", BIT(dword, 28)),
288fa225cbcSrjs    printf("PORT_HOTPLUG_EN DisplayPort port D\t%ld\n",      BIT(dword, 27)),
289fa225cbcSrjs    printf("PORT_HOTPLUG_EN SDVOB\t\t\t%ld\n", BIT(dword, 26)),
290fa225cbcSrjs    printf("PORT_HOTPLUG_EN SDVOC\t\t\t%ld\n", BIT(dword, 25)),
291fa225cbcSrjs    printf("PORT_HOTPLUG_EN audio\t\t\t%ld\n", BIT(dword, 24)),
292fa225cbcSrjs    printf("PORT_HOTPLUG_EN TV\t\t\t%ld\n",    BIT(dword, 23)),
293fa225cbcSrjs    printf("PORT_HOTPLUG_EN CRT\t\t\t%ld\n",   BIT(dword, 9)),
294fa225cbcSrjs
295fa225cbcSrjs    dword = INREG(VIDEO_DIP_CTL);
296fa225cbcSrjs    printf("VIDEO_DIP_CTL enable graphics DIP\t%ld\n",     BIT(dword, 31)),
297fa225cbcSrjs    printf("VIDEO_DIP_CTL port select\t\t[0x%lx] %s\n",
298fa225cbcSrjs		    BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
299fa225cbcSrjs    printf("VIDEO_DIP_CTL DIP buffer trans active\t%lu\n", BIT(dword, 28));
300fa225cbcSrjs    printf("VIDEO_DIP_CTL AVI DIP enabled\t\t%lu\n",       BIT(dword, 21));
301fa225cbcSrjs    printf("VIDEO_DIP_CTL vendor DIP enabled\t%lu\n",      BIT(dword, 22));
302fa225cbcSrjs    printf("VIDEO_DIP_CTL SPD DIP enabled\t\t%lu\n",       BIT(dword, 24));
303fa225cbcSrjs    printf("VIDEO_DIP_CTL DIP buffer index\t\t[0x%lx] %s\n",
304fa225cbcSrjs		    BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]);
305fa225cbcSrjs    printf("VIDEO_DIP_CTL DIP trans freq\t\t[0x%lx] %s\n",
306fa225cbcSrjs		    BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]);
307fa225cbcSrjs    printf("VIDEO_DIP_CTL DIP buffer size\t\t%lu\n", BITS(dword, 11, 8));
308fa225cbcSrjs    printf("VIDEO_DIP_CTL DIP address\t\t%lu\n", BITS(dword, 3, 0));
309fa225cbcSrjs
310fa225cbcSrjs    dword = INREG(AUD_CONFIG);
311fa225cbcSrjs    printf("AUD_CONFIG pixel clock\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
312fa225cbcSrjs		    OPNAME(pixel_clock, BITS(dword, 19, 16)));
313fa225cbcSrjs    printf("AUD_CONFIG fabrication enabled\t\t%lu\n", BITS(dword, 2, 2));
314fa225cbcSrjs    printf("AUD_CONFIG professional use allowed\t%lu\n", BIT(dword, 1));
315fa225cbcSrjs    printf("AUD_CONFIG fuse enabled\t\t\t%lu\n", BIT(dword, 0));
316fa225cbcSrjs
317fa225cbcSrjs    dword = INREG(AUD_DEBUG);
318fa225cbcSrjs    printf("AUD_DEBUG function reset\t\t%lu\n", BIT(dword, 0));
319fa225cbcSrjs
320fa225cbcSrjs    dword = INREG(AUD_SUBN_CNT);
321fa225cbcSrjs    printf("AUD_SUBN_CNT starting node number\t0x%lx\n",  BITS(dword, 23, 16));
322fa225cbcSrjs    printf("AUD_SUBN_CNT total number of nodes\t0x%lx\n", BITS(dword, 7, 0));
323fa225cbcSrjs
324fa225cbcSrjs    dword = INREG(AUD_SUBN_CNT2);
325fa225cbcSrjs    printf("AUD_SUBN_CNT2 starting node number\t0x%lx\n",  BITS(dword, 24, 16));
326fa225cbcSrjs    printf("AUD_SUBN_CNT2 total number of nodes\t0x%lx\n", BITS(dword, 7, 0));
327fa225cbcSrjs
328fa225cbcSrjs    dword = INREG(AUD_FUNC_GRP);
329fa225cbcSrjs    printf("AUD_FUNC_GRP unsol capable\t\t%lu\n", BIT(dword, 8));
330fa225cbcSrjs    printf("AUD_FUNC_GRP node type\t\t\t0x%lx\n", BITS(dword, 7, 0));
331fa225cbcSrjs
332fa225cbcSrjs    dword = INREG(AUD_GRP_CAP);
333fa225cbcSrjs    printf("AUD_GRP_CAP beep 0\t\t\t%lu\n",       BIT(dword, 16));
334fa225cbcSrjs    printf("AUD_GRP_CAP input delay\t\t\t%lu\n",  BITS(dword, 11, 8));
335fa225cbcSrjs    printf("AUD_GRP_CAP output delay\t\t%lu\n",   BITS(dword, 3, 0));
336fa225cbcSrjs
337fa225cbcSrjs    dword = INREG(AUD_PWRST);
338fa225cbcSrjs    printf("AUD_PWRST device power state\t\t%s\n",
339fa225cbcSrjs				    power_state[BITS(dword, 5, 4)]);
340fa225cbcSrjs    printf("AUD_PWRST device power state setting\t%s\n",
341fa225cbcSrjs				    power_state[BITS(dword, 1, 0)]);
342fa225cbcSrjs
343fa225cbcSrjs    dword = INREG(AUD_SUPPWR);
344fa225cbcSrjs    printf("AUD_SUPPWR support D0\t\t\t%lu\n", BIT(dword, 0));
345fa225cbcSrjs    printf("AUD_SUPPWR support D1\t\t\t%lu\n", BIT(dword, 1));
346fa225cbcSrjs    printf("AUD_SUPPWR support D2\t\t\t%lu\n", BIT(dword, 2));
347fa225cbcSrjs    printf("AUD_SUPPWR support D3\t\t\t%lu\n", BIT(dword, 3));
348fa225cbcSrjs
349fa225cbcSrjs    dword = INREG(AUD_OUT_CWCAP);
350fa225cbcSrjs    printf("AUD_OUT_CWCAP widget type\t\t0x%lx\n",  BITS(dword, 23, 20));
351fa225cbcSrjs    printf("AUD_OUT_CWCAP sample delay\t\t0x%lx\n", BITS(dword, 19, 16));
352fa225cbcSrjs    printf("AUD_OUT_CWCAP channel count\t\t%lu\n",
353fa225cbcSrjs		    BITS(dword, 15, 13) * 2 + BIT(dword, 0) + 1);
354fa225cbcSrjs    printf("AUD_OUT_CWCAP L-R swap\t\t\t%lu\n",       BIT(dword, 11));
355fa225cbcSrjs    printf("AUD_OUT_CWCAP power control\t\t%lu\n",    BIT(dword, 10));
356fa225cbcSrjs    printf("AUD_OUT_CWCAP digital\t\t\t%lu\n",        BIT(dword, 9));
357fa225cbcSrjs    printf("AUD_OUT_CWCAP conn list\t\t\t%lu\n",      BIT(dword, 8));
358fa225cbcSrjs    printf("AUD_OUT_CWCAP unsol\t\t\t%lu\n",          BIT(dword, 7));
359fa225cbcSrjs    printf("AUD_OUT_CWCAP mute\t\t\t%lu\n",           BIT(dword, 5));
360fa225cbcSrjs    printf("AUD_OUT_CWCAP format override\t\t%lu\n",  BIT(dword, 4));
361fa225cbcSrjs    printf("AUD_OUT_CWCAP amp param override\t%lu\n", BIT(dword, 3));
362fa225cbcSrjs    printf("AUD_OUT_CWCAP out amp present\t\t%lu\n",  BIT(dword, 2));
363fa225cbcSrjs    printf("AUD_OUT_CWCAP in amp present\t\t%lu\n",   BIT(dword, 1));
364fa225cbcSrjs
365fa225cbcSrjs    dword = INREG(AUD_OUT_DIG_CNVT);
366fa225cbcSrjs    printf("AUD_OUT_DIG_CNVT SPDIF category\t\t0x%lx\n", BITS(dword, 14, 8));
367fa225cbcSrjs    printf("AUD_OUT_DIG_CNVT SPDIF level\t\t%lu\n",      BIT(dword, 7));
368fa225cbcSrjs    printf("AUD_OUT_DIG_CNVT professional\t\t%lu\n",     BIT(dword, 6));
369fa225cbcSrjs    printf("AUD_OUT_DIG_CNVT non PCM\t\t%lu\n",          BIT(dword, 5));
370fa225cbcSrjs    printf("AUD_OUT_DIG_CNVT copyright asserted\t%lu\n", BIT(dword, 4));
371fa225cbcSrjs    printf("AUD_OUT_DIG_CNVT filter preemphasis\t%lu\n", BIT(dword, 3));
372fa225cbcSrjs    printf("AUD_OUT_DIG_CNVT validity config\t%lu\n",    BIT(dword, 2));
373fa225cbcSrjs    printf("AUD_OUT_DIG_CNVT validity flag\t\t%lu\n",    BIT(dword, 1));
374fa225cbcSrjs    printf("AUD_OUT_DIG_CNVT digital enable\t\t%lu\n",   BIT(dword, 0));
375fa225cbcSrjs
376fa225cbcSrjs    dword = INREG(AUD_OUT_CH_STR);
377fa225cbcSrjs    printf("AUD_OUT_CH_STR stream id\t\t0x%lx\n",        BITS(dword, 7, 4));
378fa225cbcSrjs    printf("AUD_OUT_CH_STR lowest channel\t\t0x%lx\n",   BITS(dword, 3, 0));
379fa225cbcSrjs
380fa225cbcSrjs    dword = INREG(AUD_OUT_STR_DESC);
381fa225cbcSrjs    printf("AUD_OUT_STR_DESC stream channels\t0x%lx\n",  BITS(dword, 3, 0));
382fa225cbcSrjs
383fa225cbcSrjs    dword = INREG(AUD_PINW_CAP);
384fa225cbcSrjs    printf("AUD_PINW_CAP widget type\t\t0x%lx\n",        BITS(dword, 23, 20));
385fa225cbcSrjs    printf("AUD_PINW_CAP sample delay\t\t0x%lx\n",       BITS(dword, 19, 16));
386fa225cbcSrjs    printf("AUD_PINW_CAP channel count\t\t0x%lx\n",
387fa225cbcSrjs		    BITS(dword, 15, 13) * 2 + BIT(dword, 0));
388fa225cbcSrjs    printf("AUD_PINW_CAP HDCP\t\t\t%lu\n",               BIT(dword, 12));
389fa225cbcSrjs    printf("AUD_PINW_CAP L-R swap\t\t\t%lu\n",           BIT(dword, 11));
390fa225cbcSrjs    printf("AUD_PINW_CAP power control\t\t%lu\n",        BIT(dword, 10));
391fa225cbcSrjs    printf("AUD_PINW_CAP digital\t\t\t%lu\n",            BIT(dword, 9));
392fa225cbcSrjs    printf("AUD_PINW_CAP conn list\t\t\t%lu\n",          BIT(dword, 8));
393fa225cbcSrjs    printf("AUD_PINW_CAP unsol\t\t\t%lu\n",              BIT(dword, 7));
394fa225cbcSrjs    printf("AUD_PINW_CAP mute\t\t\t%lu\n",               BIT(dword, 5));
395fa225cbcSrjs    printf("AUD_PINW_CAP format override\t\t%lu\n",      BIT(dword, 4));
396fa225cbcSrjs    printf("AUD_PINW_CAP amp param override\t\t%lu\n",   BIT(dword, 3));
397fa225cbcSrjs    printf("AUD_PINW_CAP out amp present\t\t%lu\n",      BIT(dword, 2));
398fa225cbcSrjs    printf("AUD_PINW_CAP in amp present\t\t%lu\n",       BIT(dword, 1));
399fa225cbcSrjs
400fa225cbcSrjs
401fa225cbcSrjs    dword = INREG(AUD_PIN_CAP);
402fa225cbcSrjs    printf("AUD_PIN_CAP EAPD\t\t\t%lu\n",          BIT(dword, 16));
403fa225cbcSrjs    printf("AUD_PIN_CAP HDMI\t\t\t%lu\n",          BIT(dword, 7));
404fa225cbcSrjs    printf("AUD_PIN_CAP output\t\t\t%lu\n",        BIT(dword, 4));
405fa225cbcSrjs    printf("AUD_PIN_CAP presence detect\t\t%lu\n", BIT(dword, 2));
406fa225cbcSrjs
407fa225cbcSrjs    dword = INREG(AUD_PINW_CNTR);
408fa225cbcSrjs    printf("AUD_PINW_CNTR mute status\t\t%lu\n",     BIT(dword, 8));
409fa225cbcSrjs    printf("AUD_PINW_CNTR out enable\t\t%lu\n",      BIT(dword, 6));
410fa225cbcSrjs    printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", BIT(dword, 8));
411fa225cbcSrjs    printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", BIT(dword, 8));
412fa225cbcSrjs    printf("AUD_PINW_CNTR stream type\t\t[0x%lx] %s\n",
413fa225cbcSrjs		    BITS(dword, 2, 0),
414fa225cbcSrjs		    OPNAME(stream_type, BITS(dword, 2, 0)));
415fa225cbcSrjs
416fa225cbcSrjs    dword = INREG(AUD_PINW_UNSOLRESP);
417fa225cbcSrjs    printf("AUD_PINW_UNSOLRESP enable unsol resp\t%lu\n", BIT(dword, 31));
418fa225cbcSrjs
419fa225cbcSrjs    dword = INREG(AUD_CNTL_ST);
420fa225cbcSrjs    printf("AUD_CNTL_ST DIP audio enabled\t\t%lu\n", BIT(dword, 21));
421fa225cbcSrjs    printf("AUD_CNTL_ST DIP ACP enabled\t\t%lu\n",   BIT(dword, 22));
422fa225cbcSrjs    printf("AUD_CNTL_ST DIP ISRCx enabled\t\t%lu\n", BIT(dword, 23));
423fa225cbcSrjs    printf("AUD_CNTL_ST DIP port select\t\t[0x%lx] %s\n",
424fa225cbcSrjs		    BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
425fa225cbcSrjs    printf("AUD_CNTL_ST DIP buffer index\t\t[0x%lx] %s\n",
426fa225cbcSrjs		    BITS(dword, 20, 18), OPNAME(dip_index, BITS(dword, 20, 18)));
427fa225cbcSrjs    printf("AUD_CNTL_ST DIP trans freq\t\t[0x%lx] %s\n",
428fa225cbcSrjs		    BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
429fa225cbcSrjs    printf("AUD_CNTL_ST DIP address\t\t\t%lu\n", BITS(dword, 3, 0));
430fa225cbcSrjs    printf("AUD_CNTL_ST CP ready\t\t\t%lu\n",    BIT(dword, 15));
431fa225cbcSrjs    printf("AUD_CNTL_ST ELD valid\t\t\t%lu\n",   BIT(dword, 14));
432fa225cbcSrjs    printf("AUD_CNTL_ST ELD ack\t\t\t%lu\n",     BIT(dword, 4));
433fa225cbcSrjs    printf("AUD_CNTL_ST ELD bufsize\t\t\t%lu\n", BITS(dword, 13, 9));
434fa225cbcSrjs    printf("AUD_CNTL_ST ELD address\t\t\t%lu\n", BITS(dword, 8, 5));
435fa225cbcSrjs
436fa225cbcSrjs    dword = INREG(AUD_HDMIW_STATUS);
437fa225cbcSrjs    printf("AUD_HDMIW_STATUS CDCLK/DOTCLK underrun\t%lu\n", BIT(dword, 31));
438fa225cbcSrjs    printf("AUD_HDMIW_STATUS CDCLK/DOTCLK overrun\t%lu\n",  BIT(dword, 30));
439fa225cbcSrjs    printf("AUD_HDMIW_STATUS BCLK/CDCLK underrun\t%lu\n",   BIT(dword, 29));
440fa225cbcSrjs    printf("AUD_HDMIW_STATUS BCLK/CDCLK overrun\t%lu\n",    BIT(dword, 28));
441fa225cbcSrjs
442fa225cbcSrjs    dword = INREG(AUD_CONV_CHCNT);
443fa225cbcSrjs    printf("AUD_CONV_CHCNT HDMI HBR enabled\t\t%lu\n", BITS(dword, 15, 14));
444fa225cbcSrjs    printf("AUD_CONV_CHCNT HDMI channel count\t%lu\n", BITS(dword, 11, 8) + 1);
445fa225cbcSrjs
446fa225cbcSrjs    printf("AUD_CONV_CHCNT HDMI channel mapping:\n");
447fa225cbcSrjs    for (i = 0; i < 8; i++) {
448fa225cbcSrjs	    OUTREG(AUD_CONV_CHCNT, i);
449fa225cbcSrjs	    dword = INREG(AUD_CONV_CHCNT);
450fa225cbcSrjs	    printf("\t\t\t\t\t[0x%x] %u => %lu \n", dword, i, BITS(dword, 7, 4));
451fa225cbcSrjs    }
452fa225cbcSrjs
453fa225cbcSrjs    return 0;
454fa225cbcSrjs}
455