i915_structs.h revision fa225cbc 
1/*
2 * Copyright © 2006 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 *    Xiang Haihao <haihao.xiang@intel.com>
25 *
26 */
27
28#ifndef _I915_STRUCTS_H
29#define _I915_STRUCTS_H
30
31#include <stdint.h>
32
33/* MI_INSTRUCTION */
34#define CMD_MI          0x00
35
36#define OPC_MI_FLUSH                            (0x04)
37
38struct i915_mi_flush
39{
40    struct {
41        unsigned map_cache_invalidate : 1;
42        unsigned pad0 : 1;
43        unsigned render_cache_flush_inhibit : 1;
44        unsigned scene_count : 1;
45        unsigned end_scene : 1;
46        unsigned pad1 : 18;
47        unsigned opcode : 6;
48        unsigned type : 3;
49    } dw0;
50};
51
52/* BLT */
53#define CMD_2D          0x02
54#define OPC_COLOR_BLT                           (0x40)
55
56struct i915_color_blt
57{
58    struct {
59        unsigned length : 5;
60        unsigned pad0 : 15;
61        unsigned bpp_mask : 2;
62        unsigned opcode : 7;
63        unsigned type : 3;
64    } dw0;
65
66    struct {
67        unsigned pitch : 16;
68        unsigned rop : 8;
69        unsigned color_depth : 2;
70        unsigned pad0 : 6;
71    } dw1;
72
73    struct {
74        unsigned width : 16;
75        unsigned height : 16;
76    } dw2;
77
78    struct {
79        unsigned address;
80    } dw3;
81
82    struct {
83        unsigned pattern;
84    } dw4;
85};
86
87/* 3D_INSTRUCTION */
88#define CMD_3D          0x03
89
90#define OPC_3DMPEG_MACROBLOCK_IPICTURE          (0x01 + (0x1e << 5))
91#define OPC_3DMPEG_SET_ORIGIN                   (0x10 + (0x1e << 5))
92#define OPC_3DMPEG_MACROBLOCK                   (0x11 + (0x1e << 5))
93#define OPC_3DMPEG_SLICE                        (0x12 + (0x1e << 5))
94#define OPC_3DMPEG_QM_PALETTE_LOAD              (0x13 + (0x1e << 5))
95
96#define OPC_3DSTATE_SCISSOR_ENABLE              (0x10 + (0x1c << 5))
97
98#define OPC_3DSTATE_MAP_STATE                   (0x00 + (0x1d << 8))
99#define OPC_3DSTATE_SAMPLER_STATE               (0x01 + (0x1d << 8))
100#define OPC_3DSTATE_LOAD_STATE_IMMEDIATE_1      (0x04 + (0x1d << 8))
101#define OPC_3DSTATE_PIXEL_SHADER_PROGRAM        (0x05 + (0x1d << 8))
102#define OPC_3DSTATE_PIXEL_SHADER_CONSTANTS      (0x06 + (0x1d << 8))
103#define OPC_3DSTATE_LOAD_INDIRECT               (0x07 + (0x1d << 8))
104
105#define OPC_3DSTATE_MODES_5                     (0x0c)
106#define OPC_3DSTATE_COORD_SET_BINDINGS          (0x16)
107#define OPC_3DPRIMITIVE                         (0x1f)
108
109#define OPC_3DSTATE_DRAWING_RECTANGLE           (0x80 + (0x1d << 8))
110#define OPC_3DSTATE_SCISSOR_RECTANGLE           (0x81 + (0x1d << 8))
111#define OPC_3DSTATE_DEST_BUFFER_VARIABLES       (0x85 + (0x1d << 8))
112#define OPC_3DSTATE_DEST_BUFFER_VARIABLES_MPEG  (0x87 + (0x1d << 8))
113#define OPC_3DSTATE_BUFFER_INFO                 (0x8e + (0x1d << 8))
114
115/*
116 * 3DMPEG instructions
117 */
118struct i915_3dmpeg_macroblock_header
119{
120    struct {
121        unsigned length : 19;
122        unsigned opcode : 10;
123        unsigned type : 3;
124    } dw0;
125
126    struct {
127        unsigned mb_intra : 1;
128        unsigned forward : 1;
129        unsigned backward : 1;
130        unsigned h263_4mv : 1;
131        unsigned pad0 : 1;
132        unsigned dct_type : 1;
133        unsigned pad1 : 2;
134        unsigned motion_type : 2;
135        unsigned pad2 : 2;
136        unsigned vertical_field_select : 4;
137        unsigned coded_block_pattern : 6;
138        unsigned pad3 : 2;
139        unsigned skipped_macroblocks : 7;
140        unsigned pad4 : 1;
141    } dw1;
142};
143
144struct i915_3dmpeg_macroblock_0mv
145{
146    struct i915_3dmpeg_macroblock_header header;
147};
148
149struct i915_3dmpeg_macroblock_1fbmv
150{
151    struct i915_3dmpeg_macroblock_header header;
152    unsigned dw2;
153    unsigned dw3;
154};
155struct i915_3dmpeg_macroblock_2fbmv
156{
157    struct i915_3dmpeg_macroblock_header header;
158    unsigned dw2;
159    unsigned dw3;
160    unsigned dw4;
161    unsigned dw5;
162};
163
164struct i915_3dmpeg_macroblock_5fmv
165{
166    struct i915_3dmpeg_macroblock_header header;
167    unsigned dw2;
168    unsigned dw3;
169    unsigned dw4;
170    unsigned dw5;
171    unsigned dw6;
172};
173
174struct i915_3dmpeg_macroblock_ipicture
175{
176    struct {
177        unsigned pad0 : 5;
178        unsigned dct_type : 1;
179        unsigned pad1 : 13;
180        unsigned opcode : 10;
181        unsigned type : 3;
182    } dw0;
183};
184
185struct i915_3dmpeg_set_origin
186{
187    struct {
188        unsigned length : 19;
189        unsigned opcode : 10;
190        unsigned type : 3;
191    } dw0;
192
193    struct {
194        unsigned v_origin : 7;
195        unsigned pad0 : 1;
196        unsigned h_origin : 7;
197        unsigned pad1 : 17;
198    } dw1;
199};
200
201struct i915_3dmpeg_slice
202{
203    struct {
204        unsigned length : 19;
205        unsigned opcode : 10;
206        unsigned type : 3;
207    } dw0;
208
209    struct {
210        unsigned fst_mb_bit_off : 3;
211        unsigned pad0 : 5;
212        unsigned mb_count : 7;
213        unsigned pad1 : 1;
214        unsigned v_position : 7;
215        unsigned pad2 : 1;
216        unsigned h_position : 7;
217        unsigned pad3 : 1;
218    } dw1;
219
220    struct {
221        unsigned length_minus_one : 17;
222        unsigned pad0 : 7;
223        unsigned qt_scale_code : 5;
224        unsigned pad1 : 3;
225    } dw2;
226};
227
228struct i915_3dmpeg_qm_palette_load
229{
230    struct {
231        unsigned length : 4;
232        unsigned pad0 : 15;
233        unsigned opcode : 10;
234        unsigned type : 3;
235    } dw0;
236
237    unsigned quantmatrix[16];
238};
239
240
241/*
242 * 3DSTATE instruction
243 */
244#define BUFFERID_COLOR_BACK     3
245#define BUFFERID_COLOR_AUX      4
246#define BUFFERID_MC_INTRA_CORR  5
247#define BUFFERID_DEPTH          7
248
249#define TILEWALK_XMAJOR         0
250#define TILEWALK_YMAJOR         1
251
252struct i915_3dstate_buffer_info
253{
254    struct {
255        unsigned length : 16;
256        unsigned opcode : 13;
257        unsigned type : 3;
258    } dw0;
259
260    struct {
261        unsigned pad0 : 2;
262        unsigned pitch : 12;
263        unsigned pad1 : 7;
264        unsigned walk : 1;
265        unsigned tiled_surface : 1;
266        unsigned fence_regs : 1;
267        unsigned buffer_id : 4;
268        unsigned aux_id : 1;
269        unsigned pad2 : 3;
270    } dw1;
271
272    struct {
273        unsigned pad0 : 2;
274        unsigned base_address : 27;
275        unsigned pad1 : 3;
276    } dw2;
277};
278
279#define COLORBUFFER_8BIT         0x00
280#define COLORBUFFER_X1R5G5B5     0x01
281#define COLORBUFFER_R5G6B5       0x02
282#define COLORBUFFER_A8R8G8B8     0x03
283#define COLORBUFFER_YCRCB_SWAP   0x04
284#define COLORBUFFER_YCRCB_NORMAL 0x05
285#define COLORBUFFER_YCRCB_SWAPUV 0x06
286#define COLORBUFFER_YCRCB_SWAPUVY   0x07
287#define COLORBUFFER_A4R4G4B4     0x08
288#define COLORBUFFER_A1R5G5B5     0x09
289#define COLORBUFFER_A2R10G10B10  0x0a
290
291
292struct i915_3dstate_dest_buffer_variables
293{
294    struct {
295        unsigned length : 16;
296        unsigned opcode : 13;
297        unsigned type : 3;
298    } dw0;
299
300    struct {
301        unsigned v_ls_offset : 1;
302        unsigned v_ls : 1;
303        unsigned depth_fmt : 2;
304        unsigned pad0 : 4;
305        unsigned color_fmt : 4;
306        unsigned yuv422_select : 3;
307        unsigned pad1 : 1;
308        unsigned dest_v_bias : 4;
309        unsigned dest_h_bias : 4;
310        unsigned dither_enhancement : 1;
311        unsigned linear_gamma : 1;
312        unsigned dither_pattern : 2;
313        unsigned lod_preclamp : 1;
314        unsigned edt_zone : 1;          /* early depth test in zone rendering */
315        unsigned texture_default_color : 1;
316        unsigned edt_classic : 1;       /* early depth test in classic mode */
317    } dw1;
318};
319
320#define MPEG_DECODE_MC          0
321#define MPEG_DECODE_VLD_IDCT_MC 1
322
323#define MPEG_I_PICTURE          1
324#define MPEG_P_PICTURE          2
325#define MPEG_B_PICTURE          3
326
327#define MC_SUB_1H               0
328#define MC_SUB_2H               1
329#define MC_SUB_4H               2
330
331#define MC_SUB_1V               0
332#define MC_SUB_2V               1
333
334struct i915_3dstate_dest_buffer_variables_mpeg
335{
336    struct {
337        unsigned length : 16;
338        unsigned opcode : 13;
339        unsigned type : 3;
340    } dw0;
341
342    struct {
343        unsigned picture_width : 7;
344        unsigned pad0 : 1;
345        unsigned v_subsample_factor : 2;
346        unsigned h_subsample_factor : 2;
347        unsigned tff : 1;
348        unsigned mismatch : 1;
349        unsigned pad1 : 1;
350        unsigned intra8 : 1;
351        unsigned abort_on_error : 8;
352        unsigned pad2 : 4;
353        unsigned bidir_avrg_control : 1;
354        unsigned rcontrol : 1;
355        unsigned decode_mode : 2;
356    } dw1;
357
358    struct {
359        unsigned pad0 : 1;
360        unsigned picture_coding_type : 2;
361        unsigned pad1 : 2;
362        unsigned scan_order : 1;
363        unsigned pad2 : 2;
364        unsigned q_scale_type : 1;
365        unsigned concealment : 1;
366        unsigned fpf_dct : 1;
367        unsigned pad3 : 2;
368        unsigned intra_dc : 2;
369        unsigned intra_vlc : 1;
370        unsigned f_code00 : 4;
371        unsigned f_code01 : 4;
372        unsigned f_code10 : 4;
373        unsigned f_code11 : 4;
374    } dw2;
375};
376
377struct i915_mc_static_indirect_state_buffer {
378    struct i915_3dstate_buffer_info dest_y;
379    struct i915_3dstate_buffer_info dest_u;
380    struct i915_3dstate_buffer_info dest_v;
381    struct i915_3dstate_dest_buffer_variables dest_buf;
382    struct i915_3dstate_dest_buffer_variables_mpeg dest_buf_mpeg;
383    struct i915_3dstate_buffer_info corr;
384};
385
386#define MAP_MAP0        0x0001
387#define MAP_MAP1        0x0002
388#define MAP_MAP2        0x0004
389#define MAP_MAP3        0x0008
390#define MAP_MAP4        0x0010
391#define MAP_MAP5        0x0020
392#define MAP_MAP6        0x0040
393#define MAP_MAP7        0x0080
394#define MAP_MAP8        0x0100
395#define MAP_MAP9        0x0200
396#define MAP_MAP10       0x0400
397#define MAP_MAP11       0x0800
398#define MAP_MAP12       0x1000
399#define MAP_MAP13       0x2000
400#define MAP_MAP14       0x4000
401#define MAP_MAP15       0x8000
402
403struct texture_map
404{
405    struct {
406        unsigned v_ls_offset : 1;
407        unsigned v_ls : 1;
408        unsigned base_address : 27;
409        unsigned pad0 : 2;
410        unsigned untrusted : 1;
411    } tm0;
412
413    struct {
414        unsigned tile_walk : 1;
415        unsigned tiled_surface : 1;
416        unsigned utilize_fence_regs : 1;
417        unsigned texel_fmt : 4;
418        unsigned surface_fmt : 3;
419        unsigned width : 11;
420        unsigned height : 11;
421    } tm1;
422
423    struct {
424        unsigned depth : 8;
425        unsigned mipmap_layout : 1;
426        unsigned max_lod : 6;
427        unsigned cube_face : 6;
428        unsigned pitch : 11;
429    } tm2;
430};
431
432struct i915_3dstate_map_state
433{
434    struct {
435        unsigned length : 6;
436        unsigned pad0 : 9;
437        unsigned retain : 1;
438        unsigned opcode : 13;
439        unsigned type : 3;
440    } dw0;
441
442    struct {
443        unsigned map_mask : 16;
444        unsigned pad0 : 16;
445    } dw1;
446};
447
448struct i915_mc_map_state {
449    struct i915_3dstate_map_state y_map;
450    struct texture_map y_forward;
451    struct texture_map y_backward;
452    struct i915_3dstate_map_state u_map;
453    struct texture_map u_forward;
454    struct texture_map u_backward;
455    struct i915_3dstate_map_state v_map;
456    struct texture_map v_forward;
457    struct texture_map v_backward;
458};
459
460#define SAMPLER_SAMPLER0        0x0001
461#define SAMPLER_SAMPLER1        0x0002
462#define SAMPLER_SAMPLER2        0x0004
463#define SAMPLER_SAMPLER3        0x0008
464#define SAMPLER_SAMPLER4        0x0010
465#define SAMPLER_SAMPLER5        0x0020
466#define SAMPLER_SAMPLER6        0x0040
467#define SAMPLER_SAMPLER7        0x0080
468#define SAMPLER_SAMPLER8        0x0100
469#define SAMPLER_SAMPLER9        0x0200
470#define SAMPLER_SAMPLER10       0x0400
471#define SAMPLER_SAMPLER11       0x0800
472#define SAMPLER_SAMPLER12       0x1000
473#define SAMPLER_SAMPLER13       0x2000
474#define SAMPLER_SAMPLER14       0x4000
475#define SAMPLER_SAMPLER15       0x8000
476
477#define MIPFILTER_NONE          0
478#define MIPFILTER_NEAREST       1
479#define MIPFILTER_LINEAR        3
480
481#define MAPFILTER_NEAREST       0
482#define MAPFILTER_LINEAR        1
483#define MAPFILTER_ANISOTROPIC   2
484#define MAPFILTER_4X4_1         3
485#define MAPFILTER_4X4_2         4
486#define MAPFILTER_4X4_FLAT      5
487#define MAPFILTER_MONO          6
488
489#define ANISORATIO_2            0
490#define ANISORATIO_4            1
491
492#define PREFILTEROP_ALWAYS      0
493#define PREFILTEROP_NEVER       1
494#define PREFILTEROP_LESS        2
495#define PREFILTEROP_EQUAL       3
496#define PREFILTEROP_LEQUAL      4
497#define PREFILTEROP_GREATER     5
498#define PREFILTEROP_NOTEQUAL    6
499#define PREFILTEROP_GEQUAL      7
500
501#define TEXCOORDMODE_WRAP       0
502#define TEXCOORDMODE_MIRROR     1
503#define TEXCOORDMODE_CLAMP      2
504#define TEXCOORDMODE_CUBE       3
505#define TEXCOORDMODE_CLAMP_BORDER       4
506#define TEXCOORDMODE_MIRROR_ONCE        5
507
508struct texture_sampler
509{
510    struct {
511        unsigned shadow_function : 3;
512        unsigned max_anisotropy : 1;
513        unsigned shadow_enable : 1;
514        unsigned lod_bias : 9;
515        unsigned min_filter : 3;
516        unsigned mag_filter : 3;
517        unsigned mip_filter : 2;
518        unsigned base_level : 5;
519        unsigned chromakey_index : 2;
520        unsigned color_conversion : 1;
521        unsigned planar2packet : 1;
522        unsigned reverse_gamma : 1;
523    } ts0;
524
525    struct {
526        unsigned east_deinterlacer : 1;
527        unsigned map_index : 4;
528        unsigned normalized_coor : 1;
529        unsigned tcz_control : 3;
530        unsigned tcy_control : 3;
531        unsigned tcx_control : 3;
532        unsigned chromakey_enable : 1;
533        unsigned keyed_texture_filter : 1;
534        unsigned kill_pixel : 1;
535        unsigned pad0 : 6;
536        unsigned min_lod : 8;
537    } ts1;
538
539    struct {
540        unsigned default_color;
541    } ts2;
542};
543
544struct i915_3dstate_sampler_state
545{
546    struct {
547        unsigned length : 6;
548        unsigned pad0 : 10;
549        unsigned opcode : 13;
550        unsigned type : 3;
551    } dw0;
552
553    struct {
554        unsigned sampler_masker : 16;
555        unsigned pad0 : 16;
556    } dw1;
557    /* we always use two samplers for mc */
558    struct texture_sampler sampler0;
559    struct texture_sampler sampler1;
560};
561
562struct arithmetic_inst
563{
564    struct {
565        unsigned pad0 : 2;
566        unsigned src0_reg : 5;
567        unsigned src0_reg_t : 3;
568        unsigned dest_channel_mask : 4;
569        unsigned dest_reg : 4;
570        unsigned pad1 : 1;
571        unsigned dest_reg_t: 3;
572        unsigned dest_saturate : 1;
573        unsigned pad2 : 1;
574        unsigned opcode : 5;
575        unsigned pad3 : 3;
576    } dw0;
577
578    struct {
579        unsigned src1_y_select : 3;
580        unsigned src1_y_negate : 1;
581        unsigned src1_x_select : 3;
582        unsigned src1_x_negate : 1;
583        unsigned src1_reg : 5;
584        unsigned src1_reg_t : 3;
585        unsigned src0_w_select : 3;
586        unsigned src0_w_negate : 1;
587        unsigned src0_z_select : 3;
588        unsigned src0_z_negate : 1;
589        unsigned src0_y_select : 3;
590        unsigned src0_y_negate : 1;
591        unsigned src0_x_select : 3;
592        unsigned src0_x_negate : 1;
593    } dw1;
594
595    struct {
596        unsigned src2_w_select : 3;
597        unsigned src2_w_negate : 1;
598        unsigned src2_z_select : 3;
599        unsigned src2_z_negate : 1;
600        unsigned src2_y_select : 3;
601        unsigned src2_y_negate : 1;
602        unsigned src2_x_select : 3;
603        unsigned src2_x_negate : 1;
604        unsigned src2_reg : 5;
605        unsigned src2_reg_t : 3;
606        unsigned src1_w_select : 3;
607        unsigned src1_w_negate : 1;
608        unsigned src1_z_select : 3;
609        unsigned src1_z_negate : 1;
610    } dw2;
611};
612
613struct texture_inst
614{
615    struct {
616        unsigned sampler_reg : 4;
617        unsigned pad0 : 10;
618        unsigned dest_reg : 4;
619        unsigned pad1 : 1;
620        unsigned dest_reg_t : 3;
621        unsigned pad2 : 2;
622        unsigned opcode : 5;
623        unsigned pad3 : 3;
624    } dw0;
625
626    struct {
627        unsigned pad0 : 16;
628        unsigned address_reg : 5;
629        unsigned pad1 : 3;
630        unsigned address_reg_t : 3;
631        unsigned pad2 : 5;
632    } dw1;
633
634    struct {
635        unsigned pad0;
636    } dw2;
637};
638
639struct declaration_inst
640{
641    struct {
642        unsigned pad0 : 10;
643        unsigned decl_channel_mask : 4;
644        unsigned decl_reg : 4;
645        unsigned pad1 : 1;
646        unsigned decl_reg_t : 2;
647        unsigned pad2 : 1;
648        unsigned sampler_type : 2;
649        unsigned opcode : 5;
650        unsigned pad3 : 3;
651    } dw0;
652
653    struct {
654        unsigned pad0;
655    } dw1;
656
657    struct {
658        unsigned pad0;
659    } dw2;
660};
661
662union shader_inst
663{
664    struct arithmetic_inst a;
665    struct texture_inst t;
666    struct declaration_inst d;
667};
668
669struct i915_3dstate_pixel_shader_header {
670    unsigned length : 9;
671    unsigned pad0 : 6;
672    unsigned retain : 1;
673    unsigned opcode : 13;
674    unsigned type : 3;
675};
676
677struct i915_3dstate_pixel_shader_program
678{
679    struct i915_3dstate_pixel_shader_header shader0;
680    /* mov oC, c0.0000 */
681    uint32_t inst0[3];
682
683    struct i915_3dstate_pixel_shader_header shader1;
684    /* dcl t0.xy */
685    /* dcl t1.xy */
686    /* dcl_2D s0 */
687    /* texld r0, t0, s0 */
688    /* mov oC, r0 */
689    uint32_t inst1[3*5];
690
691    struct i915_3dstate_pixel_shader_header shader2;
692    /* dcl t2.xy */
693    /* dcl t3.xy */
694    /* dcl_2D s1 */
695    /* texld r0, t2, s1 */
696    /* mov oC, r0 */
697    uint32_t inst2[3*5];
698
699    struct i915_3dstate_pixel_shader_header shader3;
700    /* dcl t0.xy */
701    /* dcl t1.xy */
702    /* dcl t2.xy */
703    /* dcl t3.xy */
704    /* dcl_2D s0 */
705    /* dcl_2D s1 */
706    /* texld r0, t0, s0 */
707    /* texld r0, t2, s1 */
708    /* add r0, r0, r1*/
709    /* mov oC, r0 */
710    uint32_t inst3[3*10];
711};
712
713#define REG_CR0         0x00000001
714#define REG_CR1         0x00000002
715#define REG_CR2         0x00000004
716#define REG_CR3         0x00000008
717#define REG_CR4         0x00000010
718#define REG_CR5         0x00000020
719#define REG_CR6         0x00000040
720#define REG_CR7         0x00000080
721#define REG_CR8         0x00000100
722#define REG_CR9         0x00000200
723#define REG_CR10        0x00000400
724#define REG_CR11        0x00000800
725#define REG_CR12        0x00001000
726#define REG_CR13        0x00002000
727#define REG_CR14        0x00004000
728#define REG_CR15        0x00008000
729#define REG_CR16        0x00010000
730#define REG_CR17        0x00020000
731#define REG_CR18        0x00040000
732#define REG_CR19        0x00080000
733#define REG_CR20        0x00100000
734#define REG_CR21        0x00200000
735#define REG_CR22        0x00400000
736#define REG_CR23        0x00800000
737#define REG_CR24        0x01000000
738#define REG_CR25        0x02000000
739#define REG_CR26        0x04000000
740#define REG_CR27        0x08000000
741#define REG_CR28        0x10000000
742#define REG_CR29        0x20000000
743#define REG_CR30        0x40000000
744#define REG_CR31        0x80000000
745
746struct shader_constant
747{
748    float x;
749    float y;
750    float z;
751    float w;
752};
753
754struct i915_3dstate_pixel_shader_constants
755{
756    struct {
757        unsigned length : 8;
758        unsigned pad0 : 8;
759        unsigned opcode : 13;
760        unsigned type : 3;
761    } dw0;
762
763    struct {
764        unsigned reg_mask;
765    } dw1;
766    /* we only need one constant */
767    struct shader_constant value;
768};
769
770#define BLOCK_SIS       0x01
771#define BLOCK_DIS       0x02
772#define BLOCK_SSB       0x04
773#define BLOCK_MSB       0x08
774#define BLOCK_PSP       0x10
775#define BLOCK_PSC       0x20
776
777typedef struct _state_ddword
778{
779    struct {
780        unsigned valid : 1;
781        unsigned force : 1;
782        unsigned buffer_address : 30;
783    } dw0;
784
785    struct {
786        unsigned length : 9;
787        unsigned pad0 : 23;
788    } dw1;
789} sis_state, ssb_state, msb_state, psp_state, psc_state;
790
791typedef struct _state_dword
792{
793    struct {
794        unsigned valid : 1;
795        unsigned reset : 1;
796        unsigned buffer_address : 30;
797    } dw0;
798} dis_state;
799
800struct i915_3dstate_load_indirect
801{
802    struct {
803        unsigned length : 8;
804        unsigned block_mask : 6;
805        unsigned mem_select : 1;
806        unsigned pad0 : 1;
807        unsigned opcode : 13;
808        unsigned type : 3;
809    } dw0;
810};
811
812#define TEXCOORDFMT_2FP       0x00
813#define TEXCOORDFMT_3FP       0x01
814#define TEXCOORDFMT_4FP       0x02
815#define TEXCOORDFMT_1FP       0x03
816#define TEXCOORDFMT_2FP_16    0x04
817#define TEXCOORDFMT_4FP_16    0x05
818#define TEXCOORDFMT_NOT_PRESENT  0x0f
819struct s2_dword
820{
821    unsigned set0_texcoord_fmt : 4;
822    unsigned set1_texcoord_fmt : 4;
823    unsigned set2_texcoord_fmt : 4;
824    unsigned set3_texcoord_fmt : 4;
825    unsigned set4_texcoord_fmt : 4;
826    unsigned set5_texcoord_fmt : 4;
827    unsigned set6_texcoord_fmt : 4;
828    unsigned set7_texcoord_fmt : 4;
829};
830
831struct s3_dword
832{
833    unsigned set0_pcd : 1;
834    unsigned set0_ws_tcz : 1;
835    unsigned set0_ws_tcy : 1;
836    unsigned set0_ws_tcx : 1;
837    unsigned set1_pcd : 1;
838    unsigned set1_ws_tcz : 1;
839    unsigned set1_ws_tcy : 1;
840    unsigned set1_ws_tcx : 1;
841    unsigned set2_pcd : 1;
842    unsigned set2_ws_tcz : 1;
843    unsigned set2_ws_tcy : 1;
844    unsigned set2_ws_tcx : 1;
845    unsigned set3_pcd : 1;
846    unsigned set3_ws_tcz : 1;
847    unsigned set3_ws_tcy : 1;
848    unsigned set3_ws_tcx : 1;
849    unsigned set4_pcd : 1;
850    unsigned set4_ws_tcz : 1;
851    unsigned set4_ws_tcy : 1;
852    unsigned set4_ws_tcx : 1;
853    unsigned set5_pcd : 1;
854    unsigned set5_ws_tcz : 1;
855    unsigned set5_ws_tcy : 1;
856    unsigned set5_ws_tcx : 1;
857    unsigned set6_pcd : 1;
858    unsigned set6_ws_tcz : 1;
859    unsigned set6_ws_tcy : 1;
860    unsigned set6_ws_tcx : 1;
861    unsigned set7_pcd : 1;
862    unsigned set7_ws_tcz : 1;
863    unsigned set7_ws_tcy : 1;
864    unsigned set7_ws_tcx : 1;
865};
866
867#define VERTEXHAS_XYZ      1
868#define VERTEXHAS_XYZW     2
869#define VERTEXHAS_XY       3
870#define VERTEXHAS_XYW      4
871
872#define CULLMODE_BOTH      0
873#define CULLMODE_NONE      1
874#define CULLMODE_CW        2
875#define CULLMODE_CCW       3
876
877#define SHADEMODE_LINEAR   0
878#define SHADEMODE_FLAT     1
879struct s4_dword
880{
881    unsigned anti_aliasing_enable : 1;
882    unsigned sprite_point_enable : 1;
883    unsigned fog_parameter_present : 1;
884    unsigned local_depth_offset_enable : 1;
885    unsigned force_specular_diffuse_color : 1;
886    unsigned force_default_diffuse_color : 1;
887    unsigned position_mask : 3;
888    unsigned local_depth_offset_present : 1;
889    unsigned diffuse_color_presetn : 1;
890    unsigned specular_color_fog_factor_present : 1;
891    unsigned point_width_present : 1;
892    unsigned cull_mode : 2;
893    unsigned color_shade_mode : 1;
894    unsigned specular_shade_mode : 1;
895    unsigned fog_shade_mode : 1;
896    unsigned alpha_shade_mode : 1;
897    unsigned line_width : 4;
898    unsigned point_width : 9;
899};
900
901struct s5_dword
902{
903    unsigned logic_op_enable : 1;
904    unsigned color_dither_enable  : 1;
905    unsigned stencil_test_enable : 1;
906    unsigned stencil_buffer_write_enable : 1;
907    unsigned stencil_pass_depth_pass_op : 3;
908    unsigned stencil_pass_depth_fail_op : 3;
909    unsigned stencil_fail_op : 3;
910    unsigned stencil_test_function : 3;
911    unsigned stencil_reference_value : 8;
912    unsigned fog_enable : 1;
913    unsigned global_depth_offset_enable : 1;
914    unsigned last_pixel_enable : 1;
915    unsigned force_default_point_width : 1;
916    unsigned color_buffer_component_write_disable : 4;
917};
918
919struct s6_dword
920{
921    unsigned triangle_pv : 2;
922    unsigned color_buffer_write : 1;
923    unsigned depth_buffer_write : 1;
924    unsigned dest_blend_factor : 4;
925    unsigned src_blend_factor : 4;
926    unsigned color_blend_function : 3;
927    unsigned color_buffer_blend : 1;
928    unsigned depth_test_function : 3;
929    unsigned depth_test_enable : 1;
930    unsigned alpha_reference_value : 8;
931    unsigned alpha_test_function : 3;
932    unsigned alpha_test_enable : 1;
933
934};
935
936struct s7_dword
937{
938    unsigned global_depth_offset_const;
939};
940
941struct i915_3dstate_load_state_immediate_1
942{
943    struct {
944        unsigned length : 4;
945        unsigned load_s0 : 1;
946        unsigned load_s1 : 1;
947        unsigned load_s2 : 1;
948        unsigned load_s3 : 1;
949        unsigned load_s4 : 1;
950        unsigned load_s5 : 1;
951        unsigned load_s6 : 1;
952        unsigned load_s7 : 1;
953        unsigned pad0 : 4;
954        unsigned opcode : 13;
955        unsigned type : 3;
956    } dw0;
957};
958
959struct i915_3dstate_scissor_rectangle
960{
961    struct {
962        unsigned length : 16;
963        unsigned opcode : 13;
964        unsigned type : 3;
965    } dw0;
966
967    struct {
968        unsigned min_x : 16;
969        unsigned min_y : 16;
970    } dw1;
971
972    struct {
973        unsigned max_x : 16;
974        unsigned max_y : 16;
975    } dw2;
976};
977
978#define VERTEX_INLINE         0x00
979#define VERTEX_INDIRECT       0x01
980
981#define PRIM_TRILIST          0x00
982#define PRIM_TRISTRIP         0x01
983#define PRIM_TRISTRIP_REVERSE 0x02
984#define PRIM_TRIFAN           0x03
985#define PRIM_POLYGON          0x04
986#define PRIM_LINELIST         0x05
987#define PRIM_LINESTRIP        0x06
988#define PRIM_RECTLIST         0x07
989#define PRIM_POINTLIST        0x08
990#define PRIM_DIB              0x09
991#define PRIM_CLEAR_RECT       0x0a
992#define PRIM_ZONE_INIT        0x0d
993
994struct texture_coordinate_set
995{
996    unsigned tcx;
997    unsigned tcy;
998};
999
1000struct vertex_data
1001{
1002    unsigned x;
1003    unsigned y;
1004    struct texture_coordinate_set tc0;
1005    struct texture_coordinate_set tc1;
1006};
1007
1008struct i915_3dprimitive
1009{
1010    union {
1011        struct {
1012            unsigned length : 18;
1013            unsigned prim : 5;
1014            unsigned vertex_location : 1;
1015            unsigned opcode : 5;
1016            unsigned type : 3;
1017        } inline_prim;
1018
1019        struct {
1020            unsigned vertex_count : 16;
1021            unsigned pad0 : 1;
1022            unsigned vertex_access_mode : 1;
1023            unsigned prim : 5;
1024            unsigned vertex_location : 1;
1025            unsigned opcode : 5;
1026            unsigned type : 3;
1027        } indirect_prim;
1028    } dw0;
1029};
1030#endif /*_I915_STRUCTS_H */
1031