103b705cfSriastradh
203b705cfSriastradh#ifndef _I810_DRI_
303b705cfSriastradh#define _I810_DRI_
403b705cfSriastradh
503b705cfSriastradh#include "xf86drm.h"
603b705cfSriastradh#include "i810_common.h"
703b705cfSriastradh
803b705cfSriastradh#define I810_MAX_DRAWABLES 256
903b705cfSriastradh
1003b705cfSriastradh#define I810_MAJOR_VERSION 1
1103b705cfSriastradh#define I810_MINOR_VERSION 7
1203b705cfSriastradh#define I810_PATCHLEVEL 4
1303b705cfSriastradh
1403b705cfSriastradhtypedef struct {
1503b705cfSriastradh   drm_handle_t regs;
1603b705cfSriastradh   drmSize regsSize;
1703b705cfSriastradh
1803b705cfSriastradh   drmSize backbufferSize;
1903b705cfSriastradh   drm_handle_t backbuffer;
2003b705cfSriastradh
2103b705cfSriastradh   drmSize depthbufferSize;
2203b705cfSriastradh   drm_handle_t depthbuffer;
2303b705cfSriastradh
2403b705cfSriastradh   drm_handle_t textures;
2503b705cfSriastradh   int textureSize;
2603b705cfSriastradh
2703b705cfSriastradh   drm_handle_t agp_buffers;
2803b705cfSriastradh   drmSize agp_buf_size;
2903b705cfSriastradh
3003b705cfSriastradh   int deviceID;
3103b705cfSriastradh   int width;
3203b705cfSriastradh   int height;
3303b705cfSriastradh   int mem;
3403b705cfSriastradh   int cpp;
3503b705cfSriastradh   int bitsPerPixel;
3603b705cfSriastradh   int fbOffset;
3703b705cfSriastradh   int fbStride;
3803b705cfSriastradh
3903b705cfSriastradh   int backOffset;
4003b705cfSriastradh   int depthOffset;
4103b705cfSriastradh
4203b705cfSriastradh   int auxPitch;
4303b705cfSriastradh   int auxPitchBits;
4403b705cfSriastradh
4503b705cfSriastradh   int logTextureGranularity;
4603b705cfSriastradh   int textureOffset;
4703b705cfSriastradh
4803b705cfSriastradh   /* For non-dma direct rendering.
4903b705cfSriastradh    */
5003b705cfSriastradh   int ringOffset;
5103b705cfSriastradh   int ringSize;
5203b705cfSriastradh
5303b705cfSriastradh   drmBufMapPtr drmBufs;
5403b705cfSriastradh   int irq;
5503b705cfSriastradh   unsigned int sarea_priv_offset;
5603b705cfSriastradh
5703b705cfSriastradh} I810DRIRec, *I810DRIPtr;
5803b705cfSriastradh
5903b705cfSriastradh/* WARNING: Do not change the SAREA structure without changing the kernel
6003b705cfSriastradh * as well */
6103b705cfSriastradh
6203b705cfSriastradh#define I810_UPLOAD_TEX0IMAGE  0x1	/* handled clientside */
6303b705cfSriastradh#define I810_UPLOAD_TEX1IMAGE  0x2	/* handled clientside */
6403b705cfSriastradh#define I810_UPLOAD_CTX        0x4
6503b705cfSriastradh#define I810_UPLOAD_BUFFERS    0x8
6603b705cfSriastradh#define I810_UPLOAD_TEX0       0x10
6703b705cfSriastradh#define I810_UPLOAD_TEX1       0x20
6803b705cfSriastradh#define I810_UPLOAD_CLIPRECTS  0x40
6903b705cfSriastradh
7003b705cfSriastradhtypedef struct {
7103b705cfSriastradh   unsigned char next, prev;		/* indices to form a circular LRU  */
7203b705cfSriastradh   unsigned char in_use;		/* owned by a client, or free? */
7303b705cfSriastradh   int age;				/* tracked by clients to update local LRU's */
7403b705cfSriastradh} I810TexRegionRec, *I810TexRegionPtr;
7503b705cfSriastradh
7603b705cfSriastradhtypedef struct {
7703b705cfSriastradh   unsigned int ContextState[I810_CTX_SETUP_SIZE];
7803b705cfSriastradh   unsigned int BufferState[I810_DEST_SETUP_SIZE];
7903b705cfSriastradh   unsigned int TexState[2][I810_TEX_SETUP_SIZE];
8003b705cfSriastradh   unsigned int dirty;
8103b705cfSriastradh
8203b705cfSriastradh   unsigned int nbox;
8303b705cfSriastradh   drm_clip_rect_t boxes[I810_NR_SAREA_CLIPRECTS];
8403b705cfSriastradh
8503b705cfSriastradh   /* Maintain an LRU of contiguous regions of texture space.  If
8603b705cfSriastradh    * you think you own a region of texture memory, and it has an
8703b705cfSriastradh    * age different to the one you set, then you are mistaken and
8803b705cfSriastradh    * it has been stolen by another client.  If global texAge
8903b705cfSriastradh    * hasn't changed, there is no need to walk the list.
9003b705cfSriastradh    *
9103b705cfSriastradh    * These regions can be used as a proxy for the fine-grained
9203b705cfSriastradh    * texture information of other clients - by maintaining them
9303b705cfSriastradh    * in the same lru which is used to age their own textures,
9403b705cfSriastradh    * clients have an approximate lru for the whole of global
9503b705cfSriastradh    * texture space, and can make informed decisions as to which
9603b705cfSriastradh    * areas to kick out.  There is no need to choose whether to
9703b705cfSriastradh    * kick out your own texture or someone else's - simply eject
9803b705cfSriastradh    * them all in LRU order.
9903b705cfSriastradh    */
10003b705cfSriastradh
10103b705cfSriastradh   drmTextureRegion texList[I810_NR_TEX_REGIONS + 1];
10203b705cfSriastradh
10303b705cfSriastradh   /* Last elt is sentinal */
10403b705cfSriastradh   int texAge;				/* last time texture was uploaded */
10503b705cfSriastradh
10603b705cfSriastradh   int last_enqueue;			/* last time a buffer was enqueued */
10703b705cfSriastradh   int last_dispatch;			/* age of the most recently dispatched buffer */
10803b705cfSriastradh   int last_quiescent;			/*  */
10903b705cfSriastradh
11003b705cfSriastradh   int ctxOwner;			/* last context to upload state */
11103b705cfSriastradh
11203b705cfSriastradh   int vertex_prim;
11303b705cfSriastradh
11403b705cfSriastradh   int pf_enabled;                  /* is pageflipping allowed? */
11503b705cfSriastradh   int pf_active;                   /* is pageflipping active right now? */
11603b705cfSriastradh   int pf_current_page; 	    /* which buffer is being displayed? */
11703b705cfSriastradh
11803b705cfSriastradh
11903b705cfSriastradh} I810SAREARec, *I810SAREAPtr;
12003b705cfSriastradh
12103b705cfSriastradhtypedef struct {
12203b705cfSriastradh   /* Nothing here yet */
12303b705cfSriastradh   int dummy;
12403b705cfSriastradh} I810ConfigPrivRec, *I810ConfigPrivPtr;
12503b705cfSriastradh
12603b705cfSriastradhtypedef struct {
12703b705cfSriastradh   /* Nothing here yet */
12803b705cfSriastradh   int dummy;
12903b705cfSriastradh} I810DRIContextRec, *I810DRIContextPtr;
13003b705cfSriastradh
13103b705cfSriastradh#endif
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