103b705cfSriastradh/*
203b705cfSriastradh * Copyright © 2006 Intel Corporation
303b705cfSriastradh *
403b705cfSriastradh * Permission is hereby granted, free of charge, to any person obtaining a
503b705cfSriastradh * copy of this software and associated documentation files (the "Software"),
603b705cfSriastradh * to deal in the Software without restriction, including without limitation
703b705cfSriastradh * the rights to use, copy, modify, merge, publish, distribute, sublicense,
803b705cfSriastradh * and/or sell copies of the Software, and to permit persons to whom the
903b705cfSriastradh * Software is furnished to do so, subject to the following conditions:
1003b705cfSriastradh *
1103b705cfSriastradh * The above copyright notice and this permission notice (including the next
1203b705cfSriastradh * paragraph) shall be included in all copies or substantial portions of the
1303b705cfSriastradh * Software.
1403b705cfSriastradh *
1503b705cfSriastradh * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1603b705cfSriastradh * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1703b705cfSriastradh * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
1803b705cfSriastradh * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
1903b705cfSriastradh * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2003b705cfSriastradh * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
2103b705cfSriastradh * IN THE SOFTWARE.
2203b705cfSriastradh *
2303b705cfSriastradh * Authors:
2403b705cfSriastradh *    Wang Zhenyu <zhenyu.z.wang@intel.com>
2503b705cfSriastradh *    Keith Packard <keithp@keithp.com>
2603b705cfSriastradh */
2703b705cfSriastradh
2803b705cfSriastradhinclude(`exa_wm.g4i')
2903b705cfSriastradh
3003b705cfSriastradh/*
3103b705cfSriastradh * Prepare data in m2-m5 for subspan(1,0), m6-m9 for subspan(3,2),
3203b705cfSriastradh */
3303b705cfSriastradh
3403b705cfSriastradhmov (16) m130<1>F	src_sample_r_01<8,8,1>F { align1 compr };
3503b705cfSriastradhmov (16) m131<1>F	src_sample_g_01<8,8,1>F { align1 compr };
3603b705cfSriastradhmov (16) m132<1>F	src_sample_b_01<8,8,1>F { align1 compr };
3703b705cfSriastradhmov (16) m133<1>F	src_sample_a_01<8,8,1>F { align1 compr };
3803b705cfSriastradh
3903b705cfSriastradh/* m0, m1 are all direct passed by PS thread payload */
4003b705cfSriastradhmov (8) data_port_msg_1<1>F	g1<8,8,1>F		{ mask_disable align1 };
4103b705cfSriastradh
4203b705cfSriastradh/* write */
4303b705cfSriastradhsend (16) 
4403b705cfSriastradh	data_port_msg_0_ind 
4503b705cfSriastradh	acc0<1>UW
4603b705cfSriastradh	g0<8,8,1>UW 
4703b705cfSriastradh	write (
4803b705cfSriastradh	       0,  /* binding_table */
4903b705cfSriastradh	       8,  /* pixel scordboard clear, msg type simd16 single source */
5003b705cfSriastradh	       4,  /* render target write */
5103b705cfSriastradh	       0   /* no write commit message */
5203b705cfSriastradh	) 
5303b705cfSriastradh	mlen 10
5403b705cfSriastradh	rlen 0
5503b705cfSriastradh	{ align1 EOT };
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