i965_3d.c revision 42542f5f 
1/*
2 * Copyright � 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#ifdef HAVE_CONFIG_H
25#include "config.h"
26#endif
27
28#include <string.h>
29
30#include "intel.h"
31#include "i965_reg.h"
32#include "brw_defines.h"
33
34void
35gen6_upload_invariant_states(intel_screen_private *intel)
36{
37	Bool ivb = INTEL_INFO(intel)->gen >= 070;
38
39	OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
40	OUT_BATCH(BRW_PIPE_CONTROL_IS_FLUSH |
41		BRW_PIPE_CONTROL_WC_FLUSH |
42		BRW_PIPE_CONTROL_DEPTH_CACHE_FLUSH |
43		BRW_PIPE_CONTROL_NOWRITE);
44	OUT_BATCH(0); /* write address */
45	OUT_BATCH(0); /* write data */
46
47	OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
48
49	OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | ((ivb ? 4 : 3) - 2));
50	OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
51		GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
52	OUT_BATCH(0);
53	if (ivb)
54		OUT_BATCH(0);
55
56	OUT_BATCH(GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
57	OUT_BATCH(1);
58
59	/* Set system instruction pointer */
60	OUT_BATCH(BRW_STATE_SIP | 0);
61	OUT_BATCH(0);
62}
63
64void
65gen6_upload_viewport_state_pointers(intel_screen_private *intel,
66				    drm_intel_bo *cc_vp_bo)
67{
68	OUT_BATCH(GEN6_3DSTATE_VIEWPORT_STATE_POINTERS |
69		GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC |
70		(4 - 2));
71	OUT_BATCH(0);
72	OUT_BATCH(0);
73	OUT_RELOC(cc_vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
74}
75
76void
77gen7_upload_viewport_state_pointers(intel_screen_private *intel,
78				    drm_intel_bo *cc_vp_bo)
79{
80	OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC | (2 - 2));
81	OUT_RELOC(cc_vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
82
83	OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL | (2 - 2));
84	OUT_BATCH(0);
85}
86
87void
88gen6_upload_urb(intel_screen_private *intel)
89{
90	OUT_BATCH(GEN6_3DSTATE_URB | (3 - 2));
91	OUT_BATCH(((1 - 1) << GEN6_3DSTATE_URB_VS_SIZE_SHIFT) |
92		(24 << GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT)); /* at least 24 on GEN6 */
93	OUT_BATCH((0 << GEN6_3DSTATE_URB_GS_SIZE_SHIFT) |
94		(0 << GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT)); /* no GS thread */
95}
96
97/*
98 * URB layout on GEN7
99 * ----------------------------------------
100 * | PS Push Constants (8KB) | VS entries |
101 * ----------------------------------------
102 */
103void
104gen7_upload_urb(intel_screen_private *intel)
105{
106	unsigned int num_urb_entries = 32;
107
108	if (IS_HSW(intel))
109		num_urb_entries = 64;
110
111	OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2));
112	OUT_BATCH(8); /* in 1KBs */
113
114	OUT_BATCH(GEN7_3DSTATE_URB_VS | (2 - 2));
115	OUT_BATCH(
116		(num_urb_entries << GEN7_URB_ENTRY_NUMBER_SHIFT) |
117		(2 - 1) << GEN7_URB_ENTRY_SIZE_SHIFT |
118		(1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
119
120	OUT_BATCH(GEN7_3DSTATE_URB_GS | (2 - 2));
121	OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
122		(1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
123
124	OUT_BATCH(GEN7_3DSTATE_URB_HS | (2 - 2));
125	OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
126		(2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
127
128	OUT_BATCH(GEN7_3DSTATE_URB_DS | (2 - 2));
129	OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
130		(2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
131}
132
133void
134gen6_upload_cc_state_pointers(intel_screen_private *intel,
135			      drm_intel_bo *blend_bo,
136			      drm_intel_bo *cc_bo,
137			      drm_intel_bo *depth_stencil_bo,
138			      uint32_t blend_offset)
139{
140	OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2));
141	if (blend_bo)
142		OUT_RELOC(blend_bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
143			  blend_offset | 1);
144	else
145		OUT_BATCH(0);
146
147	if (depth_stencil_bo)
148		OUT_RELOC(depth_stencil_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
149	else
150		OUT_BATCH(0);
151
152	if (cc_bo)
153		OUT_RELOC(cc_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
154	else
155		OUT_BATCH(0);
156}
157
158void
159gen7_upload_cc_state_pointers(intel_screen_private *intel,
160			      drm_intel_bo *blend_bo,
161			      drm_intel_bo *cc_bo,
162			      drm_intel_bo *depth_stencil_bo,
163			      uint32_t blend_offset)
164{
165	OUT_BATCH(GEN7_3DSTATE_BLEND_STATE_POINTERS | (2 - 2));
166	if (blend_bo)
167		OUT_RELOC(blend_bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
168			  blend_offset | 1);
169	else
170		OUT_BATCH(0);
171
172	OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (2 - 2));
173	if (cc_bo)
174		OUT_RELOC(cc_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
175	else
176		OUT_BATCH(0);
177
178	OUT_BATCH(GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS | (2 - 2));
179	if (depth_stencil_bo)
180		OUT_RELOC(depth_stencil_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
181	else
182		OUT_BATCH(0);
183}
184
185void
186gen6_upload_sampler_state_pointers(intel_screen_private *intel,
187				   drm_intel_bo *sampler_bo)
188{
189	OUT_BATCH(GEN6_3DSTATE_SAMPLER_STATE_POINTERS |
190		GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS |
191		(4 - 2));
192	OUT_BATCH(0); /* VS */
193	OUT_BATCH(0); /* GS */
194	OUT_RELOC(sampler_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
195}
196
197void
198gen7_upload_sampler_state_pointers(intel_screen_private *intel,
199				   drm_intel_bo *sampler_bo)
200{
201	OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS | (2 - 2));
202	OUT_RELOC(sampler_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
203}
204
205void
206gen7_upload_bypass_states(intel_screen_private *intel)
207{
208	/* bypass GS */
209	OUT_BATCH(GEN6_3DSTATE_CONSTANT_GS | (7 - 2));
210	OUT_BATCH(0);
211	OUT_BATCH(0);
212	OUT_BATCH(0);
213	OUT_BATCH(0);
214	OUT_BATCH(0);
215	OUT_BATCH(0);
216
217	OUT_BATCH(GEN6_3DSTATE_GS | (7 - 2));
218	OUT_BATCH(0); /* without GS kernel */
219	OUT_BATCH(0);
220	OUT_BATCH(0);
221	OUT_BATCH(0);
222	OUT_BATCH(0);
223	OUT_BATCH(0); /* pass-through */
224
225	OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS | (2 - 2));
226	OUT_BATCH(0);
227
228	/* disable HS */
229	OUT_BATCH(GEN7_3DSTATE_CONSTANT_HS | (7 - 2));
230	OUT_BATCH(0);
231	OUT_BATCH(0);
232	OUT_BATCH(0);
233	OUT_BATCH(0);
234	OUT_BATCH(0);
235	OUT_BATCH(0);
236
237	OUT_BATCH(GEN7_3DSTATE_HS | (7 - 2));
238	OUT_BATCH(0);
239	OUT_BATCH(0);
240	OUT_BATCH(0);
241	OUT_BATCH(0);
242	OUT_BATCH(0);
243	OUT_BATCH(0);
244
245	OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS | (2 - 2));
246	OUT_BATCH(0);
247
248	/* Disable TE */
249	OUT_BATCH(GEN7_3DSTATE_TE | (4 - 2));
250	OUT_BATCH(0);
251	OUT_BATCH(0);
252	OUT_BATCH(0);
253
254	/* Disable DS */
255	OUT_BATCH(GEN7_3DSTATE_CONSTANT_DS | (7 - 2));
256	OUT_BATCH(0);
257	OUT_BATCH(0);
258	OUT_BATCH(0);
259	OUT_BATCH(0);
260	OUT_BATCH(0);
261	OUT_BATCH(0);
262
263	OUT_BATCH(GEN7_3DSTATE_DS | (6 - 2));
264	OUT_BATCH(0);
265	OUT_BATCH(0);
266	OUT_BATCH(0);
267	OUT_BATCH(0);
268	OUT_BATCH(0);
269
270	OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS | (2 - 2));
271	OUT_BATCH(0);
272
273	/* Disable STREAMOUT */
274	OUT_BATCH(GEN7_3DSTATE_STREAMOUT | (3 - 2));
275	OUT_BATCH(0);
276	OUT_BATCH(0);
277}
278
279void
280gen6_upload_vs_state(intel_screen_private *intel)
281{
282	Bool ivb = INTEL_INFO(intel)->gen >= 070;
283	/* disable VS constant buffer */
284	OUT_BATCH(GEN6_3DSTATE_CONSTANT_VS | ((ivb ? 7 : 5) - 2));
285	OUT_BATCH(0);
286	OUT_BATCH(0);
287	OUT_BATCH(0);
288	OUT_BATCH(0);
289	if (ivb) {
290		OUT_BATCH(0);
291		OUT_BATCH(0);
292	}
293
294	OUT_BATCH(GEN6_3DSTATE_VS | (6 - 2));
295	OUT_BATCH(0); /* without VS kernel */
296	OUT_BATCH(0);
297	OUT_BATCH(0);
298	OUT_BATCH(0);
299	OUT_BATCH(0); /* pass-through */
300}
301
302void
303gen6_upload_gs_state(intel_screen_private *intel)
304{
305	/* disable GS constant buffer */
306	OUT_BATCH(GEN6_3DSTATE_CONSTANT_GS | (5 - 2));
307	OUT_BATCH(0);
308	OUT_BATCH(0);
309	OUT_BATCH(0);
310	OUT_BATCH(0);
311
312	OUT_BATCH(GEN6_3DSTATE_GS | (7 - 2));
313	OUT_BATCH(0); /* without GS kernel */
314	OUT_BATCH(0);
315	OUT_BATCH(0);
316	OUT_BATCH(0);
317	OUT_BATCH(0);
318	OUT_BATCH(0); /* pass-through */
319}
320
321void
322gen6_upload_clip_state(intel_screen_private *intel)
323{
324	OUT_BATCH(GEN6_3DSTATE_CLIP | (4 - 2));
325	OUT_BATCH(0);
326	OUT_BATCH(0); /* pass-through */
327	OUT_BATCH(0);
328}
329
330void
331gen6_upload_sf_state(intel_screen_private *intel,
332		     int num_sf_outputs,
333		     int read_offset)
334{
335	OUT_BATCH(GEN6_3DSTATE_SF | (20 - 2));
336	OUT_BATCH((num_sf_outputs << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT) |
337		(1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT) |
338		(read_offset << GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT));
339	OUT_BATCH(0);
340	OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE);
341	OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); /* DW4 */
342	OUT_BATCH(0);
343	OUT_BATCH(0);
344	OUT_BATCH(0);
345	OUT_BATCH(0);
346	OUT_BATCH(0); /* DW9 */
347	OUT_BATCH(0);
348	OUT_BATCH(0);
349	OUT_BATCH(0);
350	OUT_BATCH(0);
351	OUT_BATCH(0); /* DW14 */
352	OUT_BATCH(0);
353	OUT_BATCH(0);
354	OUT_BATCH(0);
355	OUT_BATCH(0);
356	OUT_BATCH(0); /* DW19 */
357}
358
359void
360gen7_upload_sf_state(intel_screen_private *intel,
361		     int num_sf_outputs,
362		     int read_offset)
363{
364	OUT_BATCH(GEN7_3DSTATE_SBE | (14 - 2));
365	OUT_BATCH((num_sf_outputs << GEN7_SBE_NUM_OUTPUTS_SHIFT) |
366		(1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT) |
367		(read_offset << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT));
368	OUT_BATCH(0);
369	OUT_BATCH(0);
370	OUT_BATCH(0); /* DW4 */
371	OUT_BATCH(0);
372	OUT_BATCH(0);
373	OUT_BATCH(0);
374	OUT_BATCH(0);
375	OUT_BATCH(0); /* DW9 */
376	OUT_BATCH(0);
377	OUT_BATCH(0);
378	OUT_BATCH(0);
379	OUT_BATCH(0);
380
381	OUT_BATCH(GEN6_3DSTATE_SF | (7 - 2));
382	OUT_BATCH(0);
383	OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE);
384	OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT);
385	OUT_BATCH(0);
386	OUT_BATCH(0);
387	OUT_BATCH(0);
388}
389
390void
391gen6_upload_binding_table(intel_screen_private *intel,
392			  uint32_t ps_binding_table_offset)
393{
394	/* Binding table pointers */
395	OUT_BATCH(BRW_3DSTATE_BINDING_TABLE_POINTERS |
396		  GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS |
397		  (4 - 2));
398	OUT_BATCH(0); /* VS */
399	OUT_BATCH(0); /* GS */
400	/* Only the PS uses the binding table */
401	OUT_BATCH(ps_binding_table_offset);
402}
403
404void
405gen7_upload_binding_table(intel_screen_private *intel,
406			  uint32_t ps_binding_table_offset)
407{
408	OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS | (2 - 2));
409	OUT_BATCH(ps_binding_table_offset);
410}
411
412void
413gen6_upload_depth_buffer_state(intel_screen_private *intel)
414{
415	OUT_BATCH(BRW_3DSTATE_DEPTH_BUFFER | (7 - 2));
416	OUT_BATCH((BRW_SURFACE_NULL << BRW_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT) |
417		  (BRW_DEPTHFORMAT_D32_FLOAT << BRW_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT));
418	OUT_BATCH(0);
419	OUT_BATCH(0);
420	OUT_BATCH(0);
421	OUT_BATCH(0);
422	OUT_BATCH(0);
423
424	OUT_BATCH(BRW_3DSTATE_CLEAR_PARAMS | (2 - 2));
425	OUT_BATCH(0);
426}
427
428void
429gen7_upload_depth_buffer_state(intel_screen_private *intel)
430{
431	OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER | (7 - 2));
432	OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) | (BRW_SURFACE_NULL << 29));
433	OUT_BATCH(0);
434	OUT_BATCH(0);
435	OUT_BATCH(0);
436	OUT_BATCH(0);
437	OUT_BATCH(0);
438
439	OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS | (3 - 2));
440	OUT_BATCH(0);
441	OUT_BATCH(0);
442}
443