atipreinit.c revision d31dbc53
1/* 2 * Copyright 1999 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that copyright 7 * notice and this permission notice appear in supporting documentation, and 8 * that the name of Marc Aurele La France not be used in advertising or 9 * publicity pertaining to distribution of the software without specific, 10 * written prior permission. Marc Aurele La France makes no representations 11 * about the suitability of this software for any purpose. It is provided 12 * "as-is" without express or implied warranty. 13 * 14 * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO 16 * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 20 * PERFORMANCE OF THIS SOFTWARE. 21 */ 22 23#ifdef HAVE_CONFIG_H 24#include "config.h" 25#endif 26 27#include <string.h> 28#include <stdio.h> 29 30#include "ati.h" 31#include "atiadjust.h" 32#include "atiaudio.h" 33#include "atibus.h" 34#include "atichip.h" 35#include "aticursor.h" 36#include "atidac.h" 37#include "atidsp.h" 38#include "atii2c.h" 39#include "atiload.h" 40#include "atilock.h" 41#include "atimach64.h" 42#include "atimach64accel.h" 43#include "atimach64io.h" 44#include "atimach64probe.h" 45#include "atimode.h" 46#include "atioption.h" 47#include "atipreinit.h" 48#include "atiprint.h" 49#include "atiprobe.h" 50#include "atividmem.h" 51#include "atiwonderio.h" 52#include "atixv.h" 53 54#include "vbe.h" 55#include "xf86RAC.h" 56 57/* 58 * FreeScreen handles the clean-up. 59 */ 60static Bool 61Mach64GetRec(ScrnInfoPtr pScrn) 62{ 63 if (!pScrn->driverPrivate) { 64 pScrn->driverPrivate = xnfcalloc(sizeof(ATIRec), 1); 65 memset(pScrn->driverPrivate, 0, sizeof(ATIRec)); 66 } 67 68 return TRUE; 69} 70 71/* 72 * ATIReportMemory -- 73 * 74 * This function reports on the amount and type of video memory found. 75 */ 76static void 77ATIReportMemory 78( 79 ScrnInfoPtr pScreenInfo, 80 ATIPtr pATI, 81 const char *MemoryTypeName 82) 83{ 84 char Buffer[128], *Message; 85 86 Message = Buffer + 87 snprintf(Buffer, SizeOf(Buffer), "%d kB of %s detected", 88 pATI->VideoRAM, MemoryTypeName); 89 90 if (pATI->VideoRAM > pScreenInfo->videoRam) 91 { 92 Message += snprintf(Message, Buffer + SizeOf(Buffer) - Message, 93 " (using %d kB)", pScreenInfo->videoRam); 94 } 95 xf86DrvMsg(pScreenInfo->scrnIndex, X_PROBED, "%s.\n", Buffer); 96} 97 98static const int videoRamSizes[] = 99 {512, 1024, 2*1024, 4*1024, 6*1024, 8*1024, 12*1024, 16*1024}; 100static const rgb defaultWeight = {0, 0, 0}; 101static const Gamma defaultGamma = {0.0, 0.0, 0.0}; 102 103/* 104 * ATIPrintNoiseIfRequested -- 105 * 106 * This function formats debugging information on the server's stderr when 107 * requested by the user through the server's verbosity setting. 108 */ 109static void 110ATIPrintNoiseIfRequested 111( 112 ATIPtr pATI, 113 CARD8 *BIOS, 114 unsigned int BIOSSize 115) 116{ 117 if (xf86GetVerbosity() <= 3) 118 return; 119 120 if (BIOSSize > 0) 121 ATIPrintBIOS(BIOS, BIOSSize); 122 xf86ErrorFVerb(4, "\n On server entry:\n"); 123 ATIPrintRegisters(pATI); 124} 125 126#define BIOS_SIZE 0x00010000U /* 64kB */ 127#define BIOSByte(_n) ((CARD8)(BIOS[_n])) 128#define BIOSWord(_n) ((CARD16)(BIOS[_n] | \ 129 (BIOS[(_n) + 1] << 8))) 130 131/* 132 * For Mach64 adapters, pick up, from the BIOS, the type of programmable 133 * clock generator (if any), and various information about it. 134 */ 135static void 136ati_bios_clock 137( 138 ScrnInfoPtr pScreenInfo, 139 ATIPtr pATI, 140 CARD8 *BIOS, 141 unsigned int ClockTable, 142 GDevPtr pGDev 143) 144{ 145 CARD16 ClockDac; 146 147 if (ClockTable > 0) 148 { 149 pATI->ProgrammableClock = BIOSByte(ClockTable); 150 pATI->ClockNumberToProgramme = BIOSByte(ClockTable + 0x06U); 151 pATI->refclk = BIOSWord(ClockTable + 0x08U); 152 pATI->refclk *= 10000; 153 } 154 else 155 { 156 /* 157 * Compensate for BIOS absence. Note that the reference 158 * frequency has already been set by option processing. 159 */ 160 if ((pATI->DAC & ~0x0FU) == ATI_DAC_INTERNAL) 161 { 162 pATI->ProgrammableClock = ATI_CLOCK_INTERNAL; 163 } 164 else switch (pATI->DAC) 165 { 166 case ATI_DAC_STG1703: 167 pATI->ProgrammableClock = ATI_CLOCK_STG1703; 168 break; 169 170 case ATI_DAC_CH8398: 171 pATI->ProgrammableClock = ATI_CLOCK_CH8398; 172 break; 173 174 case ATI_DAC_ATT20C408: 175 pATI->ProgrammableClock = ATI_CLOCK_ATT20C408; 176 break; 177 178 case ATI_DAC_IBMRGB514: 179 pATI->ProgrammableClock = ATI_CLOCK_IBMRGB514; 180 break; 181 182 default: /* Provisional */ 183 pATI->ProgrammableClock = ATI_CLOCK_ICS2595; 184 break; 185 } 186 187 /* This should be safe for all generators except IBM's RGB514 */ 188 pATI->ClockNumberToProgramme = 3; 189 } 190 191 pATI->ClockDescriptor = ATIClockDescriptors[ATI_CLOCK_FIXED]; 192 193 if ((pATI->ProgrammableClock > ATI_CLOCK_FIXED) && 194 (pATI->ProgrammableClock < ATI_CLOCK_MAX)) 195 { 196 /* 197 * Graphics PRO TURBO 1600's are unusual in that an ICS2595 is used 198 * to generate clocks for VGA modes, and an IBM RGB514 is used for 199 * accelerator modes. 200 */ 201 if ((pATI->ProgrammableClock == ATI_CLOCK_ICS2595) && 202 (pATI->DAC == ATI_DAC_IBMRGB514)) 203 pATI->ProgrammableClock = ATI_CLOCK_IBMRGB514; 204 205 pATI->ClockDescriptor = ATIClockDescriptors[pATI->ProgrammableClock]; 206 } 207 208 ClockDac = pATI->DAC; 209 switch (pATI->ProgrammableClock) 210 { 211 case ATI_CLOCK_ICS2595: 212 /* 213 * Pick up reference divider (43 or 46) appropriate to the chip 214 * revision level. 215 */ 216 if (ClockTable > 0) 217 pATI->ClockDescriptor.MinM = 218 pATI->ClockDescriptor.MaxM = BIOSWord(ClockTable + 0x0AU); 219 else if (!xf86NameCmp(pGDev->clockchip, "ATI 18818-0")) 220 pATI->ClockDescriptor.MinM = 221 pATI->ClockDescriptor.MaxM = 43; 222 else if (!xf86NameCmp(pGDev->clockchip, "ATI 18818-1")) 223 pATI->ClockDescriptor.MinM = 224 pATI->ClockDescriptor.MaxM = 46; 225 else 226 pATI->ProgrammableClock = ATI_CLOCK_UNKNOWN; 227 break; 228 229 case ATI_CLOCK_STG1703: 230 /* This one's also a RAMDAC */ 231 ClockDac = ATI_DAC_STG1703; 232 break; 233 234 case ATI_CLOCK_CH8398: 235 /* This one's also a RAMDAC */ 236 ClockDac = ATI_DAC_CH8398; 237 break; 238 239 case ATI_CLOCK_INTERNAL: 240 /* 241 * The reference divider has already been programmed by BIOS 242 * initialisation. Because, there is only one reference 243 * divider for all generated frequencies (including MCLK), it 244 * cannot be changed without reprogramming all clocks every 245 * time one of them needs a different reference divider. 246 * 247 * Besides, it's not a good idea to change the reference 248 * divider. BIOS initialisation sets it to a value that 249 * effectively prevents generating frequencies beyond the 250 * graphics controller's tolerance. 251 */ 252 pATI->ClockDescriptor.MinM = 253 pATI->ClockDescriptor.MaxM = ATIMach64GetPLLReg(PLL_REF_DIV); 254 255 /* The DAC is also integrated */ 256 if ((pATI->DAC & ~0x0FU) != ATI_DAC_INTERNAL) 257 ClockDac = ATI_DAC_INTERNAL; 258 259 break; 260 261 case ATI_CLOCK_ATT20C408: 262 /* This one's also a RAMDAC */ 263 ClockDac = ATI_DAC_ATT20C408; 264 break; 265 266 case ATI_CLOCK_IBMRGB514: 267 /* This one's also a RAMDAC */ 268 ClockDac = ATI_DAC_IBMRGB514; 269 pATI->ClockNumberToProgramme = 7; 270 break; 271 272 default: 273 break; 274 } 275 276 /* 277 * We now have up to two indications of what RAMDAC the adapter uses. 278 * They should be the same. The following test and corresponding 279 * action are under construction. 280 */ 281 if (pATI->DAC != ClockDac) 282 { 283 xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING, 284 "Mach64 RAMDAC probe discrepancy detected:\n" 285 " DAC=0x%02X; ClockDac=0x%02X.\n", 286 pATI->DAC, ClockDac); 287 288 if (pATI->DAC == ATI_DAC_IBMRGB514) 289 { 290 pATI->ProgrammableClock = ATI_CLOCK_IBMRGB514; 291 pATI->ClockDescriptor = ATIClockDescriptors[ATI_CLOCK_IBMRGB514]; 292 pATI->ClockNumberToProgramme = 7; 293 } 294 else 295 { 296 pATI->DAC = ClockDac; /* For now */ 297 } 298 } 299 300 switch (pATI->refclk / 100000) 301 { 302 case 143: 303 pATI->ReferenceNumerator = 157500; 304 pATI->ReferenceDenominator = 11; 305 break; 306 307 case 286: 308 pATI->ReferenceNumerator = 315000; 309 pATI->ReferenceDenominator = 11; 310 break; 311 312 default: 313 pATI->ReferenceNumerator = pATI->refclk / 1000; 314 pATI->ReferenceDenominator = 1; 315 break; 316 } 317} 318 319/* 320 * Pick up multimedia information, which will be at different 321 * displacements depending on table revision. 322 */ 323static void 324ati_bios_mmedia 325( 326 ScrnInfoPtr pScreenInfo, 327 ATIPtr pATI, 328 CARD8 *BIOS, 329 unsigned int VideoTable, 330 unsigned int HardwareTable 331) 332{ 333 pATI->Audio = ATI_AUDIO_NONE; 334 335 if (VideoTable > 0) 336 { 337 switch (BIOSByte(VideoTable - 0x02U)) 338 { 339 case 0x00U: 340 pATI->Tuner = BIOSByte(VideoTable) & 0x1FU; 341 342 /* 343 * XXX The VideoTable[1] byte is known to have been 344 * omitted in LTPro and Mobility BIOS'es. Any others? 345 */ 346 switch (pATI->Chip) 347 { 348 case ATI_CHIP_264LTPRO: 349 case ATI_CHIP_MOBILITY: 350 pATI->Decoder = BIOSByte(VideoTable + 0x01U) & 0x07U; 351 pATI->Audio = BIOSByte(VideoTable + 0x02U) & 0x0FU; 352 break; 353 354 default: 355 pATI->Decoder = BIOSByte(VideoTable + 0x02U) & 0x07U; 356 pATI->Audio = BIOSByte(VideoTable + 0x03U) & 0x0FU; 357 break; 358 } 359 360 break; 361 362 case 0x01U: 363 pATI->Tuner = BIOSByte(VideoTable) & 0x1FU; 364 pATI->Audio = BIOSByte(VideoTable + 0x01U) & 0x0FU; 365 pATI->Decoder = BIOSByte(VideoTable + 0x05U) & 0x0FU; 366 break; 367 368 default: 369 break; 370 } 371 } 372 373 if (HardwareTable > 0) 374 { 375 pATI->I2CType = BIOSByte(HardwareTable + 0x06U) & 0x0FU; 376 } 377} 378 379/* 380 * Determine panel dimensions and model. 381 */ 382static void 383ati_bios_panel_info 384( 385 ScrnInfoPtr pScreenInfo, 386 ATIPtr pATI, 387 CARD8 *BIOS, 388 unsigned int BIOSSize, 389 unsigned int LCDTable 390) 391{ 392 unsigned int LCDPanelInfo = 0; 393 char Buffer[128]; 394 int i, j; 395 396 if (LCDTable > 0) 397 { 398 LCDPanelInfo = BIOSWord(LCDTable + 0x0AU); 399 if (((LCDPanelInfo + 0x1DU) > BIOSSize) || 400 ((BIOSByte(LCDPanelInfo) != pATI->LCDPanelID) && 401 (pATI->LCDPanelID || (BIOSByte(LCDPanelInfo) > 0x1FU) || 402 (pATI->Chip <= ATI_CHIP_264LTPRO)))) 403 LCDPanelInfo = 0; 404 } 405 406 if (!LCDPanelInfo) 407 { 408 /* 409 * Scan BIOS for panel info table. 410 */ 411 for (i = 0; i <= (int)(BIOSSize - 0x1DU); i++) 412 { 413 /* Look for panel ID ... */ 414 if ((BIOSByte(i) != pATI->LCDPanelID) && 415 (pATI->LCDPanelID || (BIOSByte(i) > 0x1FU) || 416 (pATI->Chip <= ATI_CHIP_264LTPRO))) 417 continue; 418 419 /* ... followed by 24-byte panel model name ... */ 420 for (j = 0; j < 24; j++) 421 { 422 if ((CARD8)(BIOSByte(i + j + 1) - 0x20U) > 0x5FU) 423 { 424 i += j; 425 goto NextBIOSByte; 426 } 427 } 428 429 /* ... verify panel width ... */ 430 if (pATI->LCDHorizontal && 431 (pATI->LCDHorizontal != BIOSWord(i + 0x19U))) 432 continue; 433 434 /* ... and verify panel height */ 435 if (pATI->LCDVertical && 436 (pATI->LCDVertical != BIOSWord(i + 0x1BU))) 437 continue; 438 439 if (LCDPanelInfo) 440 { 441 /* 442 * More than one possibility, but don't care if all 443 * tables describe panels of the same size. 444 */ 445 if ((BIOSByte(LCDPanelInfo + 0x19U) == 446 BIOSByte(i + 0x19U)) && 447 (BIOSByte(LCDPanelInfo + 0x1AU) == 448 BIOSByte(i + 0x1AU)) && 449 (BIOSByte(LCDPanelInfo + 0x1BU) == 450 BIOSByte(i + 0x1BU)) && 451 (BIOSByte(LCDPanelInfo + 0x1CU) == 452 BIOSByte(i + 0x1CU))) 453 continue; 454 455 LCDPanelInfo = 0; 456 break; 457 } 458 459 LCDPanelInfo = i; 460 461 NextBIOSByte: ; 462 } 463 } 464 465 if (LCDPanelInfo > 0) 466 { 467 pATI->LCDPanelID = BIOSByte(LCDPanelInfo); 468 pATI->LCDHorizontal = BIOSWord(LCDPanelInfo + 0x19U); 469 pATI->LCDVertical = BIOSWord(LCDPanelInfo + 0x1BU); 470 } 471 472 if (LCDPanelInfo) 473 { 474 for (i = 0; i < 24; i++) 475 Buffer[i] = BIOSByte(LCDPanelInfo + 1 + i); 476 for (; --i >= 0; ) 477 if (Buffer[i] && Buffer[i] != ' ') 478 { 479 Buffer[i + 1] = '\0'; 480 xf86DrvMsg(pScreenInfo->scrnIndex, X_PROBED, 481 "Panel model %s.\n", Buffer); 482 break; 483 } 484 } 485} 486 487/* 488 * ATIPreInit -- 489 * 490 * This function is only called once per screen at the start of the first 491 * server generation. 492 */ 493Bool 494ATIPreInit 495( 496 ScrnInfoPtr pScreenInfo, 497 int flags 498) 499{ 500 CARD8 BIOS[BIOS_SIZE]; 501 unsigned int BIOSSize = 0; 502 unsigned int ROMTable = 0, ClockTable = 0, FrequencyTable = 0; 503 unsigned int LCDTable = 0, VideoTable = 0; 504 unsigned int HardwareTable = 0; 505 506 char Buffer[128], *Message; 507 ATIPtr pATI; 508 GDevPtr pGDev; 509 EntityInfoPtr pEntity; 510 resPtr pResources; 511 pciVideoPtr pVideo; 512 DisplayModePtr pMode; 513 CARD32 IOValue; 514 int i, j; 515 int Numerator, Denominator; 516 int MinX, MinY; 517 ClockRange ATIClockRange = {NULL, 0, 80000, -1, TRUE, TRUE, 1, 1, 0}; 518 int DefaultmaxClock = 0; 519 int minPitch, maxPitch = 0xFFU, pitchInc, maxHeight = 0; 520 int ApertureSize = 0x00010000U; 521 int ModeType = M_T_BUILTIN; 522 LookupModeFlags Strategy = LOOKUP_CLOSEST_CLOCK; 523 int DefaultDepth; 524 Bool PreInitSuccess = FALSE; 525 526# define pATIHW (&pATI->OldHW) 527 528#ifndef AVOID_CPIO 529 530 xf86Int10InfoPtr pInt10Info = NULL; 531 vbeInfoPtr pVBE = NULL; 532 pointer pInt10Module, pDDCModule = NULL, pVBEModule = NULL; 533 534#endif /* AVOID_CPIO */ 535 536 if (pScreenInfo->numEntities != 1) 537 { 538 xf86DrvMsg(pScreenInfo->scrnIndex, X_ERROR, 539 "Logic error: Number of attached entities not 1.\n"); 540 return FALSE; 541 } 542 543 if (!Mach64GetRec(pScreenInfo)) 544 return FALSE; 545 546 pATI = ATIPTR(pScreenInfo); 547 548 /* Register resources */ 549 pEntity = xf86GetEntityInfo(pScreenInfo->entityList[0]); 550 pGDev = pEntity->device; 551 pResources = pEntity->resources; 552 553 pATI->iEntity = pEntity->index; 554 pATI->Chip = pEntity->chipset; 555 pVideo = xf86GetPciInfoForEntity(pATI->iEntity); 556 557 xfree(pEntity); 558 559 if (!pResources) 560 pResources = xf86RegisterResources(pATI->iEntity, NULL, ResShared); 561 if (pResources) 562 { 563 xf86DrvMsg(pScreenInfo->scrnIndex, X_ERROR, 564 "Unable to register bus resources\n"); 565 xf86FreeResList(pResources); 566 return FALSE; 567 } 568 569 ConfiguredMonitor = NULL; 570 (void)memset(BIOS, 0, SizeOf(BIOS)); 571 572 if (!(flags & PROBE_DETECT)) 573 { 574 /* Set monitor */ 575 pScreenInfo->monitor = pScreenInfo->confScreen->monitor; 576 577 /* Set depth, bpp, etc. */ 578 if ((pATI->Chip < ATI_CHIP_264CT)) 579 { 580 i = NoDepth24Support; /* No support for >8bpp either */ 581 DefaultDepth = 8; 582 } 583 else 584 { 585 i = Support24bppFb | Support32bppFb; 586 DefaultDepth = 0; 587 } 588 589 if (!xf86SetDepthBpp(pScreenInfo, DefaultDepth, 0, 0, i)) 590 return FALSE; 591 592 for (j = 0; ; j++) 593 { 594 static const CARD8 AllowedDepthBpp[][2] = 595 { 596 { 8, 8}, 597 {15, 16}, 598 {16, 16}, 599 {24, 24}, 600 {24, 32} 601 }; 602 603 if (j < NumberOf(AllowedDepthBpp)) 604 { 605 if (pScreenInfo->depth > AllowedDepthBpp[j][0]) 606 continue; 607 608 if (pScreenInfo->depth == AllowedDepthBpp[j][0]) 609 { 610 if (pScreenInfo->bitsPerPixel > AllowedDepthBpp[j][1]) 611 continue; 612 613 if (pScreenInfo->bitsPerPixel == AllowedDepthBpp[j][1]) 614 break; 615 } 616 } 617 618 xf86DrvMsg(pScreenInfo->scrnIndex, X_ERROR, 619 "Driver does not support depth %d at fbbpp %d.\n", 620 pScreenInfo->depth, pScreenInfo->bitsPerPixel); 621 return FALSE; 622 } 623 624 xf86PrintDepthBpp(pScreenInfo); 625 626 if ((i == NoDepth24Support) && (pScreenInfo->depth > 8)) 627 { 628 xf86DrvMsg(pScreenInfo->scrnIndex, X_ERROR, 629 "Depth %d is not supported through this adapter.\n", 630 pScreenInfo->depth); 631 return FALSE; 632 } 633 634 /* Pick up XF86Config options */ 635 ATIProcessOptions(pScreenInfo, pATI); 636 } 637 638 if (!ATIMach64ProbeIO(pVideo, pATI)) 639 return FALSE; 640 641 ATIClaimBusSlot(pGDev->active, pATI); 642 643#ifndef AVOID_CPIO 644 645#ifdef TV_OUT 646 647 pATI->pVBE = NULL; 648 pATI->pInt10 = NULL; 649 650#endif /* TV_OUT */ 651 652 /* 653 * If there is an ix86-style BIOS, ensure its initialisation entry point 654 * has been executed, and retrieve DDC and VBE information from it. 655 */ 656 if (!(pInt10Module = xf86LoadSubModule(pScreenInfo, "int10"))) 657 { 658 xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING, 659 "Unable to load int10 module.\n"); 660 } 661 else if (!(pInt10Info = xf86InitInt10(pATI->iEntity))) 662 { 663 xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING, 664 "Unable to initialise int10 interface.\n"); 665 } 666 else 667 { 668 if (!(pDDCModule = xf86LoadSubModule(pScreenInfo, "ddc"))) 669 { 670 xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING, 671 "Unable to load ddc module.\n"); 672 } 673 else 674 if (!(pVBEModule = xf86LoadSubModule(pScreenInfo, "vbe"))) 675 { 676 xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING, 677 "Unable to load vbe module.\n"); 678 } 679 else 680 { 681 if ((pVBE = VBEInit(pInt10Info, pATI->iEntity))) 682 { 683 ConfiguredMonitor = vbeDoEDID(pVBE, pDDCModule); 684 } 685 } 686 687 if (!(flags & PROBE_DETECT)) 688 { 689 /* Validate, then make a private copy of, the initialised BIOS */ 690 CARD8 *pBIOS = xf86int10Addr(pInt10Info, pInt10Info->BIOSseg << 4); 691 692 if ((pBIOS[0] != 0x55U) || (pBIOS[1] != 0xAAU) || !pBIOS[2]) 693 { 694 xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING, 695 "Unable to correctly retrieve adapter BIOS.\n"); 696 } 697 else 698 { 699 BIOSSize = pBIOS[2] << 9; 700 if (BIOSSize > BIOS_SIZE) 701 BIOSSize = BIOS_SIZE; 702 (void)memcpy(BIOS, pBIOS, BIOSSize); 703 } 704 } 705 } 706 707#ifndef TV_OUT 708 /* De-activate VBE */ 709 vbeFree(pVBE); 710 xf86UnloadSubModule(pVBEModule); 711 712 /* De-activate int10 */ 713 xf86FreeInt10(pInt10Info); 714 xf86UnloadSubModule(pInt10Module); 715#else 716 pATI->pInt10 = pInt10Info; 717 pATI->pVBE = pVBE; 718 pVBE = NULL; 719 pInt10Info = NULL; 720#endif /* TV_OUT */ 721 722 if (ConfiguredMonitor && !(flags & PROBE_DETECT)) 723 { 724 xf86PrintEDID(ConfiguredMonitor); 725 xf86SetDDCproperties(pScreenInfo, ConfiguredMonitor); 726 } 727 728 /* DDC module is no longer needed at this point */ 729 xf86UnloadSubModule(pDDCModule); 730 731#endif /* AVOID_CPIO */ 732 733 if (flags & PROBE_DETECT) 734 { 735 return TRUE; 736 } 737 738#ifndef AVOID_CPIO 739 740 /* I/O bases might no longer be valid after BIOS initialisation */ 741 { 742 if (pATI->CPIODecoding == BLOCK_IO) 743 pATI->CPIOBase = PCI_REGION_BASE(pVideo, 1, REGION_IO); 744 745 pATI->MMIOInLinear = FALSE; 746 747 /* Set MMIO address from PCI configuration space, if available */ 748 if ((pATI->Block0Base = PCI_REGION_BASE(pVideo, 2, REGION_MEM))) 749 { 750 pATI->Block0Base += 0x0400U; 751 } 752 } 753 754#endif /* AVOID_CPIO */ 755 756#ifdef AVOID_CPIO 757 758 pScreenInfo->racMemFlags = 759 RAC_FB | RAC_COLORMAP | RAC_VIEWPORT | RAC_CURSOR; 760 761#else /* AVOID_CPIO */ 762 763 pScreenInfo->racIoFlags = 764 RAC_FB | RAC_COLORMAP | RAC_VIEWPORT | RAC_CURSOR; 765 pScreenInfo->racMemFlags = RAC_FB | RAC_CURSOR; 766 767#endif /* AVOID_CPIO */ 768 769 /* Finish private area initialisation */ 770 pATI->nFIFOEntries = 16; /* For now */ 771 772 /* Finish probing the adapter */ 773 { 774 /* 775 * For MMIO register access, the MMIO address is computed when probing 776 * and there are no BIOS calls. This mapping should always succeed. 777 * 778 * For CPIO register access, the MMIO address is computed above in the 779 * presence of an auxiliary aperture. Otherwise, it is set to zero and 780 * gets computed when we read the linear aperture configuration. This 781 * mapping is either irrelevant or a no-op. 782 */ 783 if (!ATIMapApertures(pScreenInfo->scrnIndex, pATI)) 784 return FALSE; 785 786#ifdef AVOID_CPIO 787 788 if (!pATI->pBlock[0]) 789 { 790 xf86DrvMsg(pScreenInfo->scrnIndex, X_ERROR, 791 "Unable to mmap() adapter registers.\n"); 792 return FALSE; 793 } 794 795#endif /* AVOID_CPIO */ 796 797 /* 798 * Verify register access by comparing against the CONFIG_CHIP_ID 799 * value saved by adapter detection. 800 */ 801 if (pATI->config_chip_id != inr(CONFIG_CHIP_ID)) 802 { 803 xf86DrvMsg(pScreenInfo->scrnIndex, X_ERROR, 804 "Adapter registers not mapped correctly.\n"); 805 ATIUnmapApertures(pScreenInfo->scrnIndex, pATI); 806 return FALSE; 807 } 808 809 pATIHW->crtc_gen_cntl = inr(CRTC_GEN_CNTL); 810 if (!(pATIHW->crtc_gen_cntl & CRTC_EN) && 811 (pATI->Chip >= ATI_CHIP_264CT)) 812 { 813 xf86DrvMsg(pScreenInfo->scrnIndex, X_ERROR, 814 "Adapter has not been initialised.\n"); 815 goto bail_locked; 816 } 817 818#ifdef AVOID_CPIO 819 820 if (!(pATIHW->crtc_gen_cntl & CRTC_EXT_DISP_EN)) 821 { 822 xf86DrvMsg(pScreenInfo->scrnIndex, X_ERROR, 823 "Adapters found to be in VGA mode on server entry are not" 824 " supported by the MMIO-only version of this driver.\n"); 825 goto bail_locked; 826 } 827 828#endif /* AVOID_CPIO */ 829 830 pATIHW->mem_cntl = inr(MEM_CNTL); 831 if (pATI->Chip < ATI_CHIP_264VTB) 832 { 833 IOValue = GetBits(pATIHW->mem_cntl, CTL_MEM_SIZE); 834 pATI->VideoRAM = videoRamSizes[IOValue]; 835 } 836 else 837 { 838 pATI->nFIFOEntries = /* Don't care */ 839 (unsigned int)(-1) >> 1; 840 841 IOValue = GetBits(pATIHW->mem_cntl, CTL_MEM_SIZEB); 842 if (IOValue < 8) 843 pATI->VideoRAM = (IOValue + 1) * 512; 844 else if (IOValue < 12) 845 pATI->VideoRAM = (IOValue - 3) * 1024; 846 else 847 pATI->VideoRAM = (IOValue - 7) * 2048; 848 } 849 850 IOValue = inr(CONFIG_STATUS64_0); 851 if (pATI->Chip >= ATI_CHIP_264CT) 852 { 853 pATI->MemoryType = GetBits(IOValue, CFG_MEM_TYPE_T); 854 } 855 else 856 { 857 pATI->MemoryType = GetBits(IOValue, CFG_MEM_TYPE); 858 } 859 860 pATI->LCDPanelID = -1; 861 862 if (pATI->Chip >= ATI_CHIP_264CT) 863 { 864 /* Get LCD panel id */ 865 if (pATI->Chip == ATI_CHIP_264LT) 866 { 867 pATI->LCDPanelID = GetBits(IOValue, CFG_PANEL_ID); 868 869 pATIHW->horz_stretching = inr(HORZ_STRETCHING); 870 pATIHW->vert_stretching = inr(VERT_STRETCHING); 871 pATIHW->lcd_gen_ctrl = inr(LCD_GEN_CTRL); 872 } 873 else if ((pATI->Chip == ATI_CHIP_264LTPRO) || 874 (pATI->Chip == ATI_CHIP_264XL) || 875 (pATI->Chip == ATI_CHIP_MOBILITY)) 876 { 877 pATI->LCDPanelID = GetBits(IOValue, CFG_PANEL_ID); 878 879 pATIHW->lcd_index = inr(LCD_INDEX); 880 pATIHW->horz_stretching = 881 ATIMach64GetLCDReg(LCD_HORZ_STRETCHING); 882 pATI->LCDHorizontal = 883 GetBits(pATIHW->horz_stretching, HORZ_PANEL_SIZE); 884 if (pATI->LCDHorizontal) 885 { 886 if (pATI->LCDHorizontal == MaxBits(HORZ_PANEL_SIZE)) 887 pATI->LCDHorizontal = 0; 888 else 889 pATI->LCDHorizontal = 890 (pATI->LCDHorizontal + 1) << 3; 891 } 892 pATIHW->ext_vert_stretch = 893 ATIMach64GetLCDReg(LCD_EXT_VERT_STRETCH); 894 pATI->LCDVertical = 895 GetBits(pATIHW->ext_vert_stretch, VERT_PANEL_SIZE); 896 if (pATI->LCDVertical) 897 { 898 if (pATI->LCDVertical == MaxBits(VERT_PANEL_SIZE)) 899 pATI->LCDVertical = 0; 900 else 901 pATI->LCDVertical++; 902 } 903 pATIHW->vert_stretching = 904 ATIMach64GetLCDReg(LCD_VERT_STRETCHING); 905 pATIHW->lcd_gen_ctrl = ATIMach64GetLCDReg(LCD_GEN_CNTL); 906 outr(LCD_INDEX, pATIHW->lcd_index); 907 } 908 909 /* 910 * Don't bother with panel support if it hasn't been previously 911 * enabled. 912 */ 913 if ((pATI->LCDPanelID >= 0) && 914 !(pATIHW->horz_stretching & HORZ_STRETCH_EN) && 915 !(pATIHW->vert_stretching & VERT_STRETCH_EN) && 916 !(pATIHW->lcd_gen_ctrl & LCD_ON)) 917 { 918 /* 919 * At this point, if an XL or Mobility BIOS hasn't set 920 * panel dimensions, then there is no panel. Otherwise, 921 * keep any panel disabled to allow for modes greater than 922 * the panel's dimensions. 923 */ 924 if ((pATI->Chip >= ATI_CHIP_264XL) && 925 (!pATI->LCDHorizontal || !pATI->LCDVertical)) 926 pATI->LCDPanelID = -1; 927 else 928 pATI->OptionPanelDisplay = FALSE; 929 } 930 } 931 932 /* Get DAC type */ 933 pATI->DAC = GetBits(inr(DAC_CNTL), DAC_TYPE); 934 935 if (pATI->Chip < ATI_CHIP_264CT) 936 { 937 /* Factor in what the BIOS says the DAC is */ 938 pATI->DAC = ATI_DAC(pATI->DAC, 939 GetBits(inr(SCRATCH_REG1), BIOS_INIT_DAC_SUBTYPE)); 940 } 941 942 /* 943 * RAMDAC types 0 & 1 for Mach64's are different than those for 944 * Mach32's. 945 */ 946 if (pATI->DAC < ATI_DAC_ATI68875) 947 pATI->DAC += ATI_DAC_INTERNAL; 948 } 949 950 { 951 ROMTable = BIOSWord(0x48U); 952 if ((ROMTable < 0x0002U) || 953 (BIOSWord(ROMTable - 0x02U) < 0x0012U) || 954 ((ROMTable + BIOSWord(ROMTable - 0x02U)) > BIOSSize)) 955 ROMTable = 0; 956 957 if (ROMTable > 0) 958 { 959 ClockTable = BIOSWord(ROMTable + 0x10U); 960 if ((ClockTable + 0x20U) > BIOSSize) 961 ClockTable = 0; 962 963 if (BIOSWord(ROMTable - 0x02U) >= 0x0048U) 964 { 965 VideoTable = BIOSWord(ROMTable + 0x46U); 966 if ((VideoTable < 0x08U) || 967 (BIOSByte(VideoTable - 0x01U) < 0x08U) || 968 (BIOSByte(VideoTable - 0x02U) > 0x01U) || 969 ((VideoTable + BIOSByte(VideoTable - 0x01U)) > BIOSSize)) 970 VideoTable = 0; 971 } 972 973 if (BIOSWord(ROMTable - 0x02U) >= 0x004AU) 974 { 975 HardwareTable = BIOSWord(ROMTable + 0x48U); 976 if (((HardwareTable + 0x08U) > BIOSSize) || 977 (memcmp(BIOS + HardwareTable, "$ATI", 4) != 0)) 978 HardwareTable = 0; 979 } 980 } 981 982 ati_bios_clock(pScreenInfo, pATI, BIOS, ClockTable, pGDev); 983 984 ati_bios_mmedia(pScreenInfo, pATI, BIOS, VideoTable, HardwareTable); 985 986 if (pATI->LCDPanelID >= 0) 987 { 988 LCDTable = BIOSWord(0x78U); 989 if ((LCDTable + BIOSByte(LCDTable + 5)) > BIOSSize) 990 LCDTable = 0; 991 992 ati_bios_panel_info(pScreenInfo, pATI, BIOS, BIOSSize, LCDTable); 993 } 994 995 xf86DrvMsgVerb(pScreenInfo->scrnIndex, X_INFO, 3, 996 "BIOS Data: BIOSSize=0x%04X, ROMTable=0x%04X.\n", 997 BIOSSize, ROMTable); 998 xf86DrvMsgVerb(pScreenInfo->scrnIndex, X_INFO, 3, 999 "BIOS Data: ClockTable=0x%04X, FrequencyTable=0x%04X.\n", 1000 ClockTable, FrequencyTable); 1001 xf86DrvMsgVerb(pScreenInfo->scrnIndex, X_INFO, 3, 1002 "BIOS Data: LCDTable=0x%04X.\n", 1003 LCDTable); 1004 xf86DrvMsgVerb(pScreenInfo->scrnIndex, X_INFO, 3, 1005 "BIOS Data: VideoTable=0x%04X, HardwareTable=0x%04X.\n", 1006 VideoTable, HardwareTable); 1007 xf86DrvMsgVerb(pScreenInfo->scrnIndex, X_INFO, 3, 1008 "BIOS Data: I2CType=0x%02X, Tuner=0x%02X, Decoder=0x%02X," 1009 " Audio=0x%02X.\n", 1010 pATI->I2CType, pATI->Tuner, pATI->Decoder, pATI->Audio); 1011 } 1012 1013 ATIUnlock(pATI); /* Unlock registers */ 1014 1015 /* Report what was found */ 1016 xf86DrvMsg(pScreenInfo->scrnIndex, X_PROBED, 1017 "%s graphics controller detected.\n", 1018 xf86TokenToString(Mach64Chipsets, pATI->Chip)); 1019 1020 { 1021 Message = Buffer + snprintf(Buffer, SizeOf(Buffer), "Chip type %04X", 1022 pATI->ChipType); 1023 if (!(pATI->ChipType & ~(CHIP_CODE_0 | CHIP_CODE_1))) 1024 Message += snprintf(Message, Buffer + SizeOf(Buffer) - Message, 1025 " (%c%c)", 1026 GetBits(pATI->ChipType, CHIP_CODE_1) + 0x41U, 1027 GetBits(pATI->ChipType, CHIP_CODE_0) + 0x41U); 1028 else if ((pATI->ChipType & 0x4040U) == 0x4040U) 1029 Message += snprintf(Message, Buffer + SizeOf(Buffer) - Message, 1030 " \"%c%c\"", 1031 GetByte(pATI->ChipType, 1), GetByte(pATI->ChipType, 0)); 1032 if ((pATI->Chip >= ATI_CHIP_264CT) && (pATI->Chip != ATI_CHIP_Mach64)) 1033 Message += snprintf(Message, Buffer + SizeOf(Buffer) - Message, 1034 ", version %d, foundry %s", 1035 pATI->ChipVersion, ATIFoundryNames[pATI->ChipFoundry]); 1036 xf86DrvMsg(pScreenInfo->scrnIndex, X_PROBED, 1037 "%s, class %d, revision 0x%02X.\n", 1038 Buffer, pATI->ChipClass, pATI->ChipRevision); 1039 } 1040 1041 { 1042 Message = Buffer + snprintf(Buffer, SizeOf(Buffer), 1043 "%s bus interface detected", ATIBusNames[pATI->BusType]); 1044 1045#ifndef AVOID_CPIO 1046 1047 { 1048 Message += snprintf(Message, Buffer + SizeOf(Buffer) - Message, 1049 "; %s I/O base is 0x%04lX", 1050 (pATI->CPIODecoding == SPARSE_IO) ? "sparse" : "block", 1051 pATI->CPIOBase); 1052 } 1053 1054#endif /* AVOID_CPIO */ 1055 1056 xf86DrvMsg(pScreenInfo->scrnIndex, X_PROBED, "%s.\n", Buffer); 1057 } 1058 1059#ifndef AVOID_CPIO 1060 1061 if (pATI->CPIO_VGAWonder) 1062 xf86DrvMsg(pScreenInfo->scrnIndex, X_PROBED, 1063 "VGA Wonder registers at I/O port 0x%04lX.\n", 1064 pATI->CPIO_VGAWonder); 1065 1066#endif /* AVOID_CPIO */ 1067 1068 xf86DrvMsg(pScreenInfo->scrnIndex, X_PROBED, 1069 "ATI Mach64 adapter detected.\n"); 1070 1071 if (pATI->Chip >= ATI_CHIP_264GT) 1072 xf86DrvMsg(pScreenInfo->scrnIndex, X_NOTICE, 1073 "For information on using the multimedia capabilities\n\tof this" 1074 " adapter, please see http://gatos.sf.net.\n"); 1075 1076 if ((pATI->DAC & ~0x0FU) == ATI_DAC_INTERNAL) 1077 { 1078 xf86DrvMsg(pScreenInfo->scrnIndex, X_PROBED, 1079 "Internal RAMDAC (subtype %d) detected.\n", pATI->DAC & 0x0FU); 1080 } 1081 else 1082 { 1083 const SymTabRec *DAC; 1084 1085 for (DAC = ATIDACDescriptors; ; DAC++) 1086 { 1087 if (pATI->DAC == DAC->token) 1088 { 1089 xf86DrvMsg(pScreenInfo->scrnIndex, X_PROBED, 1090 "%s RAMDAC detected.\n", DAC->name); 1091 break; 1092 } 1093 1094 if (pATI->DAC < DAC->token) 1095 { 1096 xf86DrvMsgVerb(pScreenInfo->scrnIndex, X_WARNING, 0, 1097 "Unknown RAMDAC type 0x%02X detected.\n", pATI->DAC); 1098 break; 1099 } 1100 } 1101 } 1102 1103 if (!xf86LinearVidMem()) 1104 { 1105 xf86DrvMsg(pScreenInfo->scrnIndex, X_ERROR, 1106 "A linear aperture is not available.\n"); 1107 goto bail; 1108 } 1109 1110 /* 1111 * Set colour weights. 1112 */ 1113 1114 if (pATI->Chip < ATI_CHIP_264CT) 1115 pScreenInfo->rgbBits = 6; 1116 else 1117 pScreenInfo->rgbBits = 8; 1118 pATI->rgbBits = pScreenInfo->rgbBits; 1119 if (!xf86SetWeight(pScreenInfo, defaultWeight, defaultWeight)) 1120 goto bail; 1121 1122 if ((pScreenInfo->depth > 8) && 1123 ((pScreenInfo->weight.red != pScreenInfo->weight.blue) || 1124 (pScreenInfo->weight.red != (CARD32)(pScreenInfo->depth / 3)) || 1125 ((CARD32)pScreenInfo->depth != (pScreenInfo->weight.red + 1126 pScreenInfo->weight.green + 1127 pScreenInfo->weight.blue)))) 1128 { 1129 xf86DrvMsg(pScreenInfo->scrnIndex, X_ERROR, 1130 "Driver does not support weight %d%d%d for depth %d.\n", 1131 (int)pScreenInfo->weight.red, (int)pScreenInfo->weight.green, 1132 (int)pScreenInfo->weight.blue, pScreenInfo->depth); 1133 goto bail; 1134 } 1135 1136 /* 1137 * Set default visual. 1138 */ 1139 1140 if (!xf86SetDefaultVisual(pScreenInfo, -1)) 1141 goto bail; 1142 1143 if ((pScreenInfo->depth > 8) && 1144 (((pScreenInfo->defaultVisual | DynamicClass) != DirectColor) || 1145 ((pScreenInfo->defaultVisual == DirectColor) && 1146 (pATI->DAC == ATI_DAC_INTERNAL)))) 1147 { 1148 xf86DrvMsg(pScreenInfo->scrnIndex, X_ERROR, 1149 "Driver does not support default visual %s for depth %d.\n", 1150 xf86GetVisualName(pScreenInfo->defaultVisual), 1151 pScreenInfo->depth); 1152 goto bail; 1153 } 1154 1155 /* 1156 * Set colour gamma. 1157 */ 1158 1159 if (!xf86SetGamma(pScreenInfo, defaultGamma)) 1160 goto bail; 1161 1162 pATI->depth = pScreenInfo->depth; 1163 pATI->bitsPerPixel = pScreenInfo->bitsPerPixel; 1164 pATI->weight = pScreenInfo->weight; 1165 pATI->XModifier = pATI->bitsPerPixel / UnitOf(pATI->bitsPerPixel); 1166 1167 /* 1168 * Determine which CRT controller to use for video modes. 1169 */ 1170 1171 { 1172 pATI->NewHW.crtc = ATI_CRTC_MACH64; 1173 1174 xf86DrvMsg(pScreenInfo->scrnIndex, X_INFO, 1175 "Using Mach64 accelerator CRTC.\n"); 1176 1177#ifndef AVOID_CPIO 1178 1179 if (pATI->VGAAdapter) 1180 { 1181 /* 1182 * No need for VGA I/O resources during operating state (but they 1183 * are still decoded). 1184 */ 1185 pResources = 1186 xf86SetOperatingState(resVgaIo, pATI->iEntity, ResUnusedOpr); 1187 if (pResources) 1188 { 1189 xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING, 1190 "Logic error setting operating state for VGA I/O.\n"); 1191 xf86FreeResList(pResources); 1192 } 1193 1194 if (pATI->CPIO_VGAWonder) 1195 { 1196 pResources = xf86SetOperatingState(pATI->VGAWonderResources, 1197 pATI->iEntity, ResUnusedOpr); 1198 if (pResources) 1199 { 1200 xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING, 1201 "Logic error setting operating state for" 1202 " VGAWonder I/O.\n"); 1203 xf86FreeResList(pResources); 1204 } 1205 } 1206 } 1207 1208#endif /* AVOID_CPIO */ 1209 1210 } 1211 1212 /* 1213 * Decide between the CRT and the panel. 1214 */ 1215 if (pATI->LCDPanelID >= 0) 1216 { 1217 if (!pATI->OptionPanelDisplay) 1218 { 1219 xf86DrvMsg(pScreenInfo->scrnIndex, X_CONFIG, 1220 "Using CRT interface and disabling digital flat panel.\n"); 1221 } 1222 else 1223 { 1224 unsigned HDisplay, VDisplay; 1225 CARD8 ClockMask, PostMask; 1226 1227 /* 1228 * Determine porch data. This groks the mode on entry to extract 1229 * the width and position of its sync and blanking pulses, and 1230 * considers any overscan as part of the displayed area, given that 1231 * the overscan is also stretched. 1232 * 1233 * This also attempts to determine panel dimensions but cannot do 1234 * so for one that is "auto-stretched". 1235 */ 1236 1237 if (pATI->Chip == ATI_CHIP_264LT) 1238 { 1239 pATIHW->lcd_gen_ctrl = inr(LCD_GEN_CTRL); 1240 1241 /* Set up to read non-shadow registers */ 1242 if (pATIHW->lcd_gen_ctrl & SHADOW_RW_EN) 1243 outr(LCD_GEN_CTRL, pATIHW->lcd_gen_ctrl & ~SHADOW_RW_EN); 1244 } 1245 else /* if ((pATI->Chip == ATI_CHIP_264LTPRO) || 1246 (pATI->Chip == ATI_CHIP_264XL) || 1247 (pATI->Chip == ATI_CHIP_MOBILITY)) */ 1248 { 1249 pATIHW->lcd_index = inr(LCD_INDEX); 1250 pATIHW->config_panel = ATIMach64GetLCDReg(LCD_CONFIG_PANEL); 1251 pATIHW->lcd_gen_ctrl = ATIMach64GetLCDReg(LCD_GEN_CNTL); 1252 1253 /* Set up to read non-shadow registers */ 1254 if (pATIHW->lcd_gen_ctrl & SHADOW_RW_EN) 1255 ATIMach64PutLCDReg(LCD_GEN_CNTL, 1256 pATIHW->lcd_gen_ctrl & ~SHADOW_RW_EN); 1257 } 1258 1259#ifndef AVOID_CPIO 1260 1261 if (!(pATIHW->crtc_gen_cntl & CRTC_EXT_DISP_EN)) 1262 { 1263 unsigned HBlankStart, HSyncStart, HSyncEnd, HBlankEnd, HTotal; 1264 unsigned VBlankStart, VSyncStart, VSyncEnd, VBlankEnd, VTotal; 1265 1266 pATIHW->clock = (inb(R_GENMO) & 0x0CU) >> 2; 1267 1268 pATIHW->crt[2] = GetReg(CRTX(pATI->CPIO_VGABase), 0x02U); 1269 pATIHW->crt[3] = GetReg(CRTX(pATI->CPIO_VGABase), 0x03U); 1270 pATIHW->crt[5] = GetReg(CRTX(pATI->CPIO_VGABase), 0x05U); 1271 pATIHW->crt[7] = GetReg(CRTX(pATI->CPIO_VGABase), 0x07U); 1272 pATIHW->crt[9] = GetReg(CRTX(pATI->CPIO_VGABase), 0x09U); 1273 pATIHW->crt[21] = GetReg(CRTX(pATI->CPIO_VGABase), 0x15U); 1274 pATIHW->crt[22] = GetReg(CRTX(pATI->CPIO_VGABase), 0x16U); 1275 1276 pATIHW->crtc_h_total_disp = inr(CRTC_H_TOTAL_DISP); 1277 pATIHW->crtc_h_sync_strt_wid = inr(CRTC_H_SYNC_STRT_WID); 1278 pATIHW->crtc_v_total_disp = inr(CRTC_V_TOTAL_DISP); 1279 pATIHW->crtc_v_sync_strt_wid = inr(CRTC_V_SYNC_STRT_WID); 1280 1281 /* Switch to shadow registers */ 1282 if (pATI->Chip == ATI_CHIP_264LT) 1283 outr(LCD_GEN_CTRL, pATIHW->lcd_gen_ctrl | SHADOW_RW_EN); 1284 else /* if ((pATI->Chip == ATI_CHIP_264LTPRO) || 1285 (pATI->Chip == ATI_CHIP_264XL) || 1286 (pATI->Chip == ATI_CHIP_MOBILITY)) */ 1287 ATIMach64PutLCDReg(LCD_GEN_CNTL, 1288 pATIHW->lcd_gen_ctrl | SHADOW_RW_EN); 1289 1290 pATIHW->shadow_vga[2] = 1291 GetReg(CRTX(pATI->CPIO_VGABase), 0x02U); 1292 pATIHW->shadow_vga[3] = 1293 GetReg(CRTX(pATI->CPIO_VGABase), 0x03U); 1294 pATIHW->shadow_vga[5] = 1295 GetReg(CRTX(pATI->CPIO_VGABase), 0x05U); 1296 pATIHW->shadow_vga[7] = 1297 GetReg(CRTX(pATI->CPIO_VGABase), 0x07U); 1298 pATIHW->shadow_vga[9] = 1299 GetReg(CRTX(pATI->CPIO_VGABase), 0x09U); 1300 pATIHW->shadow_vga[21] = 1301 GetReg(CRTX(pATI->CPIO_VGABase), 0x15U); 1302 pATIHW->shadow_vga[22] = 1303 GetReg(CRTX(pATI->CPIO_VGABase), 0x16U); 1304 1305 pATIHW->shadow_h_total_disp = inr(CRTC_H_TOTAL_DISP); 1306 pATIHW->shadow_h_sync_strt_wid = inr(CRTC_H_SYNC_STRT_WID); 1307 pATIHW->shadow_v_total_disp = inr(CRTC_V_TOTAL_DISP); 1308 pATIHW->shadow_v_sync_strt_wid = inr(CRTC_V_SYNC_STRT_WID); 1309 1310 /* 1311 * HSyncStart and HSyncEnd should equal their shadow 1312 * counterparts. Otherwise, due to a chip bug, the panel might 1313 * not sync, regardless of which register set is used to drive 1314 * the panel. There are certain combinations of register 1315 * values where the panel does in fact sync, but it remains 1316 * impossible to accurately determine the horizontal sync pulse 1317 * timing actually seen by the panel. 1318 * 1319 * Note that this hardware bug does not affect the CRT output. 1320 */ 1321 if (((pATIHW->crtc_h_sync_strt_wid ^ 1322 pATIHW->shadow_h_sync_strt_wid) & 1323 (CRTC_H_SYNC_STRT | CRTC_H_SYNC_STRT_HI | 1324 CRTC_H_SYNC_WID))) 1325 { 1326 xf86DrvMsgVerb(pScreenInfo->scrnIndex, X_NOTICE, 0, 1327 "Invalid horizontal sync pulse timing detected in mode" 1328 " on server entry.\n"); 1329 1330 /* Don't trust input timing */ 1331 pATI->OptionLCDSync = TRUE; 1332 ModeType = 0; 1333 } 1334 1335 /* Merge in shadow registers as appropriate */ 1336 if (pATIHW->lcd_gen_ctrl & SHADOW_EN) 1337 { 1338 pATIHW->crt[2] = pATIHW->shadow_vga[2]; 1339 pATIHW->crt[3] = pATIHW->shadow_vga[3]; 1340 pATIHW->crt[5] = pATIHW->shadow_vga[5]; 1341 1342 /* XXX Does this apply to VGA? If so, what about the LT? */ 1343 if ((pATI->Chip < ATI_CHIP_264LTPRO) || 1344 !(pATIHW->config_panel & DONT_SHADOW_HEND)) 1345 { 1346 pATIHW->crtc_h_total_disp &= ~CRTC_H_DISP; 1347 pATIHW->crtc_h_total_disp |= 1348 pATIHW->shadow_h_total_disp & CRTC_H_DISP; 1349 } 1350 1351 pATIHW->crtc_h_total_disp &= ~CRTC_H_TOTAL; 1352 pATIHW->crtc_h_total_disp |= 1353 pATIHW->shadow_h_total_disp & CRTC_H_TOTAL; 1354 pATIHW->crtc_h_sync_strt_wid = 1355 pATIHW->shadow_h_sync_strt_wid; 1356 1357 /* XXX Does this apply to VGA? */ 1358 if (pATIHW->lcd_gen_ctrl & USE_SHADOWED_VEND) 1359 { 1360 pATIHW->crtc_v_total_disp &= ~CRTC_V_DISP; 1361 pATIHW->crtc_v_total_disp |= 1362 pATIHW->shadow_v_total_disp & CRTC_V_DISP; 1363 } 1364 1365 if (!(pATIHW->lcd_gen_ctrl & DONT_SHADOW_VPAR)) 1366 { 1367 pATIHW->crt[7] = pATIHW->shadow_vga[7]; 1368 pATIHW->crt[9] = pATIHW->shadow_vga[9]; 1369 pATIHW->crt[21] = pATIHW->shadow_vga[21]; 1370 pATIHW->crt[22] = pATIHW->shadow_vga[22]; 1371 1372 pATIHW->crtc_v_total_disp &= ~CRTC_V_TOTAL; 1373 pATIHW->crtc_v_total_disp |= 1374 pATIHW->shadow_v_total_disp & CRTC_V_TOTAL; 1375 } 1376 } 1377 1378 if (!(pATIHW->lcd_gen_ctrl & DONT_SHADOW_VPAR)) 1379 pATIHW->crtc_v_sync_strt_wid = 1380 pATIHW->shadow_v_sync_strt_wid; 1381 1382 /* 1383 * Decipher input timing. This is complicated by the fact that 1384 * the full width of all timing parameters, except for the 1385 * blanking pulses, is only available through the accelerator 1386 * registers, not the VGA ones. Blanking pulse boundaries must 1387 * then be interpolated. 1388 * 1389 * Note that, in VGA mode, the accelerator's sync width fields 1390 * are actually end positions, not widths. 1391 */ 1392 HDisplay = GetBits(pATIHW->crtc_h_total_disp, CRTC_H_DISP); 1393 HSyncStart = 1394 (GetBits(pATIHW->crtc_h_sync_strt_wid, 1395 CRTC_H_SYNC_STRT_HI) * 1396 (MaxBits(CRTC_H_SYNC_STRT) + 1)) | 1397 GetBits(pATIHW->crtc_h_sync_strt_wid, CRTC_H_SYNC_STRT); 1398 HSyncEnd = (HSyncStart & ~MaxBits(CRTC_H_SYNC_WID)) | 1399 GetBits(pATIHW->crtc_h_sync_strt_wid, CRTC_H_SYNC_WID); 1400 if (HSyncStart >= HSyncEnd) 1401 HSyncEnd += MaxBits(CRTC_H_SYNC_WID) + 1; 1402 HTotal = GetBits(pATIHW->crtc_h_total_disp, CRTC_H_TOTAL); 1403 1404 HBlankStart = (HDisplay & ~0xFFU) | pATIHW->crt[2]; 1405 if (HDisplay > HBlankStart) 1406 HBlankStart += 0x0100U; 1407 HBlankEnd = (HSyncEnd & ~0x3FU) | 1408 ((pATIHW->crt[5] >> 2) & 0x20U) | 1409 (pATIHW->crt[3] & 0x1FU); 1410 if (HSyncEnd > (HBlankEnd + 1)) 1411 HBlankEnd += 0x40U; 1412 1413 VDisplay = GetBits(pATIHW->crtc_v_total_disp, CRTC_V_DISP); 1414 VSyncStart = 1415 GetBits(pATIHW->crtc_v_sync_strt_wid, CRTC_V_SYNC_STRT); 1416 VSyncEnd = (VSyncStart & ~MaxBits(CRTC_V_SYNC_END_VGA)) | 1417 GetBits(pATIHW->crtc_v_sync_strt_wid, CRTC_V_SYNC_END_VGA); 1418 if (VSyncStart > VSyncEnd) 1419 VSyncEnd += MaxBits(CRTC_V_SYNC_END_VGA) + 1; 1420 VTotal = GetBits(pATIHW->crtc_v_total_disp, CRTC_V_TOTAL); 1421 1422 VBlankStart = (VDisplay & ~0x03FFU) | 1423 ((pATIHW->crt[9] << 4) & 0x0200U) | 1424 ((pATIHW->crt[7] << 5) & 0x0100U) | pATIHW->crt[21]; 1425 if (VDisplay > VBlankStart) 1426 VBlankStart += 0x0400U; 1427 VBlankEnd = (VSyncEnd & ~0x00FFU) | pATIHW->crt[22]; 1428 if (VSyncEnd > (VBlankEnd + 1)) 1429 VBlankEnd += 0x0100U; 1430 1431 pATI->LCDHBlankWidth = HBlankEnd - HBlankStart; 1432 pATI->LCDHSyncStart = HSyncStart - HBlankStart; 1433 pATI->LCDHSyncWidth = HSyncEnd - HSyncStart; 1434 1435 pATI->LCDVBlankWidth = VBlankEnd - VBlankStart; 1436 pATI->LCDVSyncStart = VSyncStart - VBlankStart; 1437 pATI->LCDVSyncWidth = VSyncEnd - VSyncStart; 1438 1439 HDisplay = HTotal + 5 - pATI->LCDHBlankWidth; 1440 VDisplay = VTotal + 2 - pATI->LCDVBlankWidth; 1441 } 1442 else 1443 1444#endif /* AVOID_CPIO */ 1445 1446 { 1447 pATIHW->clock = inr(CLOCK_CNTL) & 0x03U; 1448 1449 pATIHW->crtc_h_total_disp = inr(CRTC_H_TOTAL_DISP); 1450 pATIHW->crtc_h_sync_strt_wid = inr(CRTC_H_SYNC_STRT_WID); 1451 pATIHW->crtc_v_total_disp = inr(CRTC_V_TOTAL_DISP); 1452 pATIHW->crtc_v_sync_strt_wid = inr(CRTC_V_SYNC_STRT_WID); 1453 pATIHW->ovr_wid_left_right = inr(OVR_WID_LEFT_RIGHT); 1454 pATIHW->ovr_wid_top_bottom = inr(OVR_WID_TOP_BOTTOM); 1455 1456 /* Switch to shadow registers */ 1457 if (pATI->Chip == ATI_CHIP_264LT) 1458 outr(LCD_GEN_CTRL, pATIHW->lcd_gen_ctrl | SHADOW_RW_EN); 1459 else /* if ((pATI->Chip == ATI_CHIP_264LTPRO) || 1460 (pATI->Chip == ATI_CHIP_264XL) || 1461 (pATI->Chip == ATI_CHIP_MOBILITY)) */ 1462 ATIMach64PutLCDReg(LCD_GEN_CNTL, 1463 pATIHW->lcd_gen_ctrl | SHADOW_RW_EN); 1464 1465 /* Oddly enough, there are no shadow overscan registers */ 1466 pATIHW->shadow_h_total_disp = inr(CRTC_H_TOTAL_DISP); 1467 pATIHW->shadow_h_sync_strt_wid = inr(CRTC_H_SYNC_STRT_WID); 1468 pATIHW->shadow_v_total_disp = inr(CRTC_V_TOTAL_DISP); 1469 pATIHW->shadow_v_sync_strt_wid = inr(CRTC_V_SYNC_STRT_WID); 1470 1471 /* 1472 * HSyncStart and HSyncEnd should equal their shadow 1473 * counterparts. Otherwise, due to a chip bug, the panel might 1474 * not sync, regardless of which register set is used to drive 1475 * the panel. There are certain combinations of register 1476 * values where the panel does in fact sync, but it remains 1477 * impossible to accurately determine the horizontal sync pulse 1478 * timing actually seen by the panel. 1479 * 1480 * Note that this hardware bug does not affect the CRT output. 1481 */ 1482 if (((pATIHW->crtc_h_sync_strt_wid ^ 1483 pATIHW->shadow_h_sync_strt_wid) & 1484 (CRTC_H_SYNC_STRT | CRTC_H_SYNC_STRT_HI | 1485 CRTC_H_SYNC_WID))) 1486 { 1487 xf86DrvMsgVerb(pScreenInfo->scrnIndex, X_NOTICE, 0, 1488 "Invalid horizontal sync pulse timing detected in mode" 1489 " on server entry.\n"); 1490 1491 /* Don't trust input timing */ 1492 pATI->OptionLCDSync = TRUE; 1493 ModeType = 0; 1494 } 1495 1496 /* Merge in shadow registers as appropriate */ 1497 if (pATIHW->lcd_gen_ctrl & SHADOW_EN) 1498 { 1499 /* XXX What about the LT? */ 1500 if ((pATI->Chip < ATI_CHIP_264LTPRO) || 1501 !(pATIHW->config_panel & DONT_SHADOW_HEND)) 1502 { 1503 pATIHW->crtc_h_total_disp &= ~CRTC_H_DISP; 1504 pATIHW->crtc_h_total_disp |= 1505 pATIHW->shadow_h_total_disp & CRTC_H_DISP; 1506 } 1507 1508 pATIHW->crtc_h_total_disp &= ~CRTC_H_TOTAL; 1509 pATIHW->crtc_h_total_disp |= 1510 pATIHW->shadow_h_total_disp & CRTC_H_TOTAL; 1511 pATIHW->crtc_h_sync_strt_wid = 1512 pATIHW->shadow_h_sync_strt_wid; 1513 1514 if (pATIHW->lcd_gen_ctrl & USE_SHADOWED_VEND) 1515 { 1516 pATIHW->crtc_v_total_disp &= ~CRTC_V_DISP; 1517 pATIHW->crtc_v_total_disp |= 1518 pATIHW->shadow_v_total_disp & CRTC_V_DISP; 1519 } 1520 1521 if (!(pATIHW->lcd_gen_ctrl & DONT_SHADOW_VPAR)) 1522 { 1523 pATIHW->crtc_v_total_disp &= ~CRTC_V_TOTAL; 1524 pATIHW->crtc_v_total_disp |= 1525 pATIHW->shadow_v_total_disp & CRTC_V_TOTAL; 1526 } 1527 } 1528 1529 if (!(pATIHW->lcd_gen_ctrl & DONT_SHADOW_VPAR)) 1530 pATIHW->crtc_v_sync_strt_wid = 1531 pATIHW->shadow_v_sync_strt_wid; 1532 1533 /* Decipher input timing */ 1534 HDisplay = GetBits(pATIHW->crtc_h_total_disp, CRTC_H_DISP) + 1535 GetBits(pATIHW->ovr_wid_left_right, OVR_WID_LEFT) + 1536 GetBits(pATIHW->ovr_wid_left_right, OVR_WID_RIGHT); 1537 VDisplay = GetBits(pATIHW->crtc_v_total_disp, CRTC_V_DISP) + 1538 GetBits(pATIHW->ovr_wid_top_bottom, OVR_WID_TOP) + 1539 GetBits(pATIHW->ovr_wid_top_bottom, OVR_WID_BOTTOM); 1540 1541 pATI->LCDHSyncStart = 1542 (GetBits(pATIHW->crtc_h_sync_strt_wid, 1543 CRTC_H_SYNC_STRT_HI) * 1544 (MaxBits(CRTC_H_SYNC_STRT) + 1)) + 1545 GetBits(pATIHW->crtc_h_sync_strt_wid, CRTC_H_SYNC_STRT) - 1546 HDisplay; 1547 pATI->LCDHSyncWidth = 1548 GetBits(pATIHW->crtc_h_sync_strt_wid, CRTC_H_SYNC_WID); 1549 pATI->LCDHBlankWidth = 1550 GetBits(pATIHW->crtc_h_total_disp, CRTC_H_TOTAL) - 1551 HDisplay; 1552 pATI->LCDVSyncStart = 1553 GetBits(pATIHW->crtc_v_sync_strt_wid, CRTC_V_SYNC_STRT) - 1554 VDisplay; 1555 pATI->LCDVSyncWidth = 1556 GetBits(pATIHW->crtc_v_sync_strt_wid, CRTC_V_SYNC_WID); 1557 pATI->LCDVBlankWidth = 1558 GetBits(pATIHW->crtc_v_total_disp, CRTC_V_TOTAL) - 1559 VDisplay; 1560 1561 HDisplay++; 1562 VDisplay++; 1563 } 1564 1565 /* Restore LCD registers */ 1566 if (pATI->Chip == ATI_CHIP_264LT) 1567 { 1568 outr(LCD_GEN_CTRL, pATIHW->lcd_gen_ctrl); 1569 } 1570 else /* if ((pATI->Chip == ATI_CHIP_264LTPRO) || 1571 (pATI->Chip == ATI_CHIP_264XL) || 1572 (pATI->Chip == ATI_CHIP_MOBILITY)) */ 1573 { 1574 ATIMach64PutLCDReg(LCD_GEN_CNTL, pATIHW->lcd_gen_ctrl); 1575 outr(LCD_INDEX, pATIHW->lcd_index); 1576 } 1577 1578 HDisplay <<= 3; 1579 pATI->LCDHSyncStart <<= 3; 1580 pATI->LCDHSyncWidth <<= 3; 1581 pATI->LCDHBlankWidth <<= 3; 1582 1583 /* Calculate panel dimensions implied by the input timing */ 1584 if ((pATIHW->horz_stretching & 1585 (HORZ_STRETCH_EN | AUTO_HORZ_RATIO)) == 1586 HORZ_STRETCH_EN) 1587 { 1588 if (pATIHW->horz_stretching & HORZ_STRETCH_MODE) 1589 { 1590 if (pATIHW->horz_stretching & HORZ_STRETCH_BLEND) 1591 { 1592 HDisplay = 1593 (HDisplay * (MaxBits(HORZ_STRETCH_BLEND) + 1)) / 1594 GetBits(pATIHW->horz_stretching, 1595 HORZ_STRETCH_BLEND); 1596 } 1597 } 1598 else if (((pATIHW->horz_stretching & HORZ_STRETCH_LOOP) > 1599 HORZ_STRETCH_LOOP15) || 1600 (pATIHW->horz_stretching & 1601 SetBits(1, HORZ_STRETCH_RATIO))) 1602 { 1603 xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING, 1604 "Ignoring invalid horizontal stretch ratio in mode on" 1605 " server entry.\n"); 1606 } 1607 else 1608 { 1609 IOValue = 1610 GetBits(pATIHW->horz_stretching, HORZ_STRETCH_RATIO); 1611 1612 switch (GetBits(pATIHW->horz_stretching, 1613 HORZ_STRETCH_LOOP)) 1614 { 1615 case GetBits(HORZ_STRETCH_LOOP09, HORZ_STRETCH_LOOP): 1616 i = 9; 1617 IOValue &= (1 << 9) - 1; 1618 break; 1619 1620 case GetBits(HORZ_STRETCH_LOOP11, HORZ_STRETCH_LOOP): 1621 i = 11; 1622 IOValue &= (1 << 11) - 1; 1623 break; 1624 1625 case GetBits(HORZ_STRETCH_LOOP12, HORZ_STRETCH_LOOP): 1626 i = 12; 1627 IOValue &= (1 << 12) - 1; 1628 break; 1629 1630 case GetBits(HORZ_STRETCH_LOOP14, HORZ_STRETCH_LOOP): 1631 i = 14; 1632 IOValue &= (1 << 14) - 1; 1633 break; 1634 1635 case GetBits(HORZ_STRETCH_LOOP15, HORZ_STRETCH_LOOP): 1636 default: /* Muffle compiler */ 1637 i = 15; 1638 IOValue &= (1 << 15) - 1; 1639 break; 1640 } 1641 1642 if (IOValue) 1643 { 1644 /* Count the number of bits in IOValue */ 1645 j = (IOValue >> 1) & 0x36DBU; 1646 j = IOValue - j - ((j >> 1) & 0x36DBU); 1647 j = ((j + (j >> 3)) & 0x71C7U) % 0x3FU; 1648 1649 HDisplay = (HDisplay * i) / j; 1650 } 1651 } 1652 } 1653 1654 if ((pATIHW->vert_stretching & VERT_STRETCH_EN) && 1655 !(pATIHW->ext_vert_stretch & AUTO_VERT_RATIO)) 1656 { 1657 if ((pATIHW->vert_stretching & VERT_STRETCH_USE0) || 1658 (VDisplay <= 350)) 1659 IOValue = 1660 GetBits(pATIHW->vert_stretching, VERT_STRETCH_RATIO0); 1661 else if (VDisplay <= 400) 1662 IOValue = 1663 GetBits(pATIHW->vert_stretching, VERT_STRETCH_RATIO1); 1664 else if ((VDisplay <= 480) || 1665 !(pATIHW->ext_vert_stretch & VERT_STRETCH_RATIO3)) 1666 IOValue = 1667 GetBits(pATIHW->vert_stretching, VERT_STRETCH_RATIO2); 1668 else 1669 IOValue = 1670 GetBits(pATIHW->ext_vert_stretch, VERT_STRETCH_RATIO3); 1671 1672 if (IOValue) 1673 VDisplay = 1674 (VDisplay * (MaxBits(VERT_STRETCH_RATIO0) + 1)) / 1675 IOValue; 1676 } 1677 1678 /* Match calculated dimensions to probed dimensions */ 1679 if (!pATI->LCDHorizontal) 1680 { 1681 if ((pATIHW->horz_stretching & 1682 (HORZ_STRETCH_EN | AUTO_HORZ_RATIO)) != 1683 (HORZ_STRETCH_EN | AUTO_HORZ_RATIO)) 1684 pATI->LCDHorizontal = HDisplay; 1685 } 1686 else if (pATI->LCDHorizontal != (int)HDisplay) 1687 { 1688 if ((pATIHW->horz_stretching & 1689 (HORZ_STRETCH_EN | AUTO_HORZ_RATIO)) != 1690 (HORZ_STRETCH_EN | AUTO_HORZ_RATIO)) 1691 xf86DrvMsgVerb(pScreenInfo->scrnIndex, X_WARNING, 4, 1692 "Inconsistent panel horizontal dimension:" 1693 " %d and %d.\n", pATI->LCDHorizontal, HDisplay); 1694 HDisplay = pATI->LCDHorizontal; 1695 } 1696 1697 if (!pATI->LCDVertical) 1698 { 1699 if (!(pATIHW->vert_stretching & VERT_STRETCH_EN) || 1700 !(pATIHW->ext_vert_stretch & AUTO_VERT_RATIO)) 1701 pATI->LCDVertical = VDisplay; 1702 } 1703 else if (pATI->LCDVertical != (int)VDisplay) 1704 { 1705 if (!(pATIHW->vert_stretching & VERT_STRETCH_EN) || 1706 !(pATIHW->ext_vert_stretch & AUTO_VERT_RATIO)) 1707 xf86DrvMsgVerb(pScreenInfo->scrnIndex, X_WARNING, 4, 1708 "Inconsistent panel vertical dimension: %d and %d.\n", 1709 pATI->LCDVertical, VDisplay); 1710 VDisplay = pATI->LCDVertical; 1711 } 1712 1713 if (!pATI->LCDHorizontal || !pATI->LCDVertical) 1714 { 1715 if (pATI->LCDPanelID || (pATI->Chip <= ATI_CHIP_264LTPRO)) 1716 xf86DrvMsg(pScreenInfo->scrnIndex, X_ERROR, 1717 "Unable to determine dimensions of panel (ID %d).\n", 1718 pATI->LCDPanelID); 1719 else 1720 xf86DrvMsg(pScreenInfo->scrnIndex, X_ERROR, 1721 "Unable to determine dimensions of panel.\n"); 1722 1723 goto bail; 1724 } 1725 1726 /* If the mode on entry wasn't stretched, adjust timings */ 1727 if (!(pATIHW->horz_stretching & HORZ_STRETCH_EN) && 1728 (pATI->LCDHorizontal > (int)HDisplay)) 1729 { 1730 HDisplay = pATI->LCDHorizontal - HDisplay; 1731 if (pATI->LCDHSyncStart >= HDisplay) 1732 pATI->LCDHSyncStart -= HDisplay; 1733 else 1734 pATI->LCDHSyncStart = 0; 1735 pATI->LCDHBlankWidth -= HDisplay; 1736 HDisplay = pATI->LCDHSyncStart + pATI->LCDHSyncWidth; 1737 if (pATI->LCDHBlankWidth < HDisplay) 1738 pATI->LCDHBlankWidth = HDisplay; 1739 } 1740 1741 if (!(pATIHW->vert_stretching & VERT_STRETCH_EN) && 1742 (pATI->LCDVertical > (int)VDisplay)) 1743 { 1744 VDisplay = pATI->LCDVertical - VDisplay; 1745 if (pATI->LCDVSyncStart >= VDisplay) 1746 pATI->LCDVSyncStart -= VDisplay; 1747 else 1748 pATI->LCDVSyncStart = 0; 1749 pATI->LCDVBlankWidth -= VDisplay; 1750 VDisplay = pATI->LCDVSyncStart + pATI->LCDVSyncWidth; 1751 if (pATI->LCDVBlankWidth < VDisplay) 1752 pATI->LCDVBlankWidth = VDisplay; 1753 } 1754 1755 if (pATI->LCDPanelID || (pATI->Chip <= ATI_CHIP_264LTPRO)) 1756 xf86DrvMsg(pScreenInfo->scrnIndex, X_PROBED, 1757 "%dx%d panel (ID %d) detected.\n", 1758 pATI->LCDHorizontal, pATI->LCDVertical, pATI->LCDPanelID); 1759 else 1760 xf86DrvMsg(pScreenInfo->scrnIndex, X_PROBED, 1761 "%dx%d panel detected.\n", 1762 pATI->LCDHorizontal, pATI->LCDVertical); 1763 1764 /* 1765 * Determine panel clock. This must be done after option 1766 * processing so that the adapter's reference frequency is always 1767 * available. 1768 * 1769 * Get post divider. A GCC bug has caused the following expression 1770 * to be broken down into its individual components. 1771 */ 1772 ClockMask = PLL_VCLK0_XDIV << pATIHW->clock; 1773 PostMask = PLL_VCLK0_POST_DIV << (pATIHW->clock * 2); 1774 i = GetBits(ATIMach64GetPLLReg(PLL_XCLK_CNTL), ClockMask); 1775 i *= MaxBits(PLL_VCLK0_POST_DIV) + 1; 1776 i |= GetBits(ATIMach64GetPLLReg(PLL_VCLK_POST_DIV), PostMask); 1777 1778 /* Calculate clock of mode on entry */ 1779 Numerator = ATIMach64GetPLLReg(PLL_VCLK0_FB_DIV + pATIHW->clock) * 1780 pATI->ReferenceNumerator; 1781 Denominator = pATI->ClockDescriptor.MinM * 1782 pATI->ReferenceDenominator * 1783 pATI->ClockDescriptor.PostDividers[i]; 1784 pATI->LCDClock = ATIDivide(Numerator, Denominator, 1, 0); 1785 1786 xf86DrvMsg(pScreenInfo->scrnIndex, X_PROBED, 1787 "Panel clock is %.3f MHz.\n", 1788 (double)(pATI->LCDClock) / 1000.0); 1789 1790 xf86DrvMsg(pScreenInfo->scrnIndex, X_INFO, 1791 "Using digital flat panel interface%s.\n", 1792 pATI->OptionCRTDisplay ? 1793 " to display on both CRT and panel" : ""); 1794 } 1795 } 1796 1797 /* 1798 * Finish detecting video RAM size. 1799 */ 1800 pScreenInfo->videoRam = pATI->VideoRAM; 1801 1802 { 1803 { 1804 /* Get adapter's linear aperture configuration */ 1805 pATIHW->config_cntl = inr(CONFIG_CNTL); 1806 pATI->LinearBase = 1807 GetBits(pATIHW->config_cntl, CFG_MEM_AP_LOC) << 22; 1808 if ((pATIHW->config_cntl & CFG_MEM_AP_SIZE) != CFG_MEM_AP_SIZE) 1809 { 1810 pATI->LinearSize = 1811 GetBits(pATIHW->config_cntl, CFG_MEM_AP_SIZE) << 22; 1812 1813 /* 1814 * Linear aperture could have been disabled (but still 1815 * assigned) by BIOS initialisation. 1816 */ 1817 if (pATI->LinearBase && !pATI->LinearSize) 1818 { 1819 if ((pATI->Chip <= ATI_CHIP_88800GXD) && 1820 (pATI->VideoRAM < 4096)) 1821 pATI->LinearSize = 4 * 1024 * 1024; 1822 else 1823 pATI->LinearSize = 8 * 1024 * 1024; 1824 } 1825 } 1826 1827 if (pATI->LinearBase && pATI->LinearSize) 1828 { 1829 int AcceleratorVideoRAM = 0, ServerVideoRAM; 1830 1831#ifndef AVOID_CPIO 1832 1833 /* 1834 * Unless specified in PCI configuration space, set MMIO 1835 * address to tail end of linear aperture. 1836 */ 1837 if (!pATI->Block0Base) 1838 { 1839 pATI->Block0Base = 1840 pATI->LinearBase + pATI->LinearSize - 0x00000400U; 1841 pATI->MMIOInLinear = TRUE; 1842 } 1843 1844#endif /* AVOID_CPIO */ 1845 1846 AcceleratorVideoRAM = pATI->LinearSize >> 10; 1847 1848 /* 1849 * Account for MMIO area at the tail end of the linear 1850 * aperture, if it is needed or if it cannot be disabled. 1851 */ 1852 if (pATI->MMIOInLinear || (pATI->Chip < ATI_CHIP_264VTB)) 1853 AcceleratorVideoRAM -= 2; 1854 1855 ServerVideoRAM = pATI->VideoRAM; 1856 1857 if (pATI->Cursor > ATI_CURSOR_SOFTWARE) 1858 { 1859 /* 1860 * Allocate a 1 kB cursor image area at the top of the 1861 * little-endian aperture, just before any MMIO area that 1862 * might also be there. 1863 */ 1864 if (ServerVideoRAM > AcceleratorVideoRAM) 1865 ServerVideoRAM = AcceleratorVideoRAM; 1866 1867 ServerVideoRAM--; 1868 pATI->CursorOffset = ServerVideoRAM << 10; 1869 pATI->CursorBase = pATI->LinearBase + pATI->CursorOffset; 1870 1871 xf86DrvMsg(pScreenInfo->scrnIndex, X_INFO, 1872 "Storing hardware cursor image at 0x%08lX.\n", 1873 pATI->CursorBase); 1874 } 1875 1876 { 1877 CARD32 PageSize = getpagesize() >> 10; 1878 1879#if X_BYTE_ORDER == X_LITTLE_ENDIAN 1880 1881 /* 1882 * MMIO areas must be mmap()'ed separately to avoid write 1883 * combining them. Thus, they might not end up still 1884 * adjacent with the little-endian linear aperture after 1885 * mmap()'ing. So, round down the linear aperture size to 1886 * avoid an overlap. Any hardware cursor image area might 1887 * not end up being write combined, but this seems 1888 * preferable to further reducing the video memory size 1889 * advertised to the server. 1890 * 1891 * XXX Ideally this should be dealt with in the os-support 1892 * layer, i.e., it should be possible to reset a 1893 * subarea's write combining after it has been 1894 * mmap()'ed, but doing so currently causes the removal 1895 * of write combining for the entire aperture. 1896 */ 1897 if (pATI->MMIOInLinear) 1898 AcceleratorVideoRAM -= AcceleratorVideoRAM % PageSize; 1899 1900#else /* if X_BYTE_ORDER != X_LITTLE_ENDIAN */ 1901 1902 /* 1903 * Big-endian apertures are 8 MB higher and don't contain 1904 * an MMIO area. 1905 */ 1906 pATI->LinearBase += 0x00800000U; 1907 AcceleratorVideoRAM = pATI->LinearSize >> 10; 1908 1909#endif /* X_BYTE_ORDER */ 1910 1911 if (ServerVideoRAM > AcceleratorVideoRAM) 1912 ServerVideoRAM = AcceleratorVideoRAM; 1913 else if (AcceleratorVideoRAM > pATI->VideoRAM) 1914 AcceleratorVideoRAM = pATI->VideoRAM; 1915 1916 PageSize--; 1917 AcceleratorVideoRAM = 1918 (AcceleratorVideoRAM + PageSize) & ~PageSize; 1919 1920 xf86DrvMsg(pScreenInfo->scrnIndex, X_INFO, 1921 "Using %d MB linear aperture at 0x%08lX.\n", 1922 pATI->LinearSize >> 20, pATI->LinearBase); 1923 1924 /* Only mmap what is needed */ 1925 ApertureSize = pATI->LinearSize = 1926 AcceleratorVideoRAM << 10; 1927 } 1928 1929 if (ServerVideoRAM < pATI->VideoRAM) 1930 { 1931 pScreenInfo->videoRam = ServerVideoRAM; 1932 xf86DrvMsg(pScreenInfo->scrnIndex, X_NOTICE, 1933 "Virtual resolutions will be limited to %d kB\n due to" 1934 " linear aperture size and/or placement of hardware" 1935 " cursor image area.\n", 1936 ServerVideoRAM); 1937 } 1938 } 1939 } 1940 1941 if (!pATI->LinearBase || !pATI->LinearSize) 1942 { 1943 xf86DrvMsg(pScreenInfo->scrnIndex, X_ERROR, 1944 "Linear aperture not available.\n"); 1945 goto bail; 1946 } 1947 1948 if (pATI->Block0Base) 1949 { 1950 xf86DrvMsg(pScreenInfo->scrnIndex, X_INFO, 1951 "Using Block 0 MMIO aperture at 0x%08lX.\n", pATI->Block0Base); 1952 1953 /* Set Block1 MMIO address if supported */ 1954 if (pATI->Chip >= ATI_CHIP_264VT) 1955 { 1956 pATI->Block1Base = pATI->Block0Base - 0x00000400U; 1957 xf86DrvMsg(pScreenInfo->scrnIndex, X_INFO, 1958 "Using Block 1 MMIO aperture at 0x%08lX.\n", 1959 pATI->Block1Base); 1960 } 1961 } 1962 } 1963 1964#ifndef AVOID_CPIO 1965 1966 if (pATI->VGAAdapter) 1967 { 1968 /* 1969 * Free VGA memory aperture during operating state (but it is still 1970 * decoded). 1971 */ 1972 pResources = xf86SetOperatingState(resVgaMem, pATI->iEntity, 1973 ResUnusedOpr); 1974 if (pResources) 1975 { 1976 xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING, 1977 "Logic error setting operating state for VGA memory" 1978 " aperture.\n"); 1979 xf86FreeResList(pResources); 1980 } 1981 } 1982 1983#endif /* AVOID_CPIO */ 1984 1985 /* 1986 * Remap apertures. Must lock and re-unlock around this in case the 1987 * remapping fails. 1988 */ 1989 ATILock(pATI); 1990 ATIUnmapApertures(pScreenInfo->scrnIndex, pATI); 1991 if (!ATIMapApertures(pScreenInfo->scrnIndex, pATI)) 1992 return FALSE; 1993 1994 ATIUnlock(pATI); 1995 1996 if (pATI->OptionAccel) 1997 { 1998 xf86DrvMsg(pScreenInfo->scrnIndex, X_INFO, 1999 "MMIO write caching %sabled.\n", 2000 pATI->OptionMMIOCache ? "en" : "dis"); 2001 } 2002 2003 { 2004 if (pATI->Chip >= ATI_CHIP_264CT) 2005 ATIReportMemory(pScreenInfo, pATI, 2006 ATIMemoryTypeNames_264xT[pATI->MemoryType]); 2007 else if (pATI->Chip == ATI_CHIP_88800CX) 2008 ATIReportMemory(pScreenInfo, pATI, 2009 ATIMemoryTypeNames_88800CX[pATI->MemoryType]); 2010 else 2011 ATIReportMemory(pScreenInfo, pATI, 2012 ATIMemoryTypeNames_Mach[pATI->MemoryType]); 2013 } 2014 2015 /* 2016 * Finish banking setup. This needs to be fixed to not assume the mode on 2017 * entry is a VGA mode. XXX 2018 */ 2019 2020#ifndef AVOID_CPIO 2021 2022 if (!pATI->VGAAdapter) 2023 { 2024 pATI->NewHW.SetBank = ATIx8800SetBank; 2025 pATI->NewHW.nPlane = 0; 2026 2027 pATIHW->crtc = pATI->NewHW.crtc; 2028 2029 pATIHW->SetBank = (ATIBankProcPtr)NoopDDA; 2030 } 2031 else 2032 { 2033 Bool ext_disp_en = (pATI->LockData.crtc_gen_cntl & CRTC_EXT_DISP_EN); 2034 Bool vga_ap_en = (pATI->LockData.config_cntl & CFG_MEM_VGA_AP_EN); 2035 Bool vga_color_256 = (GetReg(SEQX, 0x04U) & 0x08U); 2036 2037 pATI->NewHW.SetBank = ATIMach64SetBankPacked; 2038 pATI->NewHW.nPlane = 1; 2039 2040 pATIHW->crtc = ATI_CRTC_VGA; 2041 2042 if (ext_disp_en) 2043 pATIHW->crtc = ATI_CRTC_MACH64; 2044 2045 if ((pATIHW->crtc != ATI_CRTC_VGA) || vga_color_256) 2046 pATIHW->nPlane = 1; 2047 else 2048 pATIHW->nPlane = 4; 2049 2050 /* VideoRAM is a multiple of 512kB and BankSize is 64kB */ 2051 pATIHW->nBank = pATI->VideoRAM / (pATIHW->nPlane * 0x40U); 2052 2053 if ((pATIHW->crtc == ATI_CRTC_VGA) && !vga_ap_en) 2054 { 2055 pATIHW->SetBank = (ATIBankProcPtr)NoopDDA; 2056 pATIHW->nBank = 1; 2057 } 2058 else if (pATIHW->nPlane == 1) 2059 { 2060 pATIHW->SetBank = ATIMach64SetBankPacked; 2061 } 2062 else 2063 { 2064 pATIHW->SetBank = ATIMach64SetBankPlanar; 2065 } 2066 } 2067 2068#else /* AVOID_CPIO */ 2069 2070 { 2071 pATIHW->crtc = pATI->NewHW.crtc; 2072 } 2073 2074#endif /* AVOID_CPIO */ 2075 2076 if (pATI->OptionShadowFB) 2077 { 2078 /* Until ShadowFB becomes a true screen wrapper, if it ever does... */ 2079 2080 if (pATI->OptionAccel) 2081 { 2082 xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING, 2083 "Cannot shadow an accelerated frame buffer.\n"); 2084 pATI->OptionShadowFB = FALSE; 2085 } 2086 else 2087 { 2088 xf86DrvMsg(pScreenInfo->scrnIndex, X_INFO, 2089 "Using shadow frame buffer.\n"); 2090 } 2091 } 2092 2093 /* 264VT-B's and later have DSP registers */ 2094 if ((pATI->Chip >= ATI_CHIP_264VTB) && 2095 !ATIDSPPreInit(pScreenInfo->scrnIndex, pATI)) 2096 goto bail; 2097 2098 /* 2099 * Determine minClock and maxClock. For adapters with supported 2100 * programmable clock generators, start with an absolute maximum. 2101 */ 2102 if (pATI->ClockDescriptor.MaxN > 0) 2103 { 2104 Numerator = pATI->ClockDescriptor.MaxN * pATI->ReferenceNumerator; 2105 Denominator = pATI->ClockDescriptor.MinM * pATI->ReferenceDenominator * 2106 pATI->ClockDescriptor.PostDividers[0]; 2107 2108 /* 2109 * An integrated PLL behaves as though the reference frequency were 2110 * doubled. It also does not appear to care about the colour depth. 2111 */ 2112 if (pATI->ProgrammableClock == ATI_CLOCK_INTERNAL) 2113 Numerator <<= 1; 2114 2115 ATIClockRange.maxClock = (Numerator / (Denominator * 1000)) * 1000; 2116 2117 Numerator = pATI->ClockDescriptor.MinN * pATI->ReferenceNumerator; 2118 Denominator = pATI->ClockDescriptor.MaxM * pATI->ReferenceDenominator * 2119 pATI->ClockDescriptor.PostDividers[pATI->ClockDescriptor.NumD - 1]; 2120 2121 if (pATI->ProgrammableClock == ATI_CLOCK_INTERNAL) 2122 Numerator <<= 1; 2123 2124 ATIClockRange.minClock = (Numerator / (Denominator * 1000)) * 1000; 2125 2126 if (pATI->XCLKFeedbackDivider) 2127 { 2128 /* Possibly reduce maxClock due to memory bandwidth */ 2129 Numerator = pATI->XCLKFeedbackDivider * 2 * 2130 pATI->ReferenceNumerator; 2131 Denominator = pATI->ClockDescriptor.MinM * 2132 pATI->XCLKReferenceDivider * pATI->ReferenceDenominator; 2133 2134 { 2135 Denominator *= pATI->bitsPerPixel / 4; 2136 } 2137 2138 i = (6 - 2) - pATI->XCLKPostDivider; 2139 2140 i = (ATIDivide(Numerator, Denominator, i, -1) / 1000) * 1000; 2141 if (i < ATIClockRange.maxClock) 2142 ATIClockRange.maxClock = i; 2143 } 2144 } 2145 2146 /* 2147 * Assume an internal DAC can handle whatever frequency the internal PLL 2148 * can produce (with the reference divider set by BIOS initialisation), but 2149 * default maxClock to a lower chip-specific default. 2150 */ 2151 if ((pATI->DAC & ~0x0FU) == ATI_DAC_INTERNAL) 2152 { 2153 int DacSpeed; 2154 switch (pATI->bitsPerPixel) 2155 { 2156 case 15: 2157 case 16: 2158 DacSpeed = pGDev->dacSpeeds[DAC_BPP16]; 2159 break; 2160 2161 case 24: 2162 DacSpeed = pGDev->dacSpeeds[DAC_BPP24]; 2163 break; 2164 2165 case 32: 2166 DacSpeed = pGDev->dacSpeeds[DAC_BPP32]; 2167 break; 2168 2169 default: 2170 DacSpeed = 0; 2171 break; 2172 } 2173 if (!DacSpeed) 2174 DacSpeed = pGDev->dacSpeeds[DAC_BPP8]; 2175 if (DacSpeed < ATIClockRange.maxClock) 2176 { 2177 DefaultmaxClock = 135000; 2178 2179 if (pATI->depth > 8) 2180 DefaultmaxClock = 80000; 2181 2182 if ((pATI->Chip >= ATI_CHIP_264VTB) && 2183 (pATI->Chip != ATI_CHIP_Mach64)) 2184 { 2185 if ((pATI->Chip >= ATI_CHIP_264VT4) && 2186 (pATI->Chip != ATI_CHIP_264LTPRO)) 2187 DefaultmaxClock = 230000; 2188 else if (pATI->Chip >= ATI_CHIP_264VT3) 2189 DefaultmaxClock = 200000; 2190 else 2191 DefaultmaxClock = 170000; 2192 } 2193 if (DacSpeed > DefaultmaxClock) 2194 ATIClockRange.maxClock = DacSpeed; 2195 else if (DefaultmaxClock < ATIClockRange.maxClock) 2196 ATIClockRange.maxClock = DefaultmaxClock; 2197 } 2198 } 2199 else 2200 { 2201 switch(pATI->DAC) 2202 { 2203 case ATI_DAC_STG1700: 2204 case ATI_DAC_STG1702: 2205 case ATI_DAC_STG1703: 2206 DefaultmaxClock = 110000; 2207 break; 2208 2209 case ATI_DAC_IBMRGB514: 2210 pATI->maxClock = 220000; 2211 { 2212 DefaultmaxClock = 220000; 2213 } 2214 break; 2215 2216 default: 2217 2218#ifndef AVOID_CPIO 2219 2220 if (pATI->CPIO_VGAWonder && (pATI->VideoRAM < 1024)) 2221 { 2222 DefaultmaxClock = 2223 (GetBits(BIOSByte(0x44U), 0x04U) * 5000) + 40000; 2224 } 2225 else 2226 2227#endif /* AVOID_CPIO */ 2228 2229 { 2230 DefaultmaxClock = 80000; 2231 } 2232 2233 break; 2234 } 2235 2236 if (DefaultmaxClock < ATIClockRange.maxClock) 2237 ATIClockRange.maxClock = DefaultmaxClock; 2238 } 2239 2240 /* 2241 * Determine available pixel clock frequencies. 2242 */ 2243 2244 if ((pATI->ProgrammableClock <= ATI_CLOCK_FIXED) || 2245 (pATI->ProgrammableClock >= ATI_CLOCK_MAX)) 2246 { 2247 xf86DrvMsg(pScreenInfo->scrnIndex, X_ERROR, 2248 "Unsupported or non-programmable clock generator.\n"); 2249 goto bail; 2250 } 2251 2252 ATIClockPreInit(pScreenInfo, pATI); 2253 Strategy = LOOKUP_BEST_REFRESH; 2254 2255 /* 2256 * Mode validation. 2257 */ 2258 2259 if (pATI->Chip >= ATI_CHIP_264CT) 2260 { 2261 minPitch = 8; 2262 } 2263 else 2264 { 2265 minPitch = 16; 2266 } 2267 2268 pitchInc = minPitch * pATI->bitsPerPixel; 2269 2270 pScreenInfo->maxHValue = (MaxBits(CRTC_H_TOTAL) + 1) << 3; 2271 2272 if (pATI->Chip < ATI_CHIP_264VT) 2273 { 2274 /* 2275 * ATI finally fixed accelerated doublescanning in the 264VT 2276 * and later. On 88800's, the bit is documented to exist, but 2277 * only doubles the vertical timings. On the 264CT and 264ET, 2278 * the bit is ignored. 2279 */ 2280 ATIClockRange.doubleScanAllowed = FALSE; 2281 2282 /* CRTC_H_TOTAL is one bit narrower */ 2283 pScreenInfo->maxHValue >>= 1; 2284 } 2285 2286 pScreenInfo->maxVValue = MaxBits(CRTC_V_TOTAL) + 1; 2287 2288 maxPitch = minPitch * MaxBits(CRTC_PITCH); 2289 2290 if (pATI->OptionAccel) 2291 { 2292 /* 2293 * Set engine restrictions on coordinate space. Use maxPitch for the 2294 * horizontal and maxHeight for the vertical. 2295 */ 2296 if (maxPitch > (ATIMach64MaxX / pATI->XModifier)) 2297 maxPitch = ATIMach64MaxX / pATI->XModifier; 2298 2299 maxHeight = ATIMach64MaxY; 2300 2301 /* 2302 * For SGRAM & WRAM adapters, the display engine limits the pitch to 2303 * multiples of 64 bytes. 2304 */ 2305 if ((pATI->Chip >= ATI_CHIP_264CT) && 2306 ((pATI->Chip >= ATI_CHIP_264VTB) || 2307 (pATI->MemoryType >= MEM_264_SGRAM))) 2308 pitchInc = pATI->XModifier * (64 * 8); 2309 } 2310 2311 if (pATI->OptionPanelDisplay && (pATI->LCDPanelID >= 0)) 2312 { 2313 /* 2314 * Given LCD modes are more tightly controlled than CRT modes, allow 2315 * the user the option of not specifying a panel's horizontal sync 2316 * and/or vertical refresh tolerances. 2317 */ 2318 Strategy |= LOOKUP_OPTIONAL_TOLERANCES; 2319 2320 if (ModeType == M_T_BUILTIN) 2321 { 2322 /* 2323 * Add a mode to the end of the monitor's list for the panel's 2324 * native resolution. 2325 */ 2326 pMode = (DisplayModePtr)xnfcalloc(1, SizeOf(DisplayModeRec)); 2327 pMode->name = "Native panel mode"; 2328 pMode->type = M_T_BUILTIN; 2329 pMode->Clock = pATI->LCDClock; 2330 pMode->HDisplay = pATI->LCDHorizontal; 2331 pMode->VDisplay = pATI->LCDVertical; 2332 2333 /* 2334 * These timings are bogus, but enough to survive sync tolerance 2335 * checks. 2336 */ 2337 pMode->HSyncStart = pMode->HDisplay; 2338 pMode->HSyncEnd = pMode->HSyncStart + minPitch; 2339 pMode->HTotal = pMode->HSyncEnd + minPitch; 2340 pMode->VSyncStart = pMode->VDisplay; 2341 pMode->VSyncEnd = pMode->VSyncStart + 1; 2342 pMode->VTotal = pMode->VSyncEnd + 1; 2343 2344 pMode->CrtcHDisplay = pMode->HDisplay; 2345 pMode->CrtcHBlankStart = pMode->HDisplay; 2346 pMode->CrtcHSyncStart = pMode->HSyncStart; 2347 pMode->CrtcHSyncEnd = pMode->HSyncEnd; 2348 pMode->CrtcHBlankEnd = pMode->HTotal; 2349 pMode->CrtcHTotal = pMode->HTotal; 2350 2351 pMode->CrtcVDisplay = pMode->VDisplay; 2352 pMode->CrtcVBlankStart = pMode->VDisplay; 2353 pMode->CrtcVSyncStart = pMode->VSyncStart; 2354 pMode->CrtcVSyncEnd = pMode->VSyncEnd; 2355 pMode->CrtcVBlankEnd = pMode->VTotal; 2356 pMode->CrtcVTotal = pMode->VTotal; 2357 2358 if (!pScreenInfo->monitor->Modes) 2359 { 2360 pScreenInfo->monitor->Modes = pMode; 2361 } 2362 else 2363 { 2364 pScreenInfo->monitor->Last->next = pMode; 2365 pMode->prev = pScreenInfo->monitor->Last; 2366 } 2367 2368 pScreenInfo->monitor->Last = pMode; 2369 } 2370 2371 /* 2372 * Defeat Xconfigurator brain damage. Ignore all HorizSync and 2373 * VertRefresh specifications. For now, this does not take 2374 * SYNC_TOLERANCE into account. 2375 */ 2376 if (pScreenInfo->monitor->nHsync > 0) 2377 { 2378 double hsync = (double)pATI->LCDClock / 2379 (pATI->LCDHorizontal + pATI->LCDHBlankWidth); 2380 2381 for (i = 0; ; i++) 2382 { 2383 if (i >= pScreenInfo->monitor->nHsync) 2384 { 2385 xf86DrvMsg(pScreenInfo->scrnIndex, X_NOTICE, 2386 "Conflicting XF86Config HorizSync specification(s)" 2387 " ignored.\n"); 2388 break; 2389 } 2390 2391 if ((hsync >= pScreenInfo->monitor->hsync[i].lo) && 2392 (hsync <= pScreenInfo->monitor->hsync[i].hi)) 2393 { 2394 xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING, 2395 "Extraneous XF86Config HorizSync specification(s)" 2396 " ignored.\n"); 2397 break; 2398 } 2399 } 2400 2401 pScreenInfo->monitor->nHsync = 0; 2402 } 2403 2404 if (pScreenInfo->monitor->nVrefresh > 0) 2405 { 2406 double vrefresh = ((double)pATI->LCDClock * 1000.0) / 2407 ((pATI->LCDHorizontal + pATI->LCDHBlankWidth) * 2408 (pATI->LCDVertical + pATI->LCDVBlankWidth)); 2409 2410 for (i = 0; ; i++) 2411 { 2412 if (i >= pScreenInfo->monitor->nVrefresh) 2413 { 2414 xf86DrvMsg(pScreenInfo->scrnIndex, X_NOTICE, 2415 "Conflicting XF86Config VertRefresh specification(s)" 2416 " ignored.\n"); 2417 break; 2418 } 2419 2420 if ((vrefresh >= pScreenInfo->monitor->vrefresh[i].lo) && 2421 (vrefresh <= pScreenInfo->monitor->vrefresh[i].hi)) 2422 { 2423 xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING, 2424 "Extraneous XF86Config VertRefresh specification(s)" 2425 " ignored.\n"); 2426 break; 2427 } 2428 } 2429 2430 pScreenInfo->monitor->nVrefresh = 0; 2431 } 2432 } 2433 2434 i = xf86ValidateModes(pScreenInfo, 2435 pScreenInfo->monitor->Modes, pScreenInfo->display->modes, 2436 &ATIClockRange, NULL, minPitch, maxPitch, 2437 pitchInc, 0, maxHeight, 2438 pScreenInfo->display->virtualX, pScreenInfo->display->virtualY, 2439 ApertureSize, Strategy); 2440 if (i <= 0) 2441 goto bail; 2442 2443 /* Remove invalid modes */ 2444 xf86PruneDriverModes(pScreenInfo); 2445 2446 /* Set current mode to the first in the list */ 2447 pScreenInfo->currentMode = pScreenInfo->modes; 2448 2449 /* Print mode list */ 2450 xf86PrintModes(pScreenInfo); 2451 2452 /* Set display resolution */ 2453 xf86SetDpi(pScreenInfo, 0, 0); 2454 2455 /* Load required modules */ 2456 if (!ATILoadModules(pScreenInfo, pATI)) 2457 goto bail; 2458 2459 pATI->displayWidth = pScreenInfo->displayWidth; 2460 2461 /* Initialise for panning */ 2462 ATIAdjustPreInit(pATI); 2463 2464 /* 2465 * Warn about modes that are too small, or not aligned, to scroll to the 2466 * bottom right corner of the virtual screen. 2467 */ 2468 MinX = pScreenInfo->virtualX - pATI->AdjustMaxX; 2469 MinY = pScreenInfo->virtualY - pATI->AdjustMaxY; 2470 2471 pMode = pScreenInfo->modes; 2472 do 2473 { 2474 if ((pMode->VDisplay <= MinY) && 2475 ((pMode->VDisplay < MinY) || (pMode->HDisplay < MinX))) 2476 xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING, 2477 "Mode \"%s\" too small to scroll to bottom right corner of" 2478 " virtual resolution.\n", pMode->name); 2479 else if ((pMode->HDisplay & ~pATI->AdjustMask) / pScreenInfo->xInc) 2480 xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING, 2481 "Mode \"%s\" cannot scroll to bottom right corner of virtual" 2482 " resolution.\n Horizontal dimension not a multiple of %ld.\n", 2483 pMode->name, ~pATI->AdjustMask + 1); 2484 } while ((pMode = pMode->next) != pScreenInfo->modes); 2485 2486 /* Initialise XVideo extension support */ 2487 ATIXVPreInit(pATI); 2488 2489 /* Initialise CRTC code */ 2490 ATIModePreInit(pScreenInfo, pATI, &pATI->NewHW); 2491 2492 /* Set up for I2C */ 2493 ATII2CPreInit(pScreenInfo, pATI); 2494 2495 if (!pScreenInfo->chipset || !*pScreenInfo->chipset) 2496 pScreenInfo->chipset = "mach64"; 2497 2498 PreInitSuccess = TRUE; 2499 2500bail: 2501 ATILock(pATI); 2502 2503bail_locked: 2504 ATIPrintNoiseIfRequested(pATI, BIOS, BIOSSize); 2505 ATIUnmapApertures(pScreenInfo->scrnIndex, pATI); 2506 2507 return PreInitSuccess; 2508} 2509