mach64_sarea.h revision 32b578d3
132b578d3Smrg/*
232b578d3Smrg * Copyright 2000 Gareth Hughes
332b578d3Smrg * All Rights Reserved.
432b578d3Smrg *
532b578d3Smrg * Permission is hereby granted, free of charge, to any person obtaining a
632b578d3Smrg * copy of this software and associated documentation files (the "Software"),
732b578d3Smrg * to deal in the Software without restriction, including without limitation
832b578d3Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
932b578d3Smrg * and/or sell copies of the Software, and to permit persons to whom the
1032b578d3Smrg * Software is furnished to do so, subject to the following conditions:
1132b578d3Smrg *
1232b578d3Smrg * The above copyright notice and this permission notice (including the next
1332b578d3Smrg * paragraph) shall be included in all copies or substantial portions of the
1432b578d3Smrg * Software.
1532b578d3Smrg *
1632b578d3Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1732b578d3Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1832b578d3Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
1932b578d3Smrg * GARETH HUGHES BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
2032b578d3Smrg * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
2132b578d3Smrg * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
2232b578d3Smrg */
2332b578d3Smrg
2432b578d3Smrg/*
2532b578d3Smrg * Authors:
2632b578d3Smrg *   Gareth Hughes <gareth@valinux.com>
2732b578d3Smrg *   Leif Delgass <ldelgass@retinalburn.net>
2832b578d3Smrg */
2932b578d3Smrg
3032b578d3Smrg#ifndef __MACH64_SAREA_H__
3132b578d3Smrg#define __MACH64_SAREA_H__ 1
3232b578d3Smrg
3332b578d3Smrg#include <X11/Xmd.h>
3432b578d3Smrg
3532b578d3Smrg/* WARNING: If you change any of these defines, make sure to change the
3632b578d3Smrg * defines in the kernel file (mach64_drm.h)
3732b578d3Smrg */
3832b578d3Smrg#ifndef __MACH64_SAREA_DEFINES__
3932b578d3Smrg#define __MACH64_SAREA_DEFINES__ 1
4032b578d3Smrg
4132b578d3Smrg/* What needs to be changed for the current vertex buffer?
4232b578d3Smrg * GH: We're going to be pedantic about this.  We want the card to do as
4332b578d3Smrg * little as possible, so let's avoid having it fetch a whole bunch of
4432b578d3Smrg * register values that don't change all that often, if at all.
4532b578d3Smrg */
4632b578d3Smrg#define MACH64_UPLOAD_DST_OFF_PITCH	0x0001
4732b578d3Smrg#define MACH64_UPLOAD_Z_OFF_PITCH	0x0002
4832b578d3Smrg#define MACH64_UPLOAD_Z_ALPHA_CNTL	0x0004
4932b578d3Smrg#define MACH64_UPLOAD_SCALE_3D_CNTL	0x0008
5032b578d3Smrg#define MACH64_UPLOAD_DP_FOG_CLR	0x0010
5132b578d3Smrg#define MACH64_UPLOAD_DP_WRITE_MASK	0x0020
5232b578d3Smrg#define MACH64_UPLOAD_DP_PIX_WIDTH	0x0040
5332b578d3Smrg#define MACH64_UPLOAD_SETUP_CNTL	0x0080
5432b578d3Smrg#define MACH64_UPLOAD_MISC		0x0100
5532b578d3Smrg#define MACH64_UPLOAD_TEXTURE		0x0200
5632b578d3Smrg#define MACH64_UPLOAD_TEX0IMAGE		0x0400
5732b578d3Smrg#define MACH64_UPLOAD_TEX1IMAGE		0x0800
5832b578d3Smrg#define MACH64_UPLOAD_CLIPRECTS		0x1000 /* handled client-side */
5932b578d3Smrg#define MACH64_UPLOAD_CONTEXT		0x00ff
6032b578d3Smrg#define MACH64_UPLOAD_ALL		0x1fff
6132b578d3Smrg
6232b578d3Smrg/* DMA buffer size
6332b578d3Smrg */
6432b578d3Smrg#define MACH64_BUFFER_SIZE		16384
6532b578d3Smrg
6632b578d3Smrg/* Max number of swaps allowed on the ring
6732b578d3Smrg * before the client must wait
6832b578d3Smrg */
6932b578d3Smrg#define MACH64_MAX_QUEUED_FRAMES        3
7032b578d3Smrg
7132b578d3Smrg/* Byte offsets for host blit buffer data
7232b578d3Smrg */
7332b578d3Smrg#define MACH64_HOSTDATA_BLIT_OFFSET	104
7432b578d3Smrg
7532b578d3Smrg/* Keep these small for testing.
7632b578d3Smrg */
7732b578d3Smrg#define MACH64_NR_SAREA_CLIPRECTS	8
7832b578d3Smrg
7932b578d3Smrg
8032b578d3Smrg#define MACH64_CARD_HEAP		0
8132b578d3Smrg#define MACH64_AGP_HEAP			1
8232b578d3Smrg#define MACH64_NR_TEX_HEAPS		2
8332b578d3Smrg#define MACH64_NR_TEX_REGIONS		64
8432b578d3Smrg#define MACH64_LOG_TEX_GRANULARITY	16
8532b578d3Smrg
8632b578d3Smrg#define MACH64_TEX_MAXLEVELS		1
8732b578d3Smrg
8832b578d3Smrg#define MACH64_NR_CONTEXT_REGS		15
8932b578d3Smrg#define MACH64_NR_TEXTURE_REGS		4
9032b578d3Smrg
9132b578d3Smrg#endif /* __MACH64_SAREA_DEFINES__ */
9232b578d3Smrg
9332b578d3Smrgtypedef struct {
9432b578d3Smrg   /* Context state */
9532b578d3Smrg   unsigned int dst_off_pitch;		/* 0x500 */
9632b578d3Smrg
9732b578d3Smrg   unsigned int z_off_pitch;		/* 0x548 */ /* ****** */
9832b578d3Smrg   unsigned int z_cntl;			/* 0x54c */
9932b578d3Smrg   unsigned int alpha_tst_cntl;		/* 0x550 */
10032b578d3Smrg
10132b578d3Smrg   unsigned int scale_3d_cntl;		/* 0x5fc */
10232b578d3Smrg
10332b578d3Smrg   unsigned int sc_left_right;		/* 0x6a8 */
10432b578d3Smrg   unsigned int sc_top_bottom;		/* 0x6b4 */
10532b578d3Smrg
10632b578d3Smrg   unsigned int dp_fog_clr;		/* 0x6c4 */
10732b578d3Smrg   unsigned int dp_write_mask;		/* 0x6c8 */
10832b578d3Smrg   unsigned int dp_pix_width;		/* 0x6d0 */
10932b578d3Smrg   unsigned int dp_mix;			/* 0x6d4 */ /* ****** */
11032b578d3Smrg   unsigned int dp_src;			/* 0x6d8 */ /* ****** */
11132b578d3Smrg
11232b578d3Smrg   unsigned int clr_cmp_cntl;		/* 0x708 */ /* ****** */
11332b578d3Smrg   unsigned int gui_traj_cntl;		/* 0x730 */ /* ****** */
11432b578d3Smrg
11532b578d3Smrg   unsigned int setup_cntl;		/* 0x304 */
11632b578d3Smrg
11732b578d3Smrg   /* Texture state */
11832b578d3Smrg   unsigned int tex_size_pitch;		/* 0x770 */
11932b578d3Smrg   unsigned int tex_cntl;		/* 0x774 */
12032b578d3Smrg   unsigned int secondary_tex_off;	/* 0x778 */
12132b578d3Smrg   unsigned int tex_offset;		/* 0x5c0 */
12232b578d3Smrg} mach64_context_regs_t;
12332b578d3Smrg
12432b578d3Smrgtypedef struct {
12532b578d3Smrg   /* The channel for communication of state information to the kernel
12632b578d3Smrg    * on firing a vertex buffer.
12732b578d3Smrg    */
12832b578d3Smrg   mach64_context_regs_t ContextState;
12932b578d3Smrg   unsigned int dirty;
13032b578d3Smrg   unsigned int vertsize;
13132b578d3Smrg
13232b578d3Smrg#ifdef XF86DRI
13332b578d3Smrg   /* The current cliprects, or a subset thereof.
13432b578d3Smrg    */
13532b578d3Smrg   drm_clip_rect_t boxes[MACH64_NR_SAREA_CLIPRECTS];
13632b578d3Smrg   unsigned int nbox;
13732b578d3Smrg#endif
13832b578d3Smrg   /* Counter for throttling of rendering clients.
13932b578d3Smrg    */
14032b578d3Smrg   unsigned int frames_queued;
14132b578d3Smrg
14232b578d3Smrg   /* Maintain an LRU of contiguous regions of texture space.  If you
14332b578d3Smrg    * think you own a region of texture memory, and it has an age
14432b578d3Smrg    * different to the one you set, then you are mistaken and it has
14532b578d3Smrg    * been stolen by another client.  If global texAge hasn't changed,
14632b578d3Smrg    * there is no need to walk the list.
14732b578d3Smrg    *
14832b578d3Smrg    * These regions can be used as a proxy for the fine-grained texture
14932b578d3Smrg    * information of other clients - by maintaining them in the same
15032b578d3Smrg    * lru which is used to age their own textures, clients have an
15132b578d3Smrg    * approximate lru for the whole of global texture space, and can
15232b578d3Smrg    * make informed decisions as to which areas to kick out.  There is
15332b578d3Smrg    * no need to choose whether to kick out your own texture or someone
15432b578d3Smrg    * else's - simply eject them all in LRU order.
15532b578d3Smrg    */
15632b578d3Smrg   drmTextureRegion texList[MACH64_NR_TEX_HEAPS][MACH64_NR_TEX_REGIONS+1];
15732b578d3Smrg   unsigned int texAge[MACH64_NR_TEX_HEAPS];
15832b578d3Smrg
15932b578d3Smrg   int ctxOwner;     /* last context to upload state */
16032b578d3Smrg} ATISAREAPrivRec, *ATISAREAPrivPtr;
16132b578d3Smrg
16232b578d3Smrg#endif /* __MACH64_SAREA_H__ */
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