mga_PInS.txt revision 1e423a8f
1fe5e51b7SmrgVersion 1:
2fe5e51b7Smrg
3fe5e51b7SmrgOffset  Type      Description
4fe5e51b7Smrg
5fe5e51b7Smrg  0     uint16_t  Length of the PInS data, in bytes.  This must be 64.
6fe5e51b7Smrg  2     uint16_t  Product ID.  Possible values are:
7fe5e51b7Smrg        0: MGA-S1P20 (2MB base with 175MHz RAMDAC)
8fe5e51b7Smrg        1: MGA-S1P21 (2MB base with 220MHz RAMDAC)
9fe5e51b7Smrg        2: Reserved
10fe5e51b7Smrg        3: Reserved
11fe5e51b7Smrg        4: MGA-S1P40 (4MB base with 175MHz RAMDAC)
12fe5e51b7Smrg        5: MGA-S1P41 (4MB base with 220MHz RAMDAC)
13fe5e51b7Smrg  4     char[8]   Serial number of the board.  NUL terminated string.
14fe5e51b7Smrg 12     uint16_t  Manufacturing date of the board (at product test).
15fe5e51b7Smrg                  Format (stored little-endian) yyyyyyymmmmddddd.
16fe5e51b7Smrg 14     uint16_t  Identification of manufacturing site.
17fe5e51b7Smrg 16     uint16_t  Number and revision level of the PCB.  Format (stored
18fe5e51b7Smrg                  little-endian): nnnnnnnnnnnrrrrr, where n = PCB number
19fe5e51b7Smrg                  ex:576 (from 0->2047) and r = PCB revision (from 0->31).
20fe5e51b7Smrg 18     uint16_t  Identification of any PMBs.
21fe5e51b7Smrg 20     uint8_t   RAMDAC speed (0=175MHz, 1=220MHz).
22fe5e51b7Smrg 21     uint8_t   RAMDAC type (0=TVP3026, 1=TVP3027).
23fe5e51b7Smrg 22     uint16_t  Maximum PCLK of the ramdac.
24fe5e51b7Smrg 24     uint16_t  Maximum LDCLK supported by the WRAM memory.
25fe5e51b7Smrg 26     uint16_t  Maximum MCLK of base board.
26fe5e51b7Smrg 28     uint16_t  Maximum MCLK of 4Mb board.
27fe5e51b7Smrg 30     uint16_t  Maximum MCLK of 8Mb board.
28fe5e51b7Smrg 32     uint16_t  Maximum MCLK of board with multimedia module.
29fe5e51b7Smrg 34     uint16_t  Diagnostic test pass frequency.
30fe5e51b7Smrg 36     uint16_t  Default VGA mode1 pixel frequency.
31fe5e51b7Smrg 38     uint16_t  Default VGA mode2 pixel frequency.
32fe5e51b7Smrg 40     uint16_t  Date of last BIOS programming / update.
33fe5e51b7Smrg 42     uint16_t  Number of times BIOS has been programmed.
34fe5e51b7Smrg 44     uint32_t  Support for up to 32 hardware/software options.
35fe5e51b7Smrg 48     uint32_t  Support for up to 32 hardware/software features.
36fe5e51b7Smrg 52     uint16_t  Definition of VGA mode MCLK.
37fe5e51b7Smrg 54     uint16_t  Indicate the revision level of this header struct.
38fe5e51b7Smrg 56     char[7]   Unused.
39fe5e51b7Smrg 63     uint8_t   Check-sum byte.
40fe5e51b7Smrg
41fe5e51b7Smrg
42fe5e51b7SmrgVersion 2:
43fe5e51b7Smrg
44fe5e51b7SmrgUnless otherwise noted, all clock speeds stored in this version of the PInS
45fe5e51b7Smrgdata are stored as the clock speed in MHz minus 100.  To convert a stored
46fe5e51b7Smrgclock speed, C, to kHz, use ((C + 100) * 1000).
47fe5e51b7Smrg
48fe5e51b7SmrgOffset  Type      Description
49fe5e51b7Smrg  0     uint16_t  PInS structure signature.  This must be the 16-bit
50fe5e51b7Smrg                  value (stored little-endian) 0x412E.
51fe5e51b7Smrg  2     uint8_t   Length of the PInS data, in bytes.  For version 2, this
52fe5e51b7Smrg                  must be 64.
53fe5e51b7Smrg  3     uint8_t   Reserved.
54fe5e51b7Smrg  4     uint16_t  Version of the structure.  For version 2, this must be the
55fe5e51b7Smrg                  value (stored little-endian) 0x02XX.
56fe5e51b7Smrg  6     uint16_t  Date of last BIOS programming / update.
57fe5e51b7Smrg  8     uint16_t  Number of times BIOS has been programmed.
58fe5e51b7Smrg 10     uint16_t  Product ID.
59fe5e51b7Smrg 12     char[16]  Serial number of the board.  NUL terminated string.
60fe5e51b7Smrg 28     char[6]   Parts list identification.  NUL terminated string.
61fe5e51b7Smrg 34     uint16_t  Number and revision level of the PCB.  Format (stored
62fe5e51b7Smrg                  little-endian): nnnnnnnnnnnrrrrr, where n = PCB number
63fe5e51b7Smrg                  ex:576 (from 0->2047) and r = PCB revision (from 0->31).
64fe5e51b7Smrg 36     uint32_t  Support for up to 32 hardware/software features.
65fe5e51b7Smrg 40     uint8_t   RAMDAC type.
66fe5e51b7Smrg 41     uint8_t   RAMDAC speed.  Stored using standard clock encoding (see
67fe5e51b7Smrg                  above).
68fe5e51b7Smrg 42     uint8_t   PclkMax
69fe5e51b7Smrg 43     uint8_t   Memory clock.  Stored using standard clock encoding (see
70fe5e51b7Smrg                  above).
71fe5e51b7Smrg 44     uint8_t   Maximum MCLK of base board.
72fe5e51b7Smrg 45     uint8_t   Maximum MCLK of 4Mb board.
73fe5e51b7Smrg 46     uint8_t   Maximum MCLK of 8Mb board.
74fe5e51b7Smrg 47     uint8_t   Maximum MCLK of board with multimedia module.
75fe5e51b7Smrg 48     uint8_t   TestClk
76fe5e51b7Smrg 49     uint8_t   Default VGA mode1 pixel frequency.
77fe5e51b7Smrg 50     uint8_t   Default VGA mode2 pixel frequency.
78fe5e51b7Smrg 51     uint8_t   MCTLWTST
79fe5e51b7Smrg 52     uint8_t   VidCtrl
80fe5e51b7Smrg 53     uint8_t   Maximum MCLK of 12Mb board.
81fe5e51b7Smrg 54     uint8_t   Maximum MCLK of 16Mb board.
82fe5e51b7Smrg 55     char[8]   Unused
83fe5e51b7Smrg 63     uint8_t   Check-sum byte
84fe5e51b7Smrg
85fe5e51b7Smrg
86fe5e51b7SmrgVersion 3:
87fe5e51b7Smrg
88fe5e51b7SmrgUnless otherwise noted, all clock speeds stored in this version of the PInS
89fe5e51b7Smrgdata are stored as the clock speed in MHz minus 100.  To convert a stored
90fe5e51b7Smrgclock speed, C, to kHz, use ((C + 100) * 1000).
91fe5e51b7Smrg
92fe5e51b7SmrgOffset  Type      Description
93fe5e51b7Smrg  0     uint16_t  PInS structure signature.  This must be the 16-bit
94fe5e51b7Smrg                  value (stored little-endian) 0x412E.
95fe5e51b7Smrg  2     uint8_t   Length of the PInS data, in bytes.  For version 3, this
96fe5e51b7Smrg                  must be 64.
97fe5e51b7Smrg  3     uint8_t   Reserved.
98fe5e51b7Smrg  4     uint16_t  Version of the structure.  For version 3, this must be the
99fe5e51b7Smrg                  value (stored little-endian) 0x03XX.
100fe5e51b7Smrg  6     uint16_t  Date of last BIOS programming / update.
101fe5e51b7Smrg  8     uint16_t  Number of times BIOS has been programmed.
102fe5e51b7Smrg 10     uint16_t  Product ID.
103fe5e51b7Smrg 12     char[16]  Serial number of the board.  NUL terminated string.
104fe5e51b7Smrg 28     char[6]   Parts list identification.  NUL terminated string.
105fe5e51b7Smrg 34     uint16_t  Number and revision level of the PCB.  Format (stored
106fe5e51b7Smrg                  little-endian): nnnnnnnnnnnrrrrr, where n = PCB number
107fe5e51b7Smrg                  ex:576 (from 0->2047) and r = PCB revision (from 0->31).
108fe5e51b7Smrg 36     uint8_t   RAMDAC speed.  Stored using standard clock encoding (see
109fe5e51b7Smrg                  above).
110fe5e51b7Smrg 37     char[15]  Unknown?
111fe5e51b7Smrg 52     uint32_t  OPTION?  Stored little-endian.
112fe5e51b7Smrg                  Bits     Meaning
113fe5e51b7Smrg		  0 - 4    Unknown?
114fe5e51b7Smrg		  5        0 = Reference PLL speed is 27.050MHz.
115fe5e51b7Smrg		           1 = Reference PLL speed is 14.318MHz.
116fe5e51b7Smrg		  6 - 31   Unknown?
117fe5e51b7Smrg 56     uint16_t  MEMRDBK?
118fe5e51b7Smrg 58     uint32_t  OPTION2?
119fe5e51b7Smrg 62     char      Unused
120fe5e51b7Smrg 63     uint8_t   Check-sum byte
121fe5e51b7Smrg
122fe5e51b7Smrg
123fe5e51b7SmrgVersion 4:
124fe5e51b7Smrg
125fe5e51b7SmrgUnless otherwise noted, all clock speeds stored in this version of the PInS
126fe5e51b7Smrgdata are stored as the clock speed in MHz divided by 4.  To convert a stored
127fe5e51b7Smrgclock speed, C, to kHz, use ((C * 4) * 1000).
128fe5e51b7Smrg
129fe5e51b7SmrgOffset  Type      Description
130fe5e51b7Smrg  0     uint16_t  PInS structure signature.  This must be the 16-bit
131fe5e51b7Smrg                  value (stored little-endian) 0x412E.
132fe5e51b7Smrg  2     uint8_t   Length of the PInS data, in bytes.  For version 4, this
133fe5e51b7Smrg                  must be 128.
134fe5e51b7Smrg  3     uint8_t   Reserved.
135fe5e51b7Smrg  4     uint16_t  Version of the structure.  For version 4, this must be the
136fe5e51b7Smrg                  value (stored little-endian) 0x04XX.
137fe5e51b7Smrg  6     uint16_t  Date of last BIOS programming / update.
138fe5e51b7Smrg  8     uint16_t  Number of times BIOS has been programmed.
139fe5e51b7Smrg 10     uint16_t  Product ID.
140fe5e51b7Smrg 12     char[16]  Serial number of the board.  NUL terminated string.
141fe5e51b7Smrg 28     char[6]   Parts list identification.  NUL terminated string.
142fe5e51b7Smrg 34     uint16_t  Number and revision level of the PCB.  Format (stored
143fe5e51b7Smrg                  little-endian): nnnnnnnnnnnrrrrr, where n = PCB number
144fe5e51b7Smrg                  ex:576 (from 0->2047) and r = PCB revision (from 0->31).
145fe5e51b7Smrg 36     char      Unknown?
146fe5e51b7Smrg 37     char      Unknown?
147fe5e51b7Smrg 38     uint8_t   VCO max for system PLL
148fe5e51b7Smrg 39     uint8_t   VCO max for pixel PLL
149fe5e51b7Smrg 40     char[13]  Unknown?
150fe5e51b7Smrg 53     uint8_t   OPTION?
151fe5e51b7Smrg 54     char[11]  Unknown?
152fe5e51b7Smrg 65     uint8_t   System PLL?  Stored using standard clock encoding (see
153fe5e51b7Smrg                  above).
154fe5e51b7Smrg 66     char      Unknown?
155fe5e51b7Smrg 67     uint32_t  OPTION3?  This offset seems wrong, but that's what
156fe5e51b7Smrg                  matroxfb does.
157fe5e51b7Smrg 71     char[15]  Unknown?
158fe5e51b7Smrg 86     uint16_t  MEMRDBK?
159fe5e51b7Smrg 88     char[4]   Unknown?
160fe5e51b7Smrg 92     uint32_t  OPTIONx?
161fe5e51b7Smrg                  Bits     Meaning
162fe5e51b7Smrg		  0        0 = Reference PLL speed is 27.050MHz.
163fe5e51b7Smrg		           1 = Reference PLL speed is 14.318MHz.
164fe5e51b7Smrg		  1 - 31   Unknown?
165fe5e51b7Smrg 96     char[21]  Unknown?
166fe5e51b7Smrg127     uint8_t   Check-sum byte
167fe5e51b7Smrg
168fe5e51b7Smrg
169fe5e51b7SmrgVersion 5:
170fe5e51b7Smrg
171fe5e51b7SmrgUnless otherwise noted, all clock speeds stored in this version of the PInS
172fe5e51b7Smrgdata are stored as the clock speed in MHz divided by 6 for version 0x500 or
173fe5e51b7Smrgby 8 for all other versions.  To convert a stored clock speed, C, to kHz, on
174fe5e51b7Smrgversion 0x0500, use ((C * 6) * 1000).  For all other versions, use ((C * 8) *
175fe5e51b7Smrg1000).
176fe5e51b7Smrg
177fe5e51b7SmrgOffset  Type      Description
178fe5e51b7Smrg  0     uint16_t  PInS structure signature.  This must be the 16-bit
179fe5e51b7Smrg                  value (stored little-endian) 0x412E.
180fe5e51b7Smrg  2     uint8_t   Length of the PInS data, in bytes.  For version 5, this
181fe5e51b7Smrg                  must be 128.
182fe5e51b7Smrg  3     uint8_t   Reserved.
183fe5e51b7Smrg  4     uint16_t  Version of the structure.  For version 5, this must be the
184fe5e51b7Smrg                  value (stored little-endian) 0x05XX.
185fe5e51b7Smrg  6     uint16_t  Date of last BIOS programming / update.
186fe5e51b7Smrg  8     uint16_t  Number of times BIOS has been programmed.
187fe5e51b7Smrg 10     uint16_t  Product ID.
188fe5e51b7Smrg 12     char[16]  Serial number of the board.  NUL terminated string.
189fe5e51b7Smrg 28     char[6]   Parts list identification.  NUL terminated string.
190fe5e51b7Smrg 34     uint16_t  Number and revision level of the PCB.  Format (stored
191fe5e51b7Smrg                  little-endian): nnnnnnnnnnnrrrrr, where n = PCB number
192fe5e51b7Smrg                  ex:576 (from 0->2047) and r = PCB revision (from 0->31).
193fe5e51b7Smrg 36     uint8_t   VCO max for system PLL.  Stored using standard clock
194fe5e51b7Smrg                  encoding (see above).
195fe5e51b7Smrg 37     uint8_t   VCO max for video PLL.  Stored using standard clock
196fe5e51b7Smrg                  encoding (see above).
197fe5e51b7Smrg 38     uint8_t   VCO max for pixel PLL.  Stored using standard clock
198fe5e51b7Smrg                  encoding (see above).
199fe5e51b7Smrg 39     char[9]   Unknown?
200fe5e51b7Smrg 48     uint32_t  OPTION1?
201fe5e51b7Smrg 52     uint32_t  OPTION2?
202fe5e51b7Smrg 56     char[38]  Unknown?
203fe5e51b7Smrg 94     uint32_t  OPTION3?
204fe5e51b7Smrg 98     uint32_t  MCTLWTST?
205fe5e51b7Smrg102     uint32_t  MEMMISC?
206fe5e51b7Smrg106     uint32_t  MEMRDBK?
207fe5e51b7Smrg110     uint32_t  OPTIONx?
208fe5e51b7Smrg                  Bits     Meaning
209fe5e51b7Smrg		  0        0 = Reference PLL speed is 27.050MHz.
210fe5e51b7Smrg		           1 = Reference PLL speed is 14.318MHz.
211fe5e51b7Smrg		  1 - 31   Unknown?
212fe5e51b7Smrg114     uint16_t  MEMINFO?
213fe5e51b7Smrg                  Bits     Meaning
214fe5e51b7Smrg		  0 - 4    Unknown
215fe5e51b7Smrg		  5 - 6    0 = SDR memory installed?
216fe5e51b7Smrg		           1 = DDR memory installed
217fe5e51b7Smrg		           2 = Unknown
218fe5e51b7Smrg		           3 = Unknown
219fe5e51b7Smrg		  7        Unknown
220fe5e51b7Smrg		  8        EMRSWEN?
221fe5e51b7Smrg		  9        Has DLL?
222fe5e51b7Smrg		  10       Core uses MCTLWTST?
223fe5e51b7Smrg		  11 - 15  MCTLWTST values for core?
224fe5e51b7Smrg116     uint16_t  Display Info.
225fe5e51b7Smrg                  Bits     Meaning
226fe5e51b7Smrg                  0-3      Primary display info (see below)
227fe5e51b7Smrg                  4-7      Secondary display info (see below)
228fe5e51b7Smrg                  8-10     Primary modes (see below)
229fe5e51b7Smrg                  13       Default output
230fe5e51b7Smrg                           0 = default output is secondary connector
231fe5e51b7Smrg                           1 = default output is primary connector
232fe5e51b7Smrg                  12-14    Secondary modes (see below)
2331e423a8fSmrg                  15       Primary hardware detect
234fe5e51b7Smrg                           0 = hardware detection is off
235fe5e51b7Smrg                           1 = use hardware detection to determine main output
236fe5e51b7Smrg                           
237fe5e51b7Smrg                  Display info values:
238fe5e51b7Smrg                  0000     None
239fe5e51b7Smrg                  0001     HD15
240fe5e51b7Smrg                  0010     DVI
241fe5e51b7Smrg                  0011     TV
242fe5e51b7Smrg                  x1xx     Reserved
243fe5e51b7Smrg                  1xxx     Reserved
244fe5e51b7Smrg
245fe5e51b7Smrg                  Modes values:
246fe5e51b7Smrg                  xx1      Analog
247fe5e51b7Smrg                  x1x      Digital
248fe5e51b7Smrg                  1xx      TV
249fe5e51b7Smrg
250fe5e51b7Smrg118     char[3]   Unknown?
251fe5e51b7Smrg121     uint8_t   VCO min for system PLL.  Stored using standard clock
252fe5e51b7Smrg                  encoding (see above).
253fe5e51b7Smrg122     uint8_t   VCO min for video PLL.  Stored using standard clock
254fe5e51b7Smrg                  encoding (see above).
255fe5e51b7Smrg123     uint8_t   VCO min for pixel PLL.  Stored using standard clock
256fe5e51b7Smrg                  encoding (see above).
257fe5e51b7Smrg124     char[3]   Unknown?
258fe5e51b7Smrg127     uint8_t   Check-sum byte
259