1fe5e51b7Smrg/* 2fe5e51b7Smrg * MGA Millennium (MGA2064W) functions 3fe5e51b7Smrg * 4fe5e51b7Smrg * Copyright 1996 The XFree86 Project, Inc. 5fe5e51b7Smrg * 6fe5e51b7Smrg * Authors 7fe5e51b7Smrg * Dirk Hohndel 8fe5e51b7Smrg * hohndel@XFree86.Org 9fe5e51b7Smrg * David Dawes 10fe5e51b7Smrg * dawes@XFree86.Org 11fe5e51b7Smrg */ 12fe5e51b7Smrg 13fe5e51b7Smrg#ifndef MGA_H 14fe5e51b7Smrg#define MGA_H 15fe5e51b7Smrg 16fe5e51b7Smrg#ifdef XSERVER_LIBPCIACCESS 17fe5e51b7Smrg#include <pciaccess.h> 18fe5e51b7Smrg#endif 19fe5e51b7Smrg#include <string.h> 20fe5e51b7Smrg#include <stdio.h> 21fe5e51b7Smrg 22fe5e51b7Smrg#include "compiler.h" 230bb88ba4Smrg#ifdef HAVE_XAA_H 24fe5e51b7Smrg#include "xaa.h" 250bb88ba4Smrg#endif 260bb88ba4Smrg#include "xf86fbman.h" 27fe5e51b7Smrg#include "exa.h" 28fe5e51b7Smrg#include "xf86Cursor.h" 29fe5e51b7Smrg#include "vgaHW.h" 30fe5e51b7Smrg#include "colormapst.h" 31fe5e51b7Smrg#include "xf86DDC.h" 32fe5e51b7Smrg#include "xf86xv.h" 33fe5e51b7Smrg 340bb88ba4Smrg#ifndef XF86DRI 350bb88ba4Smrg#undef MGADRI 360bb88ba4Smrg#endif 370bb88ba4Smrg 380bb88ba4Smrg#ifdef MGADRI 39fe5e51b7Smrg#include "xf86drm.h" 40fe5e51b7Smrg 41fe5e51b7Smrg#define _XF86DRI_SERVER_ 42fe5e51b7Smrg#include "mga_dripriv.h" 43fe5e51b7Smrg#include "dri.h" 44fe5e51b7Smrg 45fe5e51b7Smrg#include "mga_dri.h" 46fe5e51b7Smrg#endif 47fe5e51b7Smrg 480bb88ba4Smrg#include "compat-api.h" 49fe5e51b7Smrg 50fe5e51b7Smrgtypedef enum { 51fe5e51b7Smrg OPTION_SW_CURSOR, 52fe5e51b7Smrg OPTION_HW_CURSOR, 53fe5e51b7Smrg OPTION_PCI_RETRY, 54fe5e51b7Smrg OPTION_SYNC_ON_GREEN, 55fe5e51b7Smrg OPTION_NOACCEL, 56fe5e51b7Smrg OPTION_SHOWCACHE, 57fe5e51b7Smrg OPTION_OVERLAY, 58fe5e51b7Smrg OPTION_MGA_SDRAM, 59fe5e51b7Smrg OPTION_SHADOW_FB, 60fe5e51b7Smrg OPTION_FBDEV, 61fe5e51b7Smrg OPTION_COLOR_KEY, 62fe5e51b7Smrg OPTION_SET_MCLK, 63fe5e51b7Smrg OPTION_OVERCLOCK_MEM, 64fe5e51b7Smrg OPTION_VIDEO_KEY, 65fe5e51b7Smrg OPTION_ROTATE, 66fe5e51b7Smrg OPTION_TEXTURED_VIDEO, 67fe5e51b7Smrg OPTION_CRTC2HALF, 68fe5e51b7Smrg OPTION_CRTC2RAM, 69fe5e51b7Smrg OPTION_INT10, 70fe5e51b7Smrg OPTION_AGP_MODE, 71fe5e51b7Smrg OPTION_AGP_SIZE, 72fe5e51b7Smrg OPTION_DIGITAL1, 73fe5e51b7Smrg OPTION_DIGITAL2, 74fe5e51b7Smrg OPTION_TV, 75fe5e51b7Smrg OPTION_TVSTANDARD, 76fe5e51b7Smrg OPTION_CABLETYPE, 77fe5e51b7Smrg OPTION_USEIRQZERO, 78fe5e51b7Smrg OPTION_NOHAL, 79fe5e51b7Smrg OPTION_SWAPPED_HEAD, 80fe5e51b7Smrg OPTION_DRI, 81fe5e51b7Smrg OPTION_MERGEDFB, 82fe5e51b7Smrg OPTION_HSYNC2, 83fe5e51b7Smrg OPTION_VREFRESH2, 84fe5e51b7Smrg OPTION_MONITOR2POS, 85fe5e51b7Smrg OPTION_METAMODES, 86fe5e51b7Smrg OPTION_OLDDMA, 87fe5e51b7Smrg OPTION_PCIDMA, 88eda3803bSmrg OPTION_ACCELMETHOD, 89eda3803bSmrg OPTION_KVM 90fe5e51b7Smrg} MGAOpts; 91fe5e51b7Smrg 92fe5e51b7Smrg 93fe5e51b7Smrg#if !defined(EXTRADEBUG) 94fe5e51b7Smrg#define INREG8(addr) MMIO_IN8(pMga->IOBase, addr) 95fe5e51b7Smrg#define INREG16(addr) MMIO_IN16(pMga->IOBase, addr) 96fe5e51b7Smrg#define INREG(addr) MMIO_IN32(pMga->IOBase, addr) 97fe5e51b7Smrg#define OUTREG8(addr, val) MMIO_OUT8(pMga->IOBase, addr, val) 98fe5e51b7Smrg#define OUTREG16(addr, val) MMIO_OUT16(pMga->IOBase, addr, val) 99fe5e51b7Smrg#define OUTREG(addr, val) MMIO_OUT32(pMga->IOBase, addr, val) 100fe5e51b7Smrg#else /* !EXTRADEBUG */ 101fe5e51b7SmrgCARD8 MGAdbg_inreg8(ScrnInfoPtr, int, int, char*); 102fe5e51b7SmrgCARD16 MGAdbg_inreg16(ScrnInfoPtr, int, int, char*); 103fe5e51b7SmrgCARD32 MGAdbg_inreg32(ScrnInfoPtr, int, int, char*); 104fe5e51b7Smrgvoid MGAdbg_outreg8(ScrnInfoPtr, int, int, char*); 105fe5e51b7Smrgvoid MGAdbg_outreg16(ScrnInfoPtr, int,int, char*); 106fe5e51b7Smrgvoid MGAdbg_outreg32(ScrnInfoPtr, int,int, char*); 107fe5e51b7Smrg#ifndef __GNUC__ 108fe5e51b7Smrg# define MGA_STRINGIZE(x) #x 109fe5e51b7Smrg# define MGA_STRINGIFY(x) MGA_STRINGIZE(x) 110fe5e51b7Smrg# define __FUNCTION__ MGA_STRINGIFY(__FILE__) ", line " MGA_STRINGIFY(__LINE__) 111fe5e51b7Smrg#endif 112fe5e51b7Smrg#define INREG8(addr) MGAdbg_inreg8(pScrn, addr, 1, __FUNCTION__) 113fe5e51b7Smrg#define INREG16(addr) MGAdbg_inreg16(pScrn, addr, 1, __FUNCTION__) 114fe5e51b7Smrg#define INREG(addr) MGAdbg_inreg32(pScrn, addr, 1, __FUNCTION__) 115fe5e51b7Smrg#define OUTREG8(addr,val) MGAdbg_outreg8(pScrn, addr, val, __FUNCTION__) 116fe5e51b7Smrg#define OUTREG16(addr,val) MGAdbg_outreg16(pScrn, addr, val, __FUNCTION__) 117fe5e51b7Smrg#define OUTREG(addr,val) MGAdbg_outreg32(pScrn, addr, val, __FUNCTION__) 118fe5e51b7Smrg#endif /* EXTRADEBUG */ 119fe5e51b7Smrg 1200bb88ba4Smrg/* 1210bb88ba4Smrg * PCI vendor/device ids, formerly in xf86PciInfo.h 1220bb88ba4Smrg */ 123eda3803bSmrg 1240bb88ba4Smrg#define PCI_VENDOR_MATROX 0x102B 1250bb88ba4Smrg 1260bb88ba4Smrg#define PCI_CHIP_MGA2085 0x0518 1270bb88ba4Smrg#define PCI_CHIP_MGA2064 0x0519 1280bb88ba4Smrg#define PCI_CHIP_MGA1064 0x051A 1290bb88ba4Smrg#define PCI_CHIP_MGA2164 0x051B 1300bb88ba4Smrg#define PCI_CHIP_MGA2164_AGP 0x051F 1310bb88ba4Smrg 1320bb88ba4Smrg#define PCI_CHIP_MGAG100_PCI 0x1000 1330bb88ba4Smrg#define PCI_CHIP_MGAG100 0x1001 1340bb88ba4Smrg#define PCI_CHIP_MGAG200_PCI 0x0520 1350bb88ba4Smrg#define PCI_CHIP_MGAG200 0x0521 1360bb88ba4Smrg#define PCI_CHIP_MGAG200_SE_A_PCI 0x0522 1370bb88ba4Smrg#define PCI_CHIP_MGAG200_SE_B_PCI 0x0524 1380bb88ba4Smrg#define PCI_CHIP_MGAG200_WINBOND_PCI 0x0532 1390bb88ba4Smrg#define PCI_CHIP_MGAG200_EV_PCI 0x0530 1400bb88ba4Smrg#define PCI_CHIP_MGAG200_EH_PCI 0x0533 1410bb88ba4Smrg#define PCI_CHIP_MGAG200_ER_PCI 0x0534 1420bb88ba4Smrg#define PCI_CHIP_MGAG400 0x0525 1430bb88ba4Smrg#define PCI_CHIP_MGAG550 0x2527 144a31a186aSmrg 145ee82cb62Smrg#ifndef PCI_CHIP_MGAG200_EW3_PCI 146ee82cb62Smrg#define PCI_CHIP_MGAG200_EW3_PCI 0x0536 147ee82cb62Smrg#endif 148ee82cb62Smrg 149b0de6900Smrg#ifndef PCI_CHIP_MGAG200_EH3_PCI 150b0de6900Smrg#define PCI_CHIP_MGAG200_EH3_PCI 0x0538 151b0de6900Smrg#endif 152ee82cb62Smrg 153fe5e51b7Smrg/* 154fe5e51b7Smrg * Read/write to the DAC via MMIO 155fe5e51b7Smrg */ 156fe5e51b7Smrg 157fe5e51b7Smrg/* 158fe5e51b7Smrg * These were functions. Use macros instead to avoid the need to 159fe5e51b7Smrg * pass pMga to them. 160fe5e51b7Smrg */ 161fe5e51b7Smrg 162fe5e51b7Smrg#define inMGAdreg(reg) INREG8(RAMDAC_OFFSET + (reg)) 163fe5e51b7Smrg 164fe5e51b7Smrg#define outMGAdreg(reg, val) OUTREG8(RAMDAC_OFFSET + (reg), val) 165fe5e51b7Smrg 166fe5e51b7Smrg#define inMGAdac(reg) \ 167fe5e51b7Smrg (outMGAdreg(MGA1064_INDEX, reg), inMGAdreg(MGA1064_DATA)) 168fe5e51b7Smrg 169fe5e51b7Smrg#define outMGAdac(reg, val) \ 170fe5e51b7Smrg (outMGAdreg(MGA1064_INDEX, reg), outMGAdreg(MGA1064_DATA, val)) 171fe5e51b7Smrg 172fe5e51b7Smrg#define outMGAdacmsk(reg, mask, val) \ 173fe5e51b7Smrg do { /* note: mask and reg may get evaluated twice */ \ 174fe5e51b7Smrg unsigned char tmp = (mask) ? (inMGAdac(reg) & (mask)) : 0; \ 175fe5e51b7Smrg outMGAdreg(MGA1064_INDEX, reg); \ 176fe5e51b7Smrg outMGAdreg(MGA1064_DATA, tmp | (val)); \ 177fe5e51b7Smrg } while (0) 178fe5e51b7Smrg 179fe5e51b7Smrg#define MGAWAITVSYNC() \ 180fe5e51b7Smrg do { \ 181fe5e51b7Smrg unsigned int count = 0; \ 182fe5e51b7Smrg unsigned int status = 0; \ 183fe5e51b7Smrg do { \ 184fe5e51b7Smrg status = INREG( MGAREG_Status ); \ 185fe5e51b7Smrg count++; \ 186fe5e51b7Smrg } while( ( status & 0x08 ) && (count < 250000) );\ 187fe5e51b7Smrg count = 0; \ 188fe5e51b7Smrg status = 0; \ 189fe5e51b7Smrg do { \ 190fe5e51b7Smrg status = INREG( MGAREG_Status ); \ 191fe5e51b7Smrg count++; \ 192fe5e51b7Smrg } while( !( status & 0x08 ) && (count < 250000) );\ 193fe5e51b7Smrg } while (0) 194fe5e51b7Smrg 195fe5e51b7Smrg#define MGAWAITBUSY() \ 196fe5e51b7Smrg do { \ 197fe5e51b7Smrg unsigned int count = 0; \ 198fe5e51b7Smrg unsigned int status = 0; \ 199fe5e51b7Smrg do { \ 200fe5e51b7Smrg status = INREG8( MGAREG_Status + 2 ); \ 201fe5e51b7Smrg count++; \ 202fe5e51b7Smrg } while( ( status & 0x01 ) && (count < 500000) ); \ 203fe5e51b7Smrg } while (0) 204fe5e51b7Smrg 205fe5e51b7Smrg#define PORT_OFFSET (0x1F00 - 0x300) 206fe5e51b7Smrg 207fe5e51b7Smrg#define MGA_VERSION 4000 208fe5e51b7Smrg#define MGA_NAME "MGA" 209fe5e51b7Smrg#define MGA_C_NAME MGA 210fe5e51b7Smrg#define MGA_MODULE_DATA mgaModuleData 211fe5e51b7Smrg#define MGA_DRIVER_NAME "mga" 212fe5e51b7Smrg 213fe5e51b7Smrgtypedef struct { 214fe5e51b7Smrg unsigned char ExtVga[6]; 215fe5e51b7Smrg unsigned char DacClk[6]; 216ee82cb62Smrg unsigned char ExtVga_MgaReq; 2170bb88ba4Smrg unsigned char Dac_Index90; 218ee82cb62Smrg unsigned char * DacRegs; 219fe5e51b7Smrg unsigned long crtc2[0x58]; 220fe5e51b7Smrg unsigned char dac2[0x21]; 221b0de6900Smrg uint32_t Option; 222b0de6900Smrg uint32_t Option2; 223b0de6900Smrg uint32_t Option3; 224fe5e51b7Smrg long Clock; 225493f84f4Smrg unsigned char Pan_Ctl; 226fe5e51b7Smrg Bool PIXPLLCSaved; 227eda3803bSmrg unsigned char PllM; 228eda3803bSmrg unsigned char PllN; 229eda3803bSmrg unsigned char PllP; 230fe5e51b7Smrg} MGARegRec, *MGARegPtr; 231fe5e51b7Smrg 232fe5e51b7Smrg/* For programming the second CRTC */ 233fe5e51b7Smrgtypedef struct { 234fe5e51b7Smrg CARD32 ulDispWidth; /* Display Width in pixels*/ 235fe5e51b7Smrg CARD32 ulDispHeight; /* Display Height in pixels*/ 236fe5e51b7Smrg CARD32 ulBpp; /* Bits Per Pixels / input format*/ 237fe5e51b7Smrg CARD32 ulPixClock; /* Pixel Clock in kHz*/ 238fe5e51b7Smrg CARD32 ulHFPorch; /* Horizontal front porch in pixels*/ 239fe5e51b7Smrg CARD32 ulHSync; /* Horizontal Sync in pixels*/ 240fe5e51b7Smrg CARD32 ulHBPorch; /* Horizontal back porch in pixels*/ 241fe5e51b7Smrg CARD32 ulVFPorch; /* Vertical front porch in lines*/ 242fe5e51b7Smrg CARD32 ulVSync; /* Vertical Sync in lines*/ 243fe5e51b7Smrg CARD32 ulVBPorch; /* Vertical back Porch in lines*/ 244fe5e51b7Smrg CARD32 ulFBPitch; /* Pitch*/ 245fe5e51b7Smrg CARD32 flSignalMode; /* Signal Mode*/ 246fe5e51b7Smrg} xMODEINFO; 247fe5e51b7Smrg 248fe5e51b7Smrg 249fe5e51b7Smrgtypedef struct { 250fe5e51b7Smrg int brightness; 251fe5e51b7Smrg int contrast; 252fe5e51b7Smrg Bool doubleBuffer; 253fe5e51b7Smrg unsigned char currentBuffer; 254fe5e51b7Smrg RegionRec clip; 255fe5e51b7Smrg CARD32 colorKey; 256fe5e51b7Smrg CARD32 videoStatus; 257fe5e51b7Smrg Time offTime; 258fe5e51b7Smrg Time freeTime; 259fe5e51b7Smrg int lastPort; 260fe5e51b7Smrg 261fe5e51b7Smrg#ifdef USE_EXA 262fe5e51b7Smrg int size; 263fe5e51b7Smrg ExaOffscreenArea *off_screen; 264fe5e51b7Smrg#endif 265fe5e51b7Smrg 266fe5e51b7Smrg void *video_memory; 267fe5e51b7Smrg int video_offset; 268fe5e51b7Smrg} MGAPortPrivRec, *MGAPortPrivPtr; 269fe5e51b7Smrg 270fe5e51b7Smrgtypedef struct { 271fe5e51b7Smrg Bool isHwCursor; 272fe5e51b7Smrg int CursorMaxWidth; 273fe5e51b7Smrg int CursorMaxHeight; 274fe5e51b7Smrg int CursorFlags; 275fe5e51b7Smrg int CursorOffscreenMemSize; 276fe5e51b7Smrg Bool (*UseHWCursor)(ScreenPtr, CursorPtr); 277fe5e51b7Smrg void (*LoadCursorImage)(ScrnInfoPtr, unsigned char*); 278fe5e51b7Smrg void (*ShowCursor)(ScrnInfoPtr); 279fe5e51b7Smrg void (*HideCursor)(ScrnInfoPtr); 280fe5e51b7Smrg void (*SetCursorPosition)(ScrnInfoPtr, int, int); 281fe5e51b7Smrg void (*SetCursorColors)(ScrnInfoPtr, int, int); 282fe5e51b7Smrg long maxPixelClock; 283fe5e51b7Smrg long MemoryClock; 284fe5e51b7Smrg MessageType ClockFrom; 285fe5e51b7Smrg MessageType MemClkFrom; 286fe5e51b7Smrg Bool SetMemClk; 287fe5e51b7Smrg void (*LoadPalette)(ScrnInfoPtr, int, int*, LOCO*, VisualPtr); 288fe5e51b7Smrg void (*RestorePalette)(ScrnInfoPtr, unsigned char *); 289fe5e51b7Smrg void (*PreInit)(ScrnInfoPtr); 290fe5e51b7Smrg void (*Save)(ScrnInfoPtr, vgaRegPtr, MGARegPtr, Bool); 291fe5e51b7Smrg void (*Restore)(ScrnInfoPtr, vgaRegPtr, MGARegPtr, Bool); 292fe5e51b7Smrg Bool (*ModeInit)(ScrnInfoPtr, DisplayModePtr); 293fe5e51b7Smrg} MGARamdacRec, *MGARamdacPtr; 294fe5e51b7Smrg 295fe5e51b7Smrg 296fe5e51b7Smrgtypedef struct { 297fe5e51b7Smrg int bitsPerPixel; 298fe5e51b7Smrg int depth; 299fe5e51b7Smrg int displayWidth; 300fe5e51b7Smrg rgb weight; 301fe5e51b7Smrg DisplayModePtr mode; 302fe5e51b7Smrg} MGAFBLayout; 303fe5e51b7Smrg 304fe5e51b7Smrg/* Card-specific driver information */ 305fe5e51b7Smrg 306fe5e51b7Smrgtypedef struct { 307fe5e51b7Smrg Bool update; 308fe5e51b7Smrg unsigned char red; 309fe5e51b7Smrg unsigned char green; 310fe5e51b7Smrg unsigned char blue; 311fe5e51b7Smrg} MGAPaletteInfo; 312fe5e51b7Smrg 313fe5e51b7Smrg#define MGAPTR(p) ((MGAPtr)((p)->driverPrivate)) 314fe5e51b7Smrg 315fe5e51b7Smrg/*avoids segfault by returning false if pMgaHwInfo not defined*/ 316fe5e51b7Smrg#define ISDIGITAL1(p) (p->pMgaHwInfo && ((p->pMgaHwInfo->ulCapsFirstOutput) & MGAHWINFOCAPS_OUTPUT_DIGITAL)) 317fe5e51b7Smrg#define ISDIGITAL2(p) (p->pMgaHwInfo && ((p->pMgaHwInfo->ulCapsSecondOutput) & MGAHWINFOCAPS_OUTPUT_DIGITAL)) 318fe5e51b7Smrg#define ISTV1(p) (p->pMgaHwInfo && ((p->pMgaHwInfo->ulCapsFirstOutput) & MGAHWINFOCAPS_OUTPUT_TV)) 319fe5e51b7Smrg#define ISTV2(p) (p->pMgaHwInfo && ((p->pMgaHwInfo->ulCapsSecondOutput) & MGAHWINFOCAPS_OUTPUT_TV)) 320fe5e51b7Smrg 321fe5e51b7Smrg 322fe5e51b7Smrg 323fe5e51b7Smrgtypedef enum { 324fe5e51b7Smrg mgaLeftOf, 325fe5e51b7Smrg mgaRightOf, 326fe5e51b7Smrg mgaAbove, 327fe5e51b7Smrg mgaBelow, 328fe5e51b7Smrg mgaClone 329fe5e51b7Smrg} MgaScrn2Rel; 330fe5e51b7Smrg 331fe5e51b7Smrgtypedef struct { 332fe5e51b7Smrg int lastInstance; 333fe5e51b7Smrg int refCount; 334fe5e51b7Smrg CARD32 masterFbAddress; 335fe5e51b7Smrg long masterFbMapSize; 336fe5e51b7Smrg CARD32 slaveFbAddress; 337fe5e51b7Smrg long slaveFbMapSize; 338fe5e51b7Smrg int mastervideoRam; 339fe5e51b7Smrg int slavevideoRam; 340fe5e51b7Smrg Bool directRenderingEnabled; 341acd6767fSmrg 342acd6767fSmrg void * mappedIOBase; 343acd6767fSmrg int mappedIOUsage; 344acd6767fSmrg 345acd6767fSmrg void * mappedILOADBase; 346acd6767fSmrg int mappedILOADUsage; 347acd6767fSmrg 348fe5e51b7Smrg ScrnInfoPtr pScrn_1; 349fe5e51b7Smrg ScrnInfoPtr pScrn_2; 350fe5e51b7Smrg} MGAEntRec, *MGAEntPtr; 351fe5e51b7Smrg 352fe5e51b7Smrg/** 353fe5e51b7Smrg * Track the range of a voltage controlled osciliator (VCO). 354fe5e51b7Smrg */ 355fe5e51b7Smrgstruct mga_VCO { 356fe5e51b7Smrg /** 357fe5e51b7Smrg * Minimum selectable frequency for this VCO, measured in kHz. 358fe5e51b7Smrg */ 359fe5e51b7Smrg unsigned min_freq; 360fe5e51b7Smrg 361fe5e51b7Smrg /** 362fe5e51b7Smrg * Maximum selectable frequency for this VCO, measured in kHz. 363fe5e51b7Smrg * 364fe5e51b7Smrg * If this value is zero, then the VCO is not available. 365fe5e51b7Smrg */ 366fe5e51b7Smrg unsigned max_freq; 367fe5e51b7Smrg}; 368fe5e51b7Smrg 369fe5e51b7Smrg/** 370fe5e51b7Smrg * Host interface types that can be set by the card's BIOS. 371fe5e51b7Smrg */ 372fe5e51b7Smrgtypedef enum { 373fe5e51b7Smrg MGA_HOST_UNKNOWN0 = 0, /**< Meaning unknown. */ 374fe5e51b7Smrg MGA_HOST_UNKNOWN1 = 1, /**< Meaning unknown. */ 375fe5e51b7Smrg MGA_HOST_UNKNOWN2 = 2, /**< Meaning unknown. */ 376fe5e51b7Smrg MGA_HOST_HYBRID = 3, /**< AGP 4x for data xfers only. */ 377fe5e51b7Smrg 378fe5e51b7Smrg /** 379fe5e51b7Smrg * PCI interface. Either native or via a universal PCI-to-PCI bridge 380fe5e51b7Smrg * chip. The PCI G450 and PCI G550 cards are examples. 381fe5e51b7Smrg */ 382fe5e51b7Smrg MGA_HOST_PCI = 4, 383fe5e51b7Smrg 384fe5e51b7Smrg MGA_HOST_AGP_1x = 5, /**< AGP 1x capable. */ 385fe5e51b7Smrg MGA_HOST_AGP_2x = 6, /**< AGP 2x capable. */ 386fe5e51b7Smrg MGA_HOST_AGP_4x = 7 /**< AGP 4x capable. */ 387fe5e51b7Smrg} mga_host_t; 388fe5e51b7Smrg 389fe5e51b7Smrg/** 3901e423a8fSmrg * Card information derived from BIOS PInS data. 391fe5e51b7Smrg */ 392fe5e51b7Smrgstruct mga_bios_values { 393fe5e51b7Smrg /** 394fe5e51b7Smrg * \name Voltage Controlled Oscilators 395fe5e51b7Smrg * \brief Track information about the various VCOs. 396fe5e51b7Smrg * 397fe5e51b7Smrg * MGA cards have between one and three VCOs that can be used to drive the 398fe5e51b7Smrg * various clocks. On older cards, only \c mga_bios_values::pixel VCO is 399fe5e51b7Smrg * available. On newer cards, such as the G450 and G550, all three are 400fe5e51b7Smrg * available. If \c mga_VCO::max_freq is zero, the VCO is not available. 401fe5e51b7Smrg */ 402fe5e51b7Smrg /*@{*/ 403fe5e51b7Smrg struct mga_VCO system; /**< System VCO. */ 404fe5e51b7Smrg struct mga_VCO pixel; /**< Pixel VCO. */ 405fe5e51b7Smrg struct mga_VCO video; /**< Video VCO. */ 406fe5e51b7Smrg /*@}*/ 407fe5e51b7Smrg 408fe5e51b7Smrg /** 409fe5e51b7Smrg * Memory clock speed, measured in kHz. 410fe5e51b7Smrg */ 411fe5e51b7Smrg unsigned mem_clock; 412fe5e51b7Smrg 413fe5e51b7Smrg /** 414fe5e51b7Smrg * PLL reference frequency value. On older cards this is ~14MHz, and on 415fe5e51b7Smrg * newer cards it is ~27MHz. 416fe5e51b7Smrg */ 417fe5e51b7Smrg unsigned pll_ref_freq; 418fe5e51b7Smrg 419fe5e51b7Smrg /** 420fe5e51b7Smrg * Some older MGA cards have a "fast bitblt" mode. This is determined 421fe5e51b7Smrg * by a capability bit stored in the PInS data. 422fe5e51b7Smrg */ 423fe5e51b7Smrg Bool fast_bitblt; 424fe5e51b7Smrg 425fe5e51b7Smrg /** 426fe5e51b7Smrg * Type of physical interface used for the card. 427fe5e51b7Smrg */ 428fe5e51b7Smrg mga_host_t host_interface; 429fe5e51b7Smrg}; 430fe5e51b7Smrg 431fe5e51b7Smrg 432fe5e51b7Smrg/** 4331e423a8fSmrg * Attributes that of an MGA device that can be derived purely from its 434fe5e51b7Smrg * PCI ID. 435fe5e51b7Smrg */ 436fe5e51b7Smrgstruct mga_device_attributes { 437fe5e51b7Smrg unsigned has_sdram:1; 438fe5e51b7Smrg unsigned probe_for_sdram:1; 439fe5e51b7Smrg unsigned dual_head_possible:1; 440fe5e51b7Smrg unsigned fb_4mb_quirk:1; 441fe5e51b7Smrg unsigned hwcursor_1064:1; 442fe5e51b7Smrg 443fe5e51b7Smrg unsigned dri_capable:1; 444fe5e51b7Smrg unsigned dri_chipset:3; 445fe5e51b7Smrg 446fe5e51b7Smrg unsigned HAL_chipset:1; 447fe5e51b7Smrg 448fe5e51b7Smrg enum { 449fe5e51b7Smrg old_BARs = 0, 450fe5e51b7Smrg probe_BARs, 451fe5e51b7Smrg new_BARs 452fe5e51b7Smrg } BARs:2; 453fe5e51b7Smrg 454fe5e51b7Smrg uint32_t accel_flags; 455eda3803bSmrg 456eda3803bSmrg /** Default BIOS values. */ 457eda3803bSmrg struct mga_bios_values default_bios_values; 458eda3803bSmrg 459eda3803bSmrg /** Default memory probe offset / size values. */ 460eda3803bSmrg unsigned probe_size; 461eda3803bSmrg unsigned probe_offset; 462fe5e51b7Smrg}; 463fe5e51b7Smrg 464fe5e51b7Smrgtypedef struct { 465fe5e51b7Smrg EntityInfoPtr pEnt; 466fe5e51b7Smrg struct mga_bios_values bios; 467fe5e51b7Smrg CARD8 BiosOutputMode; 468fe5e51b7Smrg#ifdef XSERVER_LIBPCIACCESS 469fe5e51b7Smrg struct pci_device * PciInfo; 470fe5e51b7Smrg#else 471fe5e51b7Smrg pciVideoPtr PciInfo; 472fe5e51b7Smrg PCITAG PciTag; 473643b027fSmrg xf86AccessRec Access; 474fe5e51b7Smrg#endif 475fe5e51b7Smrg const struct mga_device_attributes * chip_attribs; 476fe5e51b7Smrg int Chipset; 477fe5e51b7Smrg int ChipRev; 478fe5e51b7Smrg 479fe5e51b7Smrg int is_Gx50:1; 480fe5e51b7Smrg int is_G200SE:1; 481eda3803bSmrg int is_G200WB:1; 482eda3803bSmrg int is_G200EV:1; 483a31a186aSmrg int is_G200EH:1; 4840bb88ba4Smrg int is_G200ER:1; 485eda3803bSmrg 486eda3803bSmrg int KVM; 487eda3803bSmrg 488eda3803bSmrg CARD32 reg_1e24; /* model revision on g200se */ 489fe5e51b7Smrg 490fe5e51b7Smrg Bool Primary; 491fe5e51b7Smrg Bool Interleave; 492fe5e51b7Smrg int HwBpp; 493fe5e51b7Smrg int Roundings[4]; 494fe5e51b7Smrg int BppShifts[4]; 495fe5e51b7Smrg Bool HasFBitBlt; 496fe5e51b7Smrg Bool OverclockMem; 497fe5e51b7Smrg int YDstOrg; 498fe5e51b7Smrg int DstOrg; 499fe5e51b7Smrg int SrcOrg; 500fe5e51b7Smrg 501fe5e51b7Smrg /** 502fe5e51b7Smrg * Which BAR corresponds to the framebuffer on this chip? 503fe5e51b7Smrg */ 504fe5e51b7Smrg unsigned framebuffer_bar; 505fe5e51b7Smrg 506fe5e51b7Smrg /** 507fe5e51b7Smrg * Which BAR corresponds to IO space on this chip? 508fe5e51b7Smrg */ 509fe5e51b7Smrg unsigned io_bar; 510fe5e51b7Smrg 511fe5e51b7Smrg /** 512fe5e51b7Smrg * Which BAR corresponds to ILOAD space on this chip? If the value is 513fe5e51b7Smrg * -1, then this chip does not have an ILOAD region. 514fe5e51b7Smrg */ 515fe5e51b7Smrg int iload_bar; 516fe5e51b7Smrg 517fe5e51b7Smrg#ifndef XSERVER_LIBPCIACCESS 518fe5e51b7Smrg unsigned long IOAddress; 519fe5e51b7Smrg unsigned long ILOADAddress; 520fe5e51b7Smrg unsigned long BiosAddress; 521fe5e51b7Smrg MessageType BiosFrom; 522fe5e51b7Smrg#endif 523fe5e51b7Smrg unsigned long FbAddress; 524b0de6900Smrg void * IOBase; 525fe5e51b7Smrg unsigned char * FbBase; 526fe5e51b7Smrg unsigned char * ILOADBase; 527fe5e51b7Smrg unsigned char * FbStart; 528fe5e51b7Smrg long FbMapSize; 529fe5e51b7Smrg long FbUsableSize; 530fe5e51b7Smrg long FbCursorOffset; 531fe5e51b7Smrg MGARamdacRec Dac; 532fe5e51b7Smrg Bool HasSDRAM; 533fe5e51b7Smrg Bool NoAccel; 534fe5e51b7Smrg Bool Exa; 535fe5e51b7Smrg ExaDriverPtr ExaDriver; 536fe5e51b7Smrg Bool SyncOnGreen; 537fe5e51b7Smrg Bool HWCursor; 538fe5e51b7Smrg Bool UsePCIRetry; 539fe5e51b7Smrg Bool ShowCache; 540fe5e51b7Smrg Bool ShadowFB; 541fe5e51b7Smrg unsigned char * ShadowPtr; 542fe5e51b7Smrg int ShadowPitch; 543fe5e51b7Smrg int MemClk; 544fe5e51b7Smrg int MinClock; 545fe5e51b7Smrg int MaxClock; 546fe5e51b7Smrg MGARegRec SavedReg; 547fe5e51b7Smrg MGARegRec ModeReg; 548fe5e51b7Smrg int MaxFastBlitY; 549fe5e51b7Smrg CARD32 BltScanDirection; 550fe5e51b7Smrg CARD32 FilledRectCMD; 551fe5e51b7Smrg CARD32 SolidLineCMD; 552fe5e51b7Smrg CARD32 PatternRectCMD; 553fe5e51b7Smrg CARD32 DashCMD; 554fe5e51b7Smrg CARD32 NiceDashCMD; 555fe5e51b7Smrg CARD32 AccelFlags; 556fe5e51b7Smrg CARD32 PlaneMask; 557fe5e51b7Smrg CARD32 FgColor; 558fe5e51b7Smrg CARD32 BgColor; 559fe5e51b7Smrg CARD32 MAccess; 560fe5e51b7Smrg int FifoSize; 561fe5e51b7Smrg int StyleLen; 562b0de6900Smrg#ifdef USE_XAA 563fe5e51b7Smrg XAAInfoRecPtr AccelInfoRec; 5640bb88ba4Smrg#endif 565fe5e51b7Smrg xf86CursorInfoPtr CursorInfoRec; 566fe5e51b7Smrg DGAModePtr DGAModes; 567fe5e51b7Smrg int numDGAModes; 568fe5e51b7Smrg Bool DGAactive; 569fe5e51b7Smrg int DGAViewportStatus; 570fe5e51b7Smrg CARD32 *Atype; 571fe5e51b7Smrg CARD32 *AtypeNoBLK; 572fe5e51b7Smrg void (*PreInit)(ScrnInfoPtr pScrn); 573fe5e51b7Smrg void (*Save)(ScrnInfoPtr, vgaRegPtr, MGARegPtr, Bool); 574fe5e51b7Smrg void (*Restore)(ScrnInfoPtr, vgaRegPtr, MGARegPtr, Bool); 575fe5e51b7Smrg Bool (*ModeInit)(ScrnInfoPtr, DisplayModePtr); 5760bb88ba4Smrg void (*PointerMoved)(SCRN_ARG_TYPE arg, int x, int y); 577fe5e51b7Smrg CloseScreenProcPtr CloseScreen; 578fe5e51b7Smrg ScreenBlockHandlerProcPtr BlockHandler; 579fe5e51b7Smrg unsigned int (*ddc1Read)(ScrnInfoPtr); 580fe5e51b7Smrg void (*DDC1SetSpeed)(ScrnInfoPtr, xf86ddcSpeed); 581fe5e51b7Smrg Bool (*i2cInit)(ScrnInfoPtr); 582fe5e51b7Smrg I2CBusPtr DDC_Bus1; 583fe5e51b7Smrg I2CBusPtr DDC_Bus2; 584fe5e51b7Smrg I2CBusPtr Maven_Bus; 585fe5e51b7Smrg I2CDevPtr Maven; 586fe5e51b7Smrg char Maven_Version; 587fe5e51b7Smrg Bool UseMaven; 588fe5e51b7Smrg Bool UseMavenPM; 589fe5e51b7Smrg Bool FBDev; 590fe5e51b7Smrg int colorKey; 591fe5e51b7Smrg int videoKey; 592fe5e51b7Smrg int fifoCount; 593fe5e51b7Smrg int Rotate; 594fe5e51b7Smrg MGAFBLayout CurrentLayout; 595fe5e51b7Smrg Bool DrawTransparent; 596fe5e51b7Smrg int MaxBlitDWORDS; 597fe5e51b7Smrg Bool TexturedVideo; 598fe5e51b7Smrg MGAPortPrivPtr portPrivate; 599fe5e51b7Smrg unsigned char *ScratchBuffer; 600fe5e51b7Smrg unsigned char *ColorExpandBase; 601fe5e51b7Smrg int expandRows; 602fe5e51b7Smrg int expandDWORDs; 603fe5e51b7Smrg int expandRemaining; 604fe5e51b7Smrg int expandHeight; 605fe5e51b7Smrg int expandY; 6060bb88ba4Smrg#ifdef MGADRI 607fe5e51b7Smrg Bool directRenderingEnabled; 608fe5e51b7Smrg DRIInfoPtr pDRIInfo; 609fe5e51b7Smrg int drmFD; 610fe5e51b7Smrg MGADRIServerPrivatePtr DRIServerInfo; 611fe5e51b7Smrg 612fe5e51b7Smrg MGARegRec DRContextRegs; 613fe5e51b7Smrg 614fe5e51b7Smrg Bool haveQuiescense; 615fe5e51b7Smrg void (*GetQuiescence)(ScrnInfoPtr pScrn); 616fe5e51b7Smrg 617fe5e51b7Smrg int agpMode; 618fe5e51b7Smrg int agpSize; 619fe5e51b7Smrg 620fe5e51b7Smrg int irq; 621fe5e51b7Smrg CARD32 reg_ien; 622fe5e51b7Smrg 623fe5e51b7Smrg Bool useOldDmaInit; 624fe5e51b7Smrg Bool forcePciDma; 625fe5e51b7Smrg#endif 626fe5e51b7Smrg XF86VideoAdaptorPtr adaptor; 627fe5e51b7Smrg Bool DualHeadEnabled; 628fe5e51b7Smrg Bool Crtc2IsTV; 629fe5e51b7Smrg Bool SecondCrtc; 630fe5e51b7Smrg Bool SecondOutput; 631fe5e51b7Smrg 632fe5e51b7Smrg GDevPtr device; 633fe5e51b7Smrg /* The hardware's real SrcOrg */ 634fe5e51b7Smrg int realSrcOrg; 635fe5e51b7Smrg MGAEntPtr entityPrivate; 636fe5e51b7Smrg void (*SetupForSolidFill)(ScrnInfoPtr pScrn, int color, 637fe5e51b7Smrg int rop, unsigned int planemask); 638fe5e51b7Smrg void (*SubsequentSolidFillRect)(ScrnInfoPtr pScrn, 639fe5e51b7Smrg int x, int y, int w, int h); 640fe5e51b7Smrg void (*RestoreAccelState)(ScrnInfoPtr pScrn); 641fe5e51b7Smrg int allowedWidth; 642fe5e51b7Smrg void (*VideoTimerCallback)(ScrnInfoPtr, Time); 643fe5e51b7Smrg void (*PaletteLoadCallback)(ScrnInfoPtr); 644fe5e51b7Smrg void (*RenderCallback)(ScrnInfoPtr); 645fe5e51b7Smrg Time RenderTime; 646fe5e51b7Smrg MGAPaletteInfo palinfo[256]; /* G400 hardware bug workaround */ 647fe5e51b7Smrg FBLinearPtr LinearScratch; 648fe5e51b7Smrg Bool softbooted; 649fe5e51b7Smrg OptionInfoPtr Options; 650fe5e51b7Smrg 651fe5e51b7Smrg /* Exa */ 652fe5e51b7Smrg PicturePtr currentSrcPicture; 653fe5e51b7Smrg PicturePtr currentMaskPicture; 654fe5e51b7Smrg PixmapPtr currentSrc; 655fe5e51b7Smrg PixmapPtr currentMask; 656fe5e51b7Smrg int src_w2; 657fe5e51b7Smrg int src_h2; 658fe5e51b7Smrg int mask_w2; 659fe5e51b7Smrg int mask_h2; 660fe5e51b7Smrg CARD32 src_pitch; /* FIXME kill me */ 661fe5e51b7Smrg 662fe5e51b7Smrg/* Merged Framebuffer data */ 663fe5e51b7Smrg Bool MergedFB; 664fe5e51b7Smrg 665fe5e51b7Smrg /* Real values specific to monitor1, since the original ones are replaced */ 666fe5e51b7Smrg DisplayModePtr M1modes; /* list of actual modes */ 667fe5e51b7Smrg DisplayModePtr M1currentMode; /* current mode */ 668fe5e51b7Smrg int M1frameX0; /* viewport position */ 669fe5e51b7Smrg int M1frameY0; 670fe5e51b7Smrg int M1frameX1; 671fe5e51b7Smrg int M1frameY1; 672fe5e51b7Smrg 673fe5e51b7Smrg ScrnInfoPtr pScrn2; /*pointer to second CRTC screeninforec, 674fe5e51b7Smrg if in merged mode */ 675fe5e51b7Smrg/* End of Merged Framebuffer Data */ 676fe5e51b7Smrg int HALGranularityOffX, HALGranularityOffY; 677fe5e51b7Smrg} MGARec, *MGAPtr; 678fe5e51b7Smrg 679fe5e51b7Smrgextern CARD32 MGAAtype[16]; 680fe5e51b7Smrgextern CARD32 MGAAtypeNoBLK[16]; 681fe5e51b7Smrg 682fe5e51b7Smrg#define USE_RECTS_FOR_LINES 0x00000001 683fe5e51b7Smrg#define FASTBLT_BUG 0x00000002 684fe5e51b7Smrg#define CLIPPER_ON 0x00000004 685fe5e51b7Smrg#define BLK_OPAQUE_EXPANSION 0x00000008 686fe5e51b7Smrg#define TRANSC_SOLID_FILL 0x00000010 687fe5e51b7Smrg#define NICE_DASH_PATTERN 0x00000020 688fe5e51b7Smrg#define TWO_PASS_COLOR_EXPAND 0x00000040 689fe5e51b7Smrg#define MGA_NO_PLANEMASK 0x00000080 690acd6767fSmrg/* linear expansion doesn't work on BE due to wrong byte order */ 691acd6767fSmrg#if X_BYTE_ORDER == X_BIG_ENDIAN 692acd6767fSmrg#define USE_LINEAR_EXPANSION 0x00000000 693acd6767fSmrg#else 694fe5e51b7Smrg#define USE_LINEAR_EXPANSION 0x00000100 695acd6767fSmrg#endif 696fe5e51b7Smrg#define LARGE_ADDRESSES 0x00000200 697fe5e51b7Smrg 698fe5e51b7Smrg#define MGAIOMAPSIZE 0x00004000 699fe5e51b7Smrg#define MGAILOADMAPSIZE 0x00400000 700fe5e51b7Smrg 701fe5e51b7Smrg#define TRANSPARENCY_KEY 255 702fe5e51b7Smrg#define KEY_COLOR 0 703fe5e51b7Smrg 704fe5e51b7Smrg 705fe5e51b7Smrg/* Prototypes */ 706fe5e51b7Smrg 7070bb88ba4Smrgvoid MGAAdjustFrame(ADJUST_FRAME_ARGS_DECL); 7080bb88ba4SmrgBool MGASwitchMode(SWITCH_MODE_ARGS_DECL); 709fe5e51b7Smrgvoid MGAFillModeInfoStruct(ScrnInfoPtr pScrn, DisplayModePtr mode); 710fe5e51b7SmrgBool MGAGetRec(ScrnInfoPtr pScrn); 711fe5e51b7Smrgvoid MGAProbeDDC(ScrnInfoPtr pScrn, int index); 712fe5e51b7Smrgvoid MGASoftReset(ScrnInfoPtr pScrn); 713fe5e51b7Smrgvoid MGAFreeRec(ScrnInfoPtr pScrn); 714fe5e51b7SmrgBool mga_read_and_process_bios(ScrnInfoPtr pScrn); 715fe5e51b7Smrgvoid MGADisplayPowerManagementSet(ScrnInfoPtr pScrn, int PowerManagementMode, 716fe5e51b7Smrg int flags); 7170bb88ba4Smrgvoid MGAAdjustFrameCrtc2(ADJUST_FRAME_ARGS_DECL); 718fe5e51b7Smrgvoid MGADisplayPowerManagementSetCrtc2(ScrnInfoPtr pScrn, 719fe5e51b7Smrg int PowerManagementMode, 720fe5e51b7Smrg int flags); 721fe5e51b7Smrgvoid MGAAdjustGranularity(ScrnInfoPtr pScrn, int* x, int* y); 722fe5e51b7Smrg 723fe5e51b7Smrg 724fe5e51b7Smrgvoid MGA2064SetupFuncs(ScrnInfoPtr pScrn); 725fe5e51b7Smrgvoid MGAGSetupFuncs(ScrnInfoPtr pScrn); 726fe5e51b7Smrg 7270bb88ba4Smrg/*#ifdef USE_XAA */ 728fe5e51b7Smrgvoid MGAStormSync(ScrnInfoPtr pScrn); 729fe5e51b7Smrgvoid MGAStormEngineInit(ScrnInfoPtr pScrn); 730fe5e51b7SmrgBool MGAStormAccelInit(ScreenPtr pScreen); 731fe5e51b7SmrgBool mgaAccelInit(ScreenPtr pScreen); 732fe5e51b7Smrg/* #endif */ 733fe5e51b7Smrg 734fe5e51b7Smrg#ifdef USE_EXA 735fe5e51b7SmrgBool mgaExaInit(ScreenPtr pScreen); 736fe5e51b7Smrg#endif 737fe5e51b7Smrg 738fe5e51b7SmrgBool MGAHWCursorInit(ScreenPtr pScreen); 739fe5e51b7Smrg 740b0de6900Smrg#ifdef USE_XAA 741fe5e51b7Smrgvoid MGAPolyArcThinSolid(DrawablePtr, GCPtr, int, xArc*); 742b0de6900Smrg#endif /* USE_XAA */ 743fe5e51b7Smrg 744fe5e51b7SmrgBool MGADGAInit(ScreenPtr pScreen); 745fe5e51b7Smrg 746fe5e51b7Smrgvoid MGARefreshArea(ScrnInfoPtr pScrn, int num, BoxPtr pbox); 747fe5e51b7Smrgvoid MGARefreshArea8(ScrnInfoPtr pScrn, int num, BoxPtr pbox); 748fe5e51b7Smrgvoid MGARefreshArea16(ScrnInfoPtr pScrn, int num, BoxPtr pbox); 749fe5e51b7Smrgvoid MGARefreshArea24(ScrnInfoPtr pScrn, int num, BoxPtr pbox); 750fe5e51b7Smrgvoid MGARefreshArea32(ScrnInfoPtr pScrn, int num, BoxPtr pbox); 751fe5e51b7Smrg 752fe5e51b7Smrgvoid mgaDoSetupForScreenToScreenCopy( ScrnInfoPtr pScrn, int xdir, 753fe5e51b7Smrg int ydir, int rop, unsigned int planemask, int trans, unsigned int bpp ); 754fe5e51b7Smrg 755fe5e51b7Smrgvoid mgaDoSetupForSolidFill( ScrnInfoPtr pScrn, int color, int rop, 756fe5e51b7Smrg unsigned int planemask, unsigned int bpp ); 757fe5e51b7Smrg 7580bb88ba4Smrgvoid MGAPointerMoved(SCRN_ARG_TYPE arg, int x, int y); 759fe5e51b7Smrg 760fe5e51b7Smrgvoid MGAInitVideo(ScreenPtr pScreen); 761fe5e51b7Smrgvoid MGAResetVideo(ScrnInfoPtr pScrn); 762fe5e51b7Smrg 7630bb88ba4Smrg#ifdef MGADRI 764fe5e51b7Smrg 765fe5e51b7Smrg#define MGA_FRONT 0x1 766fe5e51b7Smrg#define MGA_BACK 0x2 767fe5e51b7Smrg#define MGA_DEPTH 0x4 768fe5e51b7Smrg 769fe5e51b7SmrgBool MGADRIScreenInit( ScreenPtr pScreen ); 770fe5e51b7Smrgvoid MGADRICloseScreen( ScreenPtr pScreen ); 771fe5e51b7SmrgBool MGADRIFinishScreenInit( ScreenPtr pScreen ); 772fe5e51b7Smrg 773fe5e51b7SmrgBool MGALockUpdate( ScrnInfoPtr pScrn, drmLockFlags flags ); 774fe5e51b7Smrg 775fe5e51b7Smrgvoid MGAGetQuiescence( ScrnInfoPtr pScrn ); 776fe5e51b7Smrgvoid MGAGetQuiescenceShared( ScrnInfoPtr pScrn ); 777fe5e51b7Smrg 778fe5e51b7Smrgvoid MGASelectBuffer(ScrnInfoPtr pScrn, int which); 779fe5e51b7SmrgBool MgaCleanupDma(ScrnInfoPtr pScrn); 780fe5e51b7SmrgBool MgaInitDma(ScrnInfoPtr pScrn, int prim_size); 781fe5e51b7Smrg 782fe5e51b7Smrg#define MGA_AGP_1X_MODE 0x01 783fe5e51b7Smrg#define MGA_AGP_2X_MODE 0x02 784fe5e51b7Smrg#define MGA_AGP_4X_MODE 0x04 785fe5e51b7Smrg#define MGA_AGP_MODE_MASK 0x07 786fe5e51b7Smrg 787fe5e51b7Smrg#endif 788fe5e51b7Smrg 789fe5e51b7SmrgBool MGAMavenRead(ScrnInfoPtr pScrn, I2CByte reg, I2CByte *val); 790fe5e51b7Smrg 791fe5e51b7Smrgvoid MGACRTC2Set(ScrnInfoPtr pScrn, xMODEINFO *pModeInfo); 792fe5e51b7Smrgvoid MGAEnableSecondOutPut(ScrnInfoPtr pScrn, xMODEINFO *pModeInfo); 793fe5e51b7Smrgvoid MGACRTC2SetPitch(ScrnInfoPtr pSrcn, xMODEINFO *pModeInfo); 794fe5e51b7Smrgvoid MGACRTC2SetDisplayStart(ScrnInfoPtr pScrn, xMODEINFO *pModeInfo, CARD32 base, CARD32 ulX, CARD32 ulY); 795fe5e51b7Smrg 796fe5e51b7Smrgvoid MGACRTC2Get(ScrnInfoPtr pScrn, xMODEINFO *pModeInfo); 797fe5e51b7Smrgvoid MGACRTC2GetPitch(ScrnInfoPtr pSrcn, xMODEINFO *pModeInfo); 798fe5e51b7Smrgvoid MGACRTC2GetDisplayStart(ScrnInfoPtr pScrn, xMODEINFO *pModeInfo, CARD32 base, CARD32 ulX, CARD32 ulY); 799fe5e51b7Smrg 800fe5e51b7Smrgdouble MGAG450SetPLLFreq(ScrnInfoPtr pScrn, long f_out); 801fe5e51b7Smrg#ifdef DEBUG 802fe5e51b7Smrgvoid MGAG450PrintPLL(ScrnInfoPtr pScrn); 803fe5e51b7Smrg#endif 804fe5e51b7Smrglong MGAG450SavePLLFreq(ScrnInfoPtr pScrn); 805fe5e51b7Smrgvoid MGAprintDac(ScrnInfoPtr pScrn); 806fe5e51b7Smrgvoid MGAG200SESaveFonts(ScrnInfoPtr, vgaRegPtr); 807fe5e51b7Smrgvoid MGAG200SERestoreFonts(ScrnInfoPtr, vgaRegPtr); 808fe5e51b7Smrgvoid MGAG200SESaveMode(ScrnInfoPtr, vgaRegPtr); 809fe5e51b7Smrgvoid MGAG200SERestoreMode(ScrnInfoPtr, vgaRegPtr); 810fe5e51b7Smrgvoid MGAG200SEHWProtect(ScrnInfoPtr, Bool); 811fe5e51b7Smrg 812fe5e51b7Smrgstatic __inline__ void 813fe5e51b7SmrgMGA_MARK_SYNC(MGAPtr pMga, ScrnInfoPtr pScrn) 814fe5e51b7Smrg{ 815fe5e51b7Smrg#ifdef USE_EXA 816fe5e51b7Smrg if (pMga->Exa) 817fe5e51b7Smrg exaMarkSync(pScrn->pScreen); 818fe5e51b7Smrg#endif 819fe5e51b7Smrg#ifdef USE_XAA 820fe5e51b7Smrg if (!pMga->Exa) 821fe5e51b7Smrg SET_SYNC_FLAG(pMga->AccelInfoRec); 822fe5e51b7Smrg#endif 823fe5e51b7Smrg} 824fe5e51b7Smrg 825fe5e51b7Smrgstatic __inline__ void 826fe5e51b7SmrgMGA_SYNC(MGAPtr pMga, ScrnInfoPtr pScrn) 827fe5e51b7Smrg{ 828fe5e51b7Smrg#ifdef USE_EXA 829fe5e51b7Smrg if (pMga->Exa) 830fe5e51b7Smrg exaWaitSync(pScrn->pScreen); 831fe5e51b7Smrg#endif 832fe5e51b7Smrg#ifdef USE_XAA 833fe5e51b7Smrg if (!pMga->Exa && pMga->AccelInfoRec && pMga->AccelInfoRec->NeedToSync) 834fe5e51b7Smrg pMga->AccelInfoRec->Sync(pScrn); 835fe5e51b7Smrg#endif 836fe5e51b7Smrg} 837fe5e51b7Smrg 838fe5e51b7Smrg#endif 839