mga.h revision 493f84f4
1fe5e51b7Smrg/*
2fe5e51b7Smrg * MGA Millennium (MGA2064W) functions
3fe5e51b7Smrg *
4fe5e51b7Smrg * Copyright 1996 The XFree86 Project, Inc.
5fe5e51b7Smrg *
6fe5e51b7Smrg * Authors
7fe5e51b7Smrg *		Dirk Hohndel
8fe5e51b7Smrg *			hohndel@XFree86.Org
9fe5e51b7Smrg *		David Dawes
10fe5e51b7Smrg *			dawes@XFree86.Org
11fe5e51b7Smrg */
12fe5e51b7Smrg
13fe5e51b7Smrg#ifndef MGA_H
14fe5e51b7Smrg#define MGA_H
15fe5e51b7Smrg
16fe5e51b7Smrg#ifdef XSERVER_LIBPCIACCESS
17fe5e51b7Smrg#include <pciaccess.h>
18fe5e51b7Smrg#endif
19fe5e51b7Smrg#include <string.h>
20fe5e51b7Smrg#include <stdio.h>
21fe5e51b7Smrg
22fe5e51b7Smrg#include "compiler.h"
230bb88ba4Smrg#ifdef HAVE_XAA_H
24fe5e51b7Smrg#include "xaa.h"
250bb88ba4Smrg#endif
260bb88ba4Smrg#include "xf86fbman.h"
27fe5e51b7Smrg#include "exa.h"
28fe5e51b7Smrg#include "xf86Cursor.h"
29fe5e51b7Smrg#include "vgaHW.h"
30fe5e51b7Smrg#include "colormapst.h"
31fe5e51b7Smrg#include "xf86DDC.h"
32fe5e51b7Smrg#include "xf86xv.h"
33fe5e51b7Smrg
340bb88ba4Smrg#ifndef XF86DRI
350bb88ba4Smrg#undef MGADRI
360bb88ba4Smrg#endif
370bb88ba4Smrg
380bb88ba4Smrg#ifdef MGADRI
39fe5e51b7Smrg#include "xf86drm.h"
40fe5e51b7Smrg
41fe5e51b7Smrg#define _XF86DRI_SERVER_
42fe5e51b7Smrg#include "mga_dripriv.h"
43fe5e51b7Smrg#include "dri.h"
44fe5e51b7Smrg#include "GL/glxint.h"
45fe5e51b7Smrg
46fe5e51b7Smrg#include "dri.h"
47fe5e51b7Smrg
48fe5e51b7Smrg#include "GL/glxint.h"
49fe5e51b7Smrg#include "mga_dri.h"
50fe5e51b7Smrg#endif
51fe5e51b7Smrg
520bb88ba4Smrg#include "compat-api.h"
53fe5e51b7Smrg
54fe5e51b7Smrgtypedef enum {
55fe5e51b7Smrg    OPTION_SW_CURSOR,
56fe5e51b7Smrg    OPTION_HW_CURSOR,
57fe5e51b7Smrg    OPTION_PCI_RETRY,
58fe5e51b7Smrg    OPTION_SYNC_ON_GREEN,
59fe5e51b7Smrg    OPTION_NOACCEL,
60fe5e51b7Smrg    OPTION_SHOWCACHE,
61fe5e51b7Smrg    OPTION_OVERLAY,
62fe5e51b7Smrg    OPTION_MGA_SDRAM,
63fe5e51b7Smrg    OPTION_SHADOW_FB,
64fe5e51b7Smrg    OPTION_FBDEV,
65fe5e51b7Smrg    OPTION_COLOR_KEY,
66fe5e51b7Smrg    OPTION_SET_MCLK,
67fe5e51b7Smrg    OPTION_OVERCLOCK_MEM,
68fe5e51b7Smrg    OPTION_VIDEO_KEY,
69fe5e51b7Smrg    OPTION_ROTATE,
70fe5e51b7Smrg    OPTION_TEXTURED_VIDEO,
71fe5e51b7Smrg    OPTION_CRTC2HALF,
72fe5e51b7Smrg    OPTION_CRTC2RAM,
73fe5e51b7Smrg    OPTION_INT10,
74fe5e51b7Smrg    OPTION_AGP_MODE,
75fe5e51b7Smrg    OPTION_AGP_SIZE,
76fe5e51b7Smrg    OPTION_DIGITAL1,
77fe5e51b7Smrg    OPTION_DIGITAL2,
78fe5e51b7Smrg    OPTION_TV,
79fe5e51b7Smrg    OPTION_TVSTANDARD,
80fe5e51b7Smrg    OPTION_CABLETYPE,
81fe5e51b7Smrg    OPTION_USEIRQZERO,
82fe5e51b7Smrg    OPTION_NOHAL,
83fe5e51b7Smrg    OPTION_SWAPPED_HEAD,
84fe5e51b7Smrg    OPTION_DRI,
85fe5e51b7Smrg    OPTION_MERGEDFB,
86fe5e51b7Smrg    OPTION_HSYNC2,
87fe5e51b7Smrg    OPTION_VREFRESH2,
88fe5e51b7Smrg    OPTION_MONITOR2POS,
89fe5e51b7Smrg    OPTION_METAMODES,
90fe5e51b7Smrg    OPTION_OLDDMA,
91fe5e51b7Smrg    OPTION_PCIDMA,
92eda3803bSmrg    OPTION_ACCELMETHOD,
93eda3803bSmrg    OPTION_KVM
94fe5e51b7Smrg} MGAOpts;
95fe5e51b7Smrg
96fe5e51b7Smrg
97fe5e51b7Smrg#if !defined(EXTRADEBUG)
98fe5e51b7Smrg#define INREG8(addr) MMIO_IN8(pMga->IOBase, addr)
99fe5e51b7Smrg#define INREG16(addr) MMIO_IN16(pMga->IOBase, addr)
100fe5e51b7Smrg#define INREG(addr) MMIO_IN32(pMga->IOBase, addr)
101fe5e51b7Smrg#define OUTREG8(addr, val) MMIO_OUT8(pMga->IOBase, addr, val)
102fe5e51b7Smrg#define OUTREG16(addr, val) MMIO_OUT16(pMga->IOBase, addr, val)
103fe5e51b7Smrg#define OUTREG(addr, val) MMIO_OUT32(pMga->IOBase, addr, val)
104fe5e51b7Smrg#else /* !EXTRADEBUG */
105fe5e51b7SmrgCARD8 MGAdbg_inreg8(ScrnInfoPtr, int, int, char*);
106fe5e51b7SmrgCARD16 MGAdbg_inreg16(ScrnInfoPtr, int, int, char*);
107fe5e51b7SmrgCARD32 MGAdbg_inreg32(ScrnInfoPtr, int, int, char*);
108fe5e51b7Smrgvoid MGAdbg_outreg8(ScrnInfoPtr, int, int, char*);
109fe5e51b7Smrgvoid MGAdbg_outreg16(ScrnInfoPtr, int,int, char*);
110fe5e51b7Smrgvoid MGAdbg_outreg32(ScrnInfoPtr, int,int, char*);
111fe5e51b7Smrg#ifndef __GNUC__
112fe5e51b7Smrg# define MGA_STRINGIZE(x) #x
113fe5e51b7Smrg# define MGA_STRINGIFY(x) MGA_STRINGIZE(x)
114fe5e51b7Smrg# define __FUNCTION__ MGA_STRINGIFY(__FILE__) ", line " MGA_STRINGIFY(__LINE__)
115fe5e51b7Smrg#endif
116fe5e51b7Smrg#define INREG8(addr) MGAdbg_inreg8(pScrn, addr, 1, __FUNCTION__)
117fe5e51b7Smrg#define INREG16(addr) MGAdbg_inreg16(pScrn, addr, 1, __FUNCTION__)
118fe5e51b7Smrg#define INREG(addr) MGAdbg_inreg32(pScrn, addr, 1, __FUNCTION__)
119fe5e51b7Smrg#define OUTREG8(addr,val) MGAdbg_outreg8(pScrn, addr, val, __FUNCTION__)
120fe5e51b7Smrg#define OUTREG16(addr,val) MGAdbg_outreg16(pScrn, addr, val, __FUNCTION__)
121fe5e51b7Smrg#define OUTREG(addr,val) MGAdbg_outreg32(pScrn, addr, val, __FUNCTION__)
122fe5e51b7Smrg#endif /* EXTRADEBUG */
123fe5e51b7Smrg
1240bb88ba4Smrg/*
1250bb88ba4Smrg * PCI vendor/device ids, formerly in xf86PciInfo.h
1260bb88ba4Smrg */
127eda3803bSmrg
1280bb88ba4Smrg#define PCI_VENDOR_MATROX               0x102B
1290bb88ba4Smrg
1300bb88ba4Smrg#define PCI_CHIP_MGA2085                0x0518
1310bb88ba4Smrg#define PCI_CHIP_MGA2064                0x0519
1320bb88ba4Smrg#define PCI_CHIP_MGA1064                0x051A
1330bb88ba4Smrg#define PCI_CHIP_MGA2164                0x051B
1340bb88ba4Smrg#define PCI_CHIP_MGA2164_AGP            0x051F
1350bb88ba4Smrg
1360bb88ba4Smrg#define PCI_CHIP_MGAG100_PCI            0x1000
1370bb88ba4Smrg#define PCI_CHIP_MGAG100                0x1001
1380bb88ba4Smrg#define PCI_CHIP_MGAG200_PCI            0x0520
1390bb88ba4Smrg#define PCI_CHIP_MGAG200                0x0521
1400bb88ba4Smrg#define PCI_CHIP_MGAG200_SE_A_PCI       0x0522
1410bb88ba4Smrg#define PCI_CHIP_MGAG200_SE_B_PCI       0x0524
1420bb88ba4Smrg#define PCI_CHIP_MGAG200_WINBOND_PCI    0x0532
1430bb88ba4Smrg#define PCI_CHIP_MGAG200_EV_PCI         0x0530
1440bb88ba4Smrg#define PCI_CHIP_MGAG200_EH_PCI         0x0533
1450bb88ba4Smrg#define PCI_CHIP_MGAG200_ER_PCI         0x0534
1460bb88ba4Smrg#define PCI_CHIP_MGAG400                0x0525
1470bb88ba4Smrg#define PCI_CHIP_MGAG550                0x2527
148a31a186aSmrg
149fe5e51b7Smrg/*
150fe5e51b7Smrg * Read/write to the DAC via MMIO
151fe5e51b7Smrg */
152fe5e51b7Smrg
153fe5e51b7Smrg/*
154fe5e51b7Smrg * These were functions.  Use macros instead to avoid the need to
155fe5e51b7Smrg * pass pMga to them.
156fe5e51b7Smrg */
157fe5e51b7Smrg
158fe5e51b7Smrg#define inMGAdreg(reg) INREG8(RAMDAC_OFFSET + (reg))
159fe5e51b7Smrg
160fe5e51b7Smrg#define outMGAdreg(reg, val) OUTREG8(RAMDAC_OFFSET + (reg), val)
161fe5e51b7Smrg
162fe5e51b7Smrg#define inMGAdac(reg) \
163fe5e51b7Smrg	(outMGAdreg(MGA1064_INDEX, reg), inMGAdreg(MGA1064_DATA))
164fe5e51b7Smrg
165fe5e51b7Smrg#define outMGAdac(reg, val) \
166fe5e51b7Smrg	(outMGAdreg(MGA1064_INDEX, reg), outMGAdreg(MGA1064_DATA, val))
167fe5e51b7Smrg
168fe5e51b7Smrg#define outMGAdacmsk(reg, mask, val) \
169fe5e51b7Smrg	do { /* note: mask and reg may get evaluated twice */ \
170fe5e51b7Smrg	    unsigned char tmp = (mask) ? (inMGAdac(reg) & (mask)) : 0; \
171fe5e51b7Smrg	    outMGAdreg(MGA1064_INDEX, reg); \
172fe5e51b7Smrg	    outMGAdreg(MGA1064_DATA, tmp | (val)); \
173fe5e51b7Smrg	} while (0)
174fe5e51b7Smrg
175fe5e51b7Smrg#define MGAWAITVSYNC() \
176fe5e51b7Smrg    do { \
177fe5e51b7Smrg	unsigned int count = 0; \
178fe5e51b7Smrg    	unsigned int status = 0; \
179fe5e51b7Smrg	do { \
180fe5e51b7Smrg	    status = INREG( MGAREG_Status ); \
181fe5e51b7Smrg	    count++; \
182fe5e51b7Smrg    	} while( ( status & 0x08 ) && (count < 250000) );\
183fe5e51b7Smrg	count = 0; \
184fe5e51b7Smrg    	status = 0; \
185fe5e51b7Smrg	do { \
186fe5e51b7Smrg	    status = INREG( MGAREG_Status ); \
187fe5e51b7Smrg	    count++; \
188fe5e51b7Smrg    	} while( !( status & 0x08 ) && (count < 250000) );\
189fe5e51b7Smrg    } while (0)
190fe5e51b7Smrg
191fe5e51b7Smrg#define MGAWAITBUSY() \
192fe5e51b7Smrg    do { \
193fe5e51b7Smrg    	unsigned int count = 0; \
194fe5e51b7Smrg	unsigned int status = 0; \
195fe5e51b7Smrg    	do { \
196fe5e51b7Smrg    	    status = INREG8( MGAREG_Status + 2 ); \
197fe5e51b7Smrg	    count++; \
198fe5e51b7Smrg    	} while( ( status & 0x01 ) && (count < 500000) ); \
199fe5e51b7Smrg    } while (0)
200fe5e51b7Smrg
201fe5e51b7Smrg#define PORT_OFFSET 	(0x1F00 - 0x300)
202fe5e51b7Smrg
203fe5e51b7Smrg#define MGA_VERSION 4000
204fe5e51b7Smrg#define MGA_NAME "MGA"
205fe5e51b7Smrg#define MGA_C_NAME MGA
206fe5e51b7Smrg#define MGA_MODULE_DATA mgaModuleData
207fe5e51b7Smrg#define MGA_DRIVER_NAME "mga"
208fe5e51b7Smrg
209fe5e51b7Smrgtypedef struct {
210fe5e51b7Smrg    unsigned char	ExtVga[6];
211fe5e51b7Smrg    unsigned char 	DacClk[6];
2120bb88ba4Smrg    unsigned char	ExtVga_Index24;
2130bb88ba4Smrg    unsigned char	Dac_Index90;
2140bb88ba4Smrg    unsigned char * DacRegs;
215fe5e51b7Smrg    unsigned long	crtc2[0x58];
216fe5e51b7Smrg    unsigned char	dac2[0x21];
217fe5e51b7Smrg    CARD32		Option;
218fe5e51b7Smrg    CARD32		Option2;
219fe5e51b7Smrg    CARD32		Option3;
220fe5e51b7Smrg    long                Clock;
221493f84f4Smrg    unsigned char	Pan_Ctl;
222fe5e51b7Smrg    Bool                PIXPLLCSaved;
223eda3803bSmrg    unsigned char       PllM;
224eda3803bSmrg    unsigned char       PllN;
225eda3803bSmrg    unsigned char       PllP;
226fe5e51b7Smrg} MGARegRec, *MGARegPtr;
227fe5e51b7Smrg
228fe5e51b7Smrg/* For programming the second CRTC */
229fe5e51b7Smrgtypedef struct {
230fe5e51b7Smrg   CARD32   ulDispWidth;        /* Display Width in pixels*/
231fe5e51b7Smrg   CARD32   ulDispHeight;       /* Display Height in pixels*/
232fe5e51b7Smrg   CARD32   ulBpp;              /* Bits Per Pixels / input format*/
233fe5e51b7Smrg   CARD32   ulPixClock;         /* Pixel Clock in kHz*/
234fe5e51b7Smrg   CARD32   ulHFPorch;          /* Horizontal front porch in pixels*/
235fe5e51b7Smrg   CARD32   ulHSync;            /* Horizontal Sync in pixels*/
236fe5e51b7Smrg   CARD32   ulHBPorch;          /* Horizontal back porch in pixels*/
237fe5e51b7Smrg   CARD32   ulVFPorch;          /* Vertical front porch in lines*/
238fe5e51b7Smrg   CARD32   ulVSync;            /* Vertical Sync in lines*/
239fe5e51b7Smrg   CARD32   ulVBPorch;          /* Vertical back Porch in lines*/
240fe5e51b7Smrg   CARD32   ulFBPitch;          /* Pitch*/
241fe5e51b7Smrg   CARD32   flSignalMode;       /* Signal Mode*/
242fe5e51b7Smrg} xMODEINFO;
243fe5e51b7Smrg
244fe5e51b7Smrg
245fe5e51b7Smrgtypedef struct {
246fe5e51b7Smrg   int          brightness;
247fe5e51b7Smrg   int          contrast;
248fe5e51b7Smrg   Bool         doubleBuffer;
249fe5e51b7Smrg   unsigned char currentBuffer;
250fe5e51b7Smrg   RegionRec	clip;
251fe5e51b7Smrg   CARD32	colorKey;
252fe5e51b7Smrg   CARD32	videoStatus;
253fe5e51b7Smrg   Time		offTime;
254fe5e51b7Smrg   Time		freeTime;
255fe5e51b7Smrg   int		lastPort;
256fe5e51b7Smrg
257fe5e51b7Smrg#ifdef USE_EXA
258fe5e51b7Smrg   int              size;
259fe5e51b7Smrg   ExaOffscreenArea *off_screen;
260fe5e51b7Smrg#endif
261fe5e51b7Smrg
262fe5e51b7Smrg   void         *video_memory;
263fe5e51b7Smrg   int           video_offset;
264fe5e51b7Smrg} MGAPortPrivRec, *MGAPortPrivPtr;
265fe5e51b7Smrg
266fe5e51b7Smrgtypedef struct {
267fe5e51b7Smrg    Bool	isHwCursor;
268fe5e51b7Smrg    int		CursorMaxWidth;
269fe5e51b7Smrg    int 	CursorMaxHeight;
270fe5e51b7Smrg    int		CursorFlags;
271fe5e51b7Smrg    int		CursorOffscreenMemSize;
272fe5e51b7Smrg    Bool	(*UseHWCursor)(ScreenPtr, CursorPtr);
273fe5e51b7Smrg    void	(*LoadCursorImage)(ScrnInfoPtr, unsigned char*);
274fe5e51b7Smrg    void	(*ShowCursor)(ScrnInfoPtr);
275fe5e51b7Smrg    void	(*HideCursor)(ScrnInfoPtr);
276fe5e51b7Smrg    void	(*SetCursorPosition)(ScrnInfoPtr, int, int);
277fe5e51b7Smrg    void	(*SetCursorColors)(ScrnInfoPtr, int, int);
278fe5e51b7Smrg    long	maxPixelClock;
279fe5e51b7Smrg    long	MemoryClock;
280fe5e51b7Smrg    MessageType ClockFrom;
281fe5e51b7Smrg    MessageType MemClkFrom;
282fe5e51b7Smrg    Bool	SetMemClk;
283fe5e51b7Smrg    void	(*LoadPalette)(ScrnInfoPtr, int, int*, LOCO*, VisualPtr);
284fe5e51b7Smrg    void	(*RestorePalette)(ScrnInfoPtr, unsigned char *);
285fe5e51b7Smrg    void	(*PreInit)(ScrnInfoPtr);
286fe5e51b7Smrg    void	(*Save)(ScrnInfoPtr, vgaRegPtr, MGARegPtr, Bool);
287fe5e51b7Smrg    void	(*Restore)(ScrnInfoPtr, vgaRegPtr, MGARegPtr, Bool);
288fe5e51b7Smrg    Bool	(*ModeInit)(ScrnInfoPtr, DisplayModePtr);
289fe5e51b7Smrg} MGARamdacRec, *MGARamdacPtr;
290fe5e51b7Smrg
291fe5e51b7Smrg
292fe5e51b7Smrgtypedef struct {
293fe5e51b7Smrg    int bitsPerPixel;
294fe5e51b7Smrg    int depth;
295fe5e51b7Smrg    int displayWidth;
296fe5e51b7Smrg    rgb weight;
297fe5e51b7Smrg    DisplayModePtr mode;
298fe5e51b7Smrg} MGAFBLayout;
299fe5e51b7Smrg
300fe5e51b7Smrg/* Card-specific driver information */
301fe5e51b7Smrg
302fe5e51b7Smrgtypedef struct {
303fe5e51b7Smrg    Bool update;
304fe5e51b7Smrg    unsigned char red;
305fe5e51b7Smrg    unsigned char green;
306fe5e51b7Smrg    unsigned char blue;
307fe5e51b7Smrg} MGAPaletteInfo;
308fe5e51b7Smrg
309fe5e51b7Smrg#define MGAPTR(p) ((MGAPtr)((p)->driverPrivate))
310fe5e51b7Smrg
311fe5e51b7Smrg/*avoids segfault by returning false if pMgaHwInfo not defined*/
312fe5e51b7Smrg#define ISDIGITAL1(p) (p->pMgaHwInfo && ((p->pMgaHwInfo->ulCapsFirstOutput) & MGAHWINFOCAPS_OUTPUT_DIGITAL))
313fe5e51b7Smrg#define ISDIGITAL2(p) (p->pMgaHwInfo && ((p->pMgaHwInfo->ulCapsSecondOutput) & MGAHWINFOCAPS_OUTPUT_DIGITAL))
314fe5e51b7Smrg#define ISTV1(p) (p->pMgaHwInfo && ((p->pMgaHwInfo->ulCapsFirstOutput) & MGAHWINFOCAPS_OUTPUT_TV))
315fe5e51b7Smrg#define ISTV2(p) (p->pMgaHwInfo && ((p->pMgaHwInfo->ulCapsSecondOutput) & MGAHWINFOCAPS_OUTPUT_TV))
316fe5e51b7Smrg
317fe5e51b7Smrg
318fe5e51b7Smrg
319fe5e51b7Smrgtypedef enum {
320fe5e51b7Smrg    mgaLeftOf,
321fe5e51b7Smrg    mgaRightOf,
322fe5e51b7Smrg    mgaAbove,
323fe5e51b7Smrg    mgaBelow,
324fe5e51b7Smrg    mgaClone
325fe5e51b7Smrg} MgaScrn2Rel;
326fe5e51b7Smrg
327fe5e51b7Smrgtypedef struct {
328fe5e51b7Smrg    int			lastInstance;
329fe5e51b7Smrg    int			refCount;
330fe5e51b7Smrg    CARD32		masterFbAddress;
331fe5e51b7Smrg    long		masterFbMapSize;
332fe5e51b7Smrg    CARD32		slaveFbAddress;
333fe5e51b7Smrg    long		slaveFbMapSize;
334fe5e51b7Smrg    int			mastervideoRam;
335fe5e51b7Smrg    int			slavevideoRam;
336fe5e51b7Smrg    Bool		directRenderingEnabled;
337acd6767fSmrg
338acd6767fSmrg    void *		mappedIOBase;
339acd6767fSmrg    int			mappedIOUsage;
340acd6767fSmrg
341acd6767fSmrg    void *		mappedILOADBase;
342acd6767fSmrg    int			mappedILOADUsage;
343acd6767fSmrg
344fe5e51b7Smrg    ScrnInfoPtr 	pScrn_1;
345fe5e51b7Smrg    ScrnInfoPtr 	pScrn_2;
346fe5e51b7Smrg} MGAEntRec, *MGAEntPtr;
347fe5e51b7Smrg
348fe5e51b7Smrg/**
349fe5e51b7Smrg * Track the range of a voltage controlled osciliator (VCO).
350fe5e51b7Smrg */
351fe5e51b7Smrgstruct mga_VCO {
352fe5e51b7Smrg    /**
353fe5e51b7Smrg     * Minimum selectable frequency for this VCO, measured in kHz.
354fe5e51b7Smrg     */
355fe5e51b7Smrg    unsigned min_freq;
356fe5e51b7Smrg
357fe5e51b7Smrg    /**
358fe5e51b7Smrg     * Maximum selectable frequency for this VCO, measured in kHz.
359fe5e51b7Smrg     *
360fe5e51b7Smrg     * If this value is zero, then the VCO is not available.
361fe5e51b7Smrg     */
362fe5e51b7Smrg    unsigned max_freq;
363fe5e51b7Smrg};
364fe5e51b7Smrg
365fe5e51b7Smrg/**
366fe5e51b7Smrg * Host interface types that can be set by the card's BIOS.
367fe5e51b7Smrg */
368fe5e51b7Smrgtypedef enum {
369fe5e51b7Smrg    MGA_HOST_UNKNOWN0 = 0,  /**< Meaning unknown. */
370fe5e51b7Smrg    MGA_HOST_UNKNOWN1 = 1,  /**< Meaning unknown. */
371fe5e51b7Smrg    MGA_HOST_UNKNOWN2 = 2,  /**< Meaning unknown. */
372fe5e51b7Smrg    MGA_HOST_HYBRID = 3,    /**< AGP 4x for data xfers only. */
373fe5e51b7Smrg
374fe5e51b7Smrg    /**
375fe5e51b7Smrg     * PCI interface.  Either native or via a universal PCI-to-PCI bridge
376fe5e51b7Smrg     * chip.  The PCI G450 and PCI G550 cards are examples.
377fe5e51b7Smrg     */
378fe5e51b7Smrg    MGA_HOST_PCI = 4,
379fe5e51b7Smrg
380fe5e51b7Smrg    MGA_HOST_AGP_1x = 5,    /**< AGP 1x capable. */
381fe5e51b7Smrg    MGA_HOST_AGP_2x = 6,    /**< AGP 2x capable. */
382fe5e51b7Smrg    MGA_HOST_AGP_4x = 7     /**< AGP 4x capable. */
383fe5e51b7Smrg} mga_host_t;
384fe5e51b7Smrg
385fe5e51b7Smrg/**
386fe5e51b7Smrg * Card information derrived from BIOS PInS data.
387fe5e51b7Smrg */
388fe5e51b7Smrgstruct mga_bios_values {
389fe5e51b7Smrg    /**
390fe5e51b7Smrg     * \name Voltage Controlled Oscilators
391fe5e51b7Smrg     * \brief Track information about the various VCOs.
392fe5e51b7Smrg     *
393fe5e51b7Smrg     * MGA cards have between one and three VCOs that can be used to drive the
394fe5e51b7Smrg     * various clocks.  On older cards, only \c mga_bios_values::pixel VCO is
395fe5e51b7Smrg     * available.  On newer cards, such as the G450 and G550, all three are
396fe5e51b7Smrg     * available.  If \c mga_VCO::max_freq is zero, the VCO is not available.
397fe5e51b7Smrg     */
398fe5e51b7Smrg    /*@{*/
399fe5e51b7Smrg    struct mga_VCO   system;    /**< System VCO. */
400fe5e51b7Smrg    struct mga_VCO   pixel;     /**< Pixel VCO. */
401fe5e51b7Smrg    struct mga_VCO   video;     /**< Video VCO. */
402fe5e51b7Smrg    /*@}*/
403fe5e51b7Smrg
404fe5e51b7Smrg    /**
405fe5e51b7Smrg     * Memory clock speed, measured in kHz.
406fe5e51b7Smrg     */
407fe5e51b7Smrg    unsigned mem_clock;
408fe5e51b7Smrg
409fe5e51b7Smrg    /**
410fe5e51b7Smrg     * PLL reference frequency value.  On older cards this is ~14MHz, and on
411fe5e51b7Smrg     * newer cards it is ~27MHz.
412fe5e51b7Smrg     */
413fe5e51b7Smrg    unsigned pll_ref_freq;
414fe5e51b7Smrg
415fe5e51b7Smrg    /**
416fe5e51b7Smrg     * Some older MGA cards have a "fast bitblt" mode.  This is determined
417fe5e51b7Smrg     * by a capability bit stored in the PInS data.
418fe5e51b7Smrg     */
419fe5e51b7Smrg    Bool fast_bitblt;
420fe5e51b7Smrg
421fe5e51b7Smrg    /**
422fe5e51b7Smrg     * Type of physical interface used for the card.
423fe5e51b7Smrg     */
424fe5e51b7Smrg    mga_host_t host_interface;
425fe5e51b7Smrg};
426fe5e51b7Smrg
427fe5e51b7Smrg
428fe5e51b7Smrg/**
429fe5e51b7Smrg * Attributes that of an MGA device that can be derrived purely from its
430fe5e51b7Smrg * PCI ID.
431fe5e51b7Smrg */
432fe5e51b7Smrgstruct mga_device_attributes {
433fe5e51b7Smrg    unsigned has_sdram:1;
434fe5e51b7Smrg    unsigned probe_for_sdram:1;
435fe5e51b7Smrg    unsigned dual_head_possible:1;
436fe5e51b7Smrg    unsigned fb_4mb_quirk:1;
437fe5e51b7Smrg    unsigned hwcursor_1064:1;
438fe5e51b7Smrg
439fe5e51b7Smrg    unsigned dri_capable:1;
440fe5e51b7Smrg    unsigned dri_chipset:3;
441fe5e51b7Smrg
442fe5e51b7Smrg    unsigned HAL_chipset:1;
443fe5e51b7Smrg
444fe5e51b7Smrg    enum {
445fe5e51b7Smrg	old_BARs = 0,
446fe5e51b7Smrg	probe_BARs,
447fe5e51b7Smrg	new_BARs
448fe5e51b7Smrg    } BARs:2;
449fe5e51b7Smrg
450fe5e51b7Smrg    uint32_t accel_flags;
451eda3803bSmrg
452eda3803bSmrg    /** Default BIOS values. */
453eda3803bSmrg    struct mga_bios_values default_bios_values;
454eda3803bSmrg
455eda3803bSmrg    /** Default memory probe offset / size values. */
456eda3803bSmrg    unsigned probe_size;
457eda3803bSmrg    unsigned probe_offset;
458fe5e51b7Smrg};
459fe5e51b7Smrg
460fe5e51b7Smrgtypedef struct {
461fe5e51b7Smrg    EntityInfoPtr	pEnt;
462fe5e51b7Smrg    struct mga_bios_values bios;
463fe5e51b7Smrg    CARD8               BiosOutputMode;
464fe5e51b7Smrg#ifdef XSERVER_LIBPCIACCESS
465fe5e51b7Smrg    struct pci_device *	PciInfo;
466fe5e51b7Smrg#else
467fe5e51b7Smrg    pciVideoPtr		PciInfo;
468fe5e51b7Smrg    PCITAG		PciTag;
469643b027fSmrg    xf86AccessRec	Access;
470fe5e51b7Smrg#endif
471fe5e51b7Smrg    const struct mga_device_attributes * chip_attribs;
472fe5e51b7Smrg    int			Chipset;
473fe5e51b7Smrg    int                 ChipRev;
474fe5e51b7Smrg
475fe5e51b7Smrg    int is_Gx50:1;
476fe5e51b7Smrg    int is_G200SE:1;
477eda3803bSmrg    int is_G200WB:1;
478eda3803bSmrg    int is_G200EV:1;
479a31a186aSmrg    int is_G200EH:1;
4800bb88ba4Smrg    int is_G200ER:1;
481eda3803bSmrg
482eda3803bSmrg    int KVM;
483eda3803bSmrg
484eda3803bSmrg    CARD32		reg_1e24;   /* model revision on g200se */
485fe5e51b7Smrg
486fe5e51b7Smrg    Bool		Primary;
487fe5e51b7Smrg    Bool		Interleave;
488fe5e51b7Smrg    int			HwBpp;
489fe5e51b7Smrg    int			Roundings[4];
490fe5e51b7Smrg    int			BppShifts[4];
491fe5e51b7Smrg    Bool		HasFBitBlt;
492fe5e51b7Smrg    Bool		OverclockMem;
493fe5e51b7Smrg    int			YDstOrg;
494fe5e51b7Smrg    int			DstOrg;
495fe5e51b7Smrg    int			SrcOrg;
496fe5e51b7Smrg
497fe5e51b7Smrg    /**
498fe5e51b7Smrg     * Which BAR corresponds to the framebuffer on this chip?
499fe5e51b7Smrg     */
500fe5e51b7Smrg    unsigned            framebuffer_bar;
501fe5e51b7Smrg
502fe5e51b7Smrg    /**
503fe5e51b7Smrg     * Which BAR corresponds to IO space on this chip?
504fe5e51b7Smrg     */
505fe5e51b7Smrg    unsigned            io_bar;
506fe5e51b7Smrg
507fe5e51b7Smrg    /**
508fe5e51b7Smrg     * Which BAR corresponds to ILOAD space on this chip?  If the value is
509fe5e51b7Smrg     * -1, then this chip does not have an ILOAD region.
510fe5e51b7Smrg     */
511fe5e51b7Smrg    int                 iload_bar;
512fe5e51b7Smrg
513fe5e51b7Smrg#ifndef XSERVER_LIBPCIACCESS
514fe5e51b7Smrg    unsigned long	IOAddress;
515fe5e51b7Smrg    unsigned long	ILOADAddress;
516fe5e51b7Smrg    unsigned long	BiosAddress;
517fe5e51b7Smrg    MessageType		BiosFrom;
518fe5e51b7Smrg#endif
519fe5e51b7Smrg    unsigned long	FbAddress;
520fe5e51b7Smrg    unsigned char *     IOBase;
521fe5e51b7Smrg    unsigned char *	FbBase;
522fe5e51b7Smrg    unsigned char *	ILOADBase;
523fe5e51b7Smrg    unsigned char *	FbStart;
524fe5e51b7Smrg    long		FbMapSize;
525fe5e51b7Smrg    long		FbUsableSize;
526fe5e51b7Smrg    long		FbCursorOffset;
527fe5e51b7Smrg    MGARamdacRec	Dac;
528fe5e51b7Smrg    Bool		HasSDRAM;
529fe5e51b7Smrg    Bool		NoAccel;
530fe5e51b7Smrg    Bool		Exa;
531fe5e51b7Smrg    ExaDriverPtr 	ExaDriver;
532fe5e51b7Smrg    Bool		SyncOnGreen;
533fe5e51b7Smrg    Bool		HWCursor;
534fe5e51b7Smrg    Bool		UsePCIRetry;
535fe5e51b7Smrg    Bool		ShowCache;
536fe5e51b7Smrg    Bool		ShadowFB;
537fe5e51b7Smrg    unsigned char *	ShadowPtr;
538fe5e51b7Smrg    int			ShadowPitch;
539fe5e51b7Smrg    int			MemClk;
540fe5e51b7Smrg    int			MinClock;
541fe5e51b7Smrg    int			MaxClock;
542fe5e51b7Smrg    MGARegRec		SavedReg;
543fe5e51b7Smrg    MGARegRec		ModeReg;
544fe5e51b7Smrg    int			MaxFastBlitY;
545fe5e51b7Smrg    CARD32		BltScanDirection;
546fe5e51b7Smrg    CARD32		FilledRectCMD;
547fe5e51b7Smrg    CARD32		SolidLineCMD;
548fe5e51b7Smrg    CARD32		PatternRectCMD;
549fe5e51b7Smrg    CARD32		DashCMD;
550fe5e51b7Smrg    CARD32		NiceDashCMD;
551fe5e51b7Smrg    CARD32		AccelFlags;
552fe5e51b7Smrg    CARD32		PlaneMask;
553fe5e51b7Smrg    CARD32		FgColor;
554fe5e51b7Smrg    CARD32		BgColor;
555fe5e51b7Smrg    CARD32		MAccess;
556fe5e51b7Smrg    int			FifoSize;
557fe5e51b7Smrg    int			StyleLen;
5580bb88ba4Smrg#ifdef HAVE_XAA_H
559fe5e51b7Smrg    XAAInfoRecPtr	AccelInfoRec;
5600bb88ba4Smrg#endif
561fe5e51b7Smrg    xf86CursorInfoPtr	CursorInfoRec;
562fe5e51b7Smrg    DGAModePtr		DGAModes;
563fe5e51b7Smrg    int			numDGAModes;
564fe5e51b7Smrg    Bool		DGAactive;
565fe5e51b7Smrg    int			DGAViewportStatus;
566fe5e51b7Smrg    CARD32		*Atype;
567fe5e51b7Smrg    CARD32		*AtypeNoBLK;
568fe5e51b7Smrg    void		(*PreInit)(ScrnInfoPtr pScrn);
569fe5e51b7Smrg    void		(*Save)(ScrnInfoPtr, vgaRegPtr, MGARegPtr, Bool);
570fe5e51b7Smrg    void		(*Restore)(ScrnInfoPtr, vgaRegPtr, MGARegPtr, Bool);
571fe5e51b7Smrg    Bool		(*ModeInit)(ScrnInfoPtr, DisplayModePtr);
5720bb88ba4Smrg    void		(*PointerMoved)(SCRN_ARG_TYPE arg, int x, int y);
573fe5e51b7Smrg    CloseScreenProcPtr	CloseScreen;
574fe5e51b7Smrg    ScreenBlockHandlerProcPtr BlockHandler;
575fe5e51b7Smrg    unsigned int	(*ddc1Read)(ScrnInfoPtr);
576fe5e51b7Smrg    void (*DDC1SetSpeed)(ScrnInfoPtr, xf86ddcSpeed);
577fe5e51b7Smrg    Bool		(*i2cInit)(ScrnInfoPtr);
578fe5e51b7Smrg    I2CBusPtr		DDC_Bus1;
579fe5e51b7Smrg    I2CBusPtr		DDC_Bus2;
580fe5e51b7Smrg    I2CBusPtr		Maven_Bus;
581fe5e51b7Smrg    I2CDevPtr		Maven;
582fe5e51b7Smrg    char		Maven_Version;
583fe5e51b7Smrg    Bool		UseMaven;
584fe5e51b7Smrg    Bool		UseMavenPM;
585fe5e51b7Smrg    Bool		FBDev;
586fe5e51b7Smrg    int			colorKey;
587fe5e51b7Smrg    int			videoKey;
588fe5e51b7Smrg    int			fifoCount;
589fe5e51b7Smrg    int			Rotate;
590fe5e51b7Smrg    MGAFBLayout		CurrentLayout;
591fe5e51b7Smrg    Bool		DrawTransparent;
592fe5e51b7Smrg    int			MaxBlitDWORDS;
593fe5e51b7Smrg    Bool		TexturedVideo;
594fe5e51b7Smrg    MGAPortPrivPtr	portPrivate;
595fe5e51b7Smrg    unsigned char	*ScratchBuffer;
596fe5e51b7Smrg    unsigned char	*ColorExpandBase;
597fe5e51b7Smrg    int			expandRows;
598fe5e51b7Smrg    int			expandDWORDs;
599fe5e51b7Smrg    int			expandRemaining;
600fe5e51b7Smrg    int			expandHeight;
601fe5e51b7Smrg    int			expandY;
6020bb88ba4Smrg#ifdef MGADRI
603fe5e51b7Smrg    Bool 		directRenderingEnabled;
604fe5e51b7Smrg    DRIInfoPtr 		pDRIInfo;
605fe5e51b7Smrg    int 		drmFD;
606fe5e51b7Smrg    int 		numVisualConfigs;
607fe5e51b7Smrg    __GLXvisualConfig*	pVisualConfigs;
608fe5e51b7Smrg    MGAConfigPrivPtr 	pVisualConfigsPriv;
609fe5e51b7Smrg    MGADRIServerPrivatePtr DRIServerInfo;
610fe5e51b7Smrg
611fe5e51b7Smrg    MGARegRec		DRContextRegs;
612fe5e51b7Smrg
613fe5e51b7Smrg    Bool		haveQuiescense;
614fe5e51b7Smrg    void		(*GetQuiescence)(ScrnInfoPtr pScrn);
615fe5e51b7Smrg
616fe5e51b7Smrg    int 		agpMode;
617fe5e51b7Smrg    int                 agpSize;
618fe5e51b7Smrg
619fe5e51b7Smrg    int                 irq;
620fe5e51b7Smrg    CARD32              reg_ien;
621fe5e51b7Smrg
622fe5e51b7Smrg    Bool                useOldDmaInit;
623fe5e51b7Smrg    Bool                forcePciDma;
624fe5e51b7Smrg#endif
625fe5e51b7Smrg    XF86VideoAdaptorPtr adaptor;
626fe5e51b7Smrg    Bool		DualHeadEnabled;
627fe5e51b7Smrg    Bool		Crtc2IsTV;
628fe5e51b7Smrg    Bool		SecondCrtc;
629fe5e51b7Smrg    Bool                SecondOutput;
630fe5e51b7Smrg
631fe5e51b7Smrg    GDevPtr		device;
632fe5e51b7Smrg    /* The hardware's real SrcOrg */
633fe5e51b7Smrg    int			realSrcOrg;
634fe5e51b7Smrg    MGAEntPtr		entityPrivate;
635fe5e51b7Smrg    void		(*SetupForSolidFill)(ScrnInfoPtr pScrn, int color,
636fe5e51b7Smrg					     int rop, unsigned int planemask);
637fe5e51b7Smrg    void		(*SubsequentSolidFillRect)(ScrnInfoPtr pScrn,
638fe5e51b7Smrg					     int x, int y, int w, int h);
639fe5e51b7Smrg    void		(*RestoreAccelState)(ScrnInfoPtr pScrn);
640fe5e51b7Smrg    int			allowedWidth;
641fe5e51b7Smrg    void		(*VideoTimerCallback)(ScrnInfoPtr, Time);
642fe5e51b7Smrg    void		(*PaletteLoadCallback)(ScrnInfoPtr);
643fe5e51b7Smrg    void		(*RenderCallback)(ScrnInfoPtr);
644fe5e51b7Smrg    Time		RenderTime;
645fe5e51b7Smrg    MGAPaletteInfo	palinfo[256];  /* G400 hardware bug workaround */
646fe5e51b7Smrg    FBLinearPtr		LinearScratch;
647fe5e51b7Smrg    Bool                softbooted;
648fe5e51b7Smrg    OptionInfoPtr	Options;
649fe5e51b7Smrg
650fe5e51b7Smrg    /* Exa */
651fe5e51b7Smrg    PicturePtr currentSrcPicture;
652fe5e51b7Smrg    PicturePtr currentMaskPicture;
653fe5e51b7Smrg    PixmapPtr currentSrc;
654fe5e51b7Smrg    PixmapPtr currentMask;
655fe5e51b7Smrg    int src_w2;
656fe5e51b7Smrg    int src_h2;
657fe5e51b7Smrg    int mask_w2;
658fe5e51b7Smrg    int mask_h2;
659fe5e51b7Smrg    CARD32 src_pitch; /* FIXME kill me */
660fe5e51b7Smrg
661fe5e51b7Smrg/* Merged Framebuffer data */
662fe5e51b7Smrg    Bool                MergedFB;
663fe5e51b7Smrg
664fe5e51b7Smrg    /* Real values specific to monitor1, since the original ones are replaced */
665fe5e51b7Smrg    DisplayModePtr	M1modes;	 /* list of actual modes */
666fe5e51b7Smrg    DisplayModePtr	M1currentMode; /* current mode */
667fe5e51b7Smrg    int			M1frameX0;	/* viewport position */
668fe5e51b7Smrg    int			M1frameY0;
669fe5e51b7Smrg    int			M1frameX1;
670fe5e51b7Smrg    int			M1frameY1;
671fe5e51b7Smrg
672fe5e51b7Smrg    ScrnInfoPtr       pScrn2; /*pointer to second CRTC screeninforec,
673fe5e51b7Smrg                                       if in merged mode */
674fe5e51b7Smrg/* End of Merged Framebuffer Data */
675fe5e51b7Smrg  int			HALGranularityOffX, HALGranularityOffY;
676fe5e51b7Smrg} MGARec, *MGAPtr;
677fe5e51b7Smrg
678fe5e51b7Smrgextern CARD32 MGAAtype[16];
679fe5e51b7Smrgextern CARD32 MGAAtypeNoBLK[16];
680fe5e51b7Smrg
681fe5e51b7Smrg#define USE_RECTS_FOR_LINES	0x00000001
682fe5e51b7Smrg#define FASTBLT_BUG		0x00000002
683fe5e51b7Smrg#define CLIPPER_ON		0x00000004
684fe5e51b7Smrg#define BLK_OPAQUE_EXPANSION	0x00000008
685fe5e51b7Smrg#define TRANSC_SOLID_FILL	0x00000010
686fe5e51b7Smrg#define	NICE_DASH_PATTERN	0x00000020
687fe5e51b7Smrg#define	TWO_PASS_COLOR_EXPAND	0x00000040
688fe5e51b7Smrg#define	MGA_NO_PLANEMASK	0x00000080
689acd6767fSmrg/* linear expansion doesn't work on BE due to wrong byte order */
690acd6767fSmrg#if X_BYTE_ORDER == X_BIG_ENDIAN
691acd6767fSmrg#define USE_LINEAR_EXPANSION	0x00000000
692acd6767fSmrg#else
693fe5e51b7Smrg#define USE_LINEAR_EXPANSION	0x00000100
694acd6767fSmrg#endif
695fe5e51b7Smrg#define LARGE_ADDRESSES		0x00000200
696fe5e51b7Smrg
697fe5e51b7Smrg#define MGAIOMAPSIZE		0x00004000
698fe5e51b7Smrg#define MGAILOADMAPSIZE		0x00400000
699fe5e51b7Smrg
700fe5e51b7Smrg#define TRANSPARENCY_KEY	255
701fe5e51b7Smrg#define KEY_COLOR		0
702fe5e51b7Smrg
703fe5e51b7Smrg
704fe5e51b7Smrg/* Prototypes */
705fe5e51b7Smrg
7060bb88ba4Smrgvoid MGAAdjustFrame(ADJUST_FRAME_ARGS_DECL);
7070bb88ba4SmrgBool MGASwitchMode(SWITCH_MODE_ARGS_DECL);
708fe5e51b7Smrgvoid MGAFillModeInfoStruct(ScrnInfoPtr pScrn, DisplayModePtr mode);
709fe5e51b7SmrgBool MGAGetRec(ScrnInfoPtr pScrn);
710fe5e51b7Smrgvoid MGAProbeDDC(ScrnInfoPtr pScrn, int index);
711fe5e51b7Smrgvoid MGASoftReset(ScrnInfoPtr pScrn);
712fe5e51b7Smrgvoid MGAFreeRec(ScrnInfoPtr pScrn);
713fe5e51b7SmrgBool mga_read_and_process_bios(ScrnInfoPtr pScrn);
714fe5e51b7Smrgvoid MGADisplayPowerManagementSet(ScrnInfoPtr pScrn, int PowerManagementMode,
715fe5e51b7Smrg				  int flags);
7160bb88ba4Smrgvoid MGAAdjustFrameCrtc2(ADJUST_FRAME_ARGS_DECL);
717fe5e51b7Smrgvoid MGADisplayPowerManagementSetCrtc2(ScrnInfoPtr pScrn,
718fe5e51b7Smrg					     int PowerManagementMode,
719fe5e51b7Smrg					     int flags);
720fe5e51b7Smrgvoid MGAAdjustGranularity(ScrnInfoPtr pScrn, int* x, int* y);
721fe5e51b7Smrg
722fe5e51b7Smrg
723fe5e51b7Smrgvoid MGA2064SetupFuncs(ScrnInfoPtr pScrn);
724fe5e51b7Smrgvoid MGAGSetupFuncs(ScrnInfoPtr pScrn);
725fe5e51b7Smrg
7260bb88ba4Smrg/*#ifdef USE_XAA */
727fe5e51b7Smrgvoid MGAStormSync(ScrnInfoPtr pScrn);
728fe5e51b7Smrgvoid MGAStormEngineInit(ScrnInfoPtr pScrn);
729fe5e51b7SmrgBool MGAStormAccelInit(ScreenPtr pScreen);
730fe5e51b7SmrgBool mgaAccelInit(ScreenPtr pScreen);
731fe5e51b7Smrg/* #endif */
732fe5e51b7Smrg
733fe5e51b7Smrg#ifdef USE_EXA
734fe5e51b7SmrgBool mgaExaInit(ScreenPtr pScreen);
735fe5e51b7Smrg#endif
736fe5e51b7Smrg
737fe5e51b7SmrgBool MGAHWCursorInit(ScreenPtr pScreen);
738fe5e51b7Smrg
739fe5e51b7Smrg
740fe5e51b7Smrgvoid MGAPolyArcThinSolid(DrawablePtr, GCPtr, int, xArc*);
741fe5e51b7Smrg
742fe5e51b7SmrgBool MGADGAInit(ScreenPtr pScreen);
743fe5e51b7Smrg
744fe5e51b7Smrgvoid MGARefreshArea(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
745fe5e51b7Smrgvoid MGARefreshArea8(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
746fe5e51b7Smrgvoid MGARefreshArea16(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
747fe5e51b7Smrgvoid MGARefreshArea24(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
748fe5e51b7Smrgvoid MGARefreshArea32(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
749fe5e51b7Smrg
750fe5e51b7Smrgvoid mgaDoSetupForScreenToScreenCopy( ScrnInfoPtr pScrn, int xdir,
751fe5e51b7Smrg    int ydir, int rop, unsigned int planemask, int trans, unsigned int bpp );
752fe5e51b7Smrg
753fe5e51b7Smrgvoid mgaDoSetupForSolidFill( ScrnInfoPtr pScrn, int color, int rop,
754fe5e51b7Smrg    unsigned int planemask, unsigned int bpp );
755fe5e51b7Smrg
7560bb88ba4Smrgvoid MGAPointerMoved(SCRN_ARG_TYPE arg, int x, int y);
757fe5e51b7Smrg
758fe5e51b7Smrgvoid MGAInitVideo(ScreenPtr pScreen);
759fe5e51b7Smrgvoid MGAResetVideo(ScrnInfoPtr pScrn);
760fe5e51b7Smrg
7610bb88ba4Smrg#ifdef MGADRI
762fe5e51b7Smrg
763fe5e51b7Smrg#define MGA_FRONT	0x1
764fe5e51b7Smrg#define MGA_BACK	0x2
765fe5e51b7Smrg#define MGA_DEPTH	0x4
766fe5e51b7Smrg
767fe5e51b7SmrgBool MGADRIScreenInit( ScreenPtr pScreen );
768fe5e51b7Smrgvoid MGADRICloseScreen( ScreenPtr pScreen );
769fe5e51b7SmrgBool MGADRIFinishScreenInit( ScreenPtr pScreen );
770fe5e51b7Smrg
771fe5e51b7SmrgBool MGALockUpdate( ScrnInfoPtr pScrn, drmLockFlags flags );
772fe5e51b7Smrg
773fe5e51b7Smrgvoid MGAGetQuiescence( ScrnInfoPtr pScrn );
774fe5e51b7Smrgvoid MGAGetQuiescenceShared( ScrnInfoPtr pScrn );
775fe5e51b7Smrg
776fe5e51b7Smrgvoid MGASelectBuffer(ScrnInfoPtr pScrn, int which);
777fe5e51b7SmrgBool MgaCleanupDma(ScrnInfoPtr pScrn);
778fe5e51b7SmrgBool MgaInitDma(ScrnInfoPtr pScrn, int prim_size);
779fe5e51b7Smrg
780fe5e51b7Smrg#define MGA_AGP_1X_MODE		0x01
781fe5e51b7Smrg#define MGA_AGP_2X_MODE		0x02
782fe5e51b7Smrg#define MGA_AGP_4X_MODE		0x04
783fe5e51b7Smrg#define MGA_AGP_MODE_MASK	0x07
784fe5e51b7Smrg
785fe5e51b7Smrg#endif
786fe5e51b7Smrg
787fe5e51b7SmrgBool MGAMavenRead(ScrnInfoPtr pScrn, I2CByte reg, I2CByte *val);
788fe5e51b7Smrg
789fe5e51b7Smrgvoid MGACRTC2Set(ScrnInfoPtr pScrn, xMODEINFO *pModeInfo);
790fe5e51b7Smrgvoid MGAEnableSecondOutPut(ScrnInfoPtr pScrn, xMODEINFO *pModeInfo);
791fe5e51b7Smrgvoid MGACRTC2SetPitch(ScrnInfoPtr pSrcn, xMODEINFO *pModeInfo);
792fe5e51b7Smrgvoid MGACRTC2SetDisplayStart(ScrnInfoPtr pScrn, xMODEINFO *pModeInfo, CARD32 base, CARD32 ulX, CARD32 ulY);
793fe5e51b7Smrg
794fe5e51b7Smrgvoid MGACRTC2Get(ScrnInfoPtr pScrn, xMODEINFO *pModeInfo);
795fe5e51b7Smrgvoid MGACRTC2GetPitch(ScrnInfoPtr pSrcn, xMODEINFO *pModeInfo);
796fe5e51b7Smrgvoid MGACRTC2GetDisplayStart(ScrnInfoPtr pScrn, xMODEINFO *pModeInfo, CARD32 base, CARD32 ulX, CARD32 ulY);
797fe5e51b7Smrg
798fe5e51b7Smrgdouble MGAG450SetPLLFreq(ScrnInfoPtr pScrn, long f_out);
799fe5e51b7Smrg#ifdef DEBUG
800fe5e51b7Smrgvoid MGAG450PrintPLL(ScrnInfoPtr pScrn);
801fe5e51b7Smrg#endif
802fe5e51b7Smrglong MGAG450SavePLLFreq(ScrnInfoPtr pScrn);
803fe5e51b7Smrgvoid MGAprintDac(ScrnInfoPtr pScrn);
804fe5e51b7Smrgvoid MGAG200SESaveFonts(ScrnInfoPtr, vgaRegPtr);
805fe5e51b7Smrgvoid MGAG200SERestoreFonts(ScrnInfoPtr, vgaRegPtr);
806fe5e51b7Smrgvoid MGAG200SESaveMode(ScrnInfoPtr, vgaRegPtr);
807fe5e51b7Smrgvoid MGAG200SERestoreMode(ScrnInfoPtr, vgaRegPtr);
808fe5e51b7Smrgvoid MGAG200SEHWProtect(ScrnInfoPtr, Bool);
809fe5e51b7Smrg
810fe5e51b7Smrgstatic __inline__ void
811fe5e51b7SmrgMGA_MARK_SYNC(MGAPtr pMga, ScrnInfoPtr pScrn)
812fe5e51b7Smrg{
813fe5e51b7Smrg#ifdef USE_EXA
814fe5e51b7Smrg    if (pMga->Exa)
815fe5e51b7Smrg        exaMarkSync(pScrn->pScreen);
816fe5e51b7Smrg#endif
817fe5e51b7Smrg#ifdef USE_XAA
818fe5e51b7Smrg    if (!pMga->Exa)
819fe5e51b7Smrg        SET_SYNC_FLAG(pMga->AccelInfoRec);
820fe5e51b7Smrg#endif
821fe5e51b7Smrg}
822fe5e51b7Smrg
823fe5e51b7Smrgstatic __inline__ void
824fe5e51b7SmrgMGA_SYNC(MGAPtr pMga, ScrnInfoPtr pScrn)
825fe5e51b7Smrg{
826fe5e51b7Smrg#ifdef USE_EXA
827fe5e51b7Smrg    if (pMga->Exa)
828fe5e51b7Smrg        exaWaitSync(pScrn->pScreen);
829fe5e51b7Smrg#endif
830fe5e51b7Smrg#ifdef USE_XAA
831fe5e51b7Smrg    if (!pMga->Exa && pMga->AccelInfoRec && pMga->AccelInfoRec->NeedToSync)
832fe5e51b7Smrg        pMga->AccelInfoRec->Sync(pScrn);
833fe5e51b7Smrg#endif
834fe5e51b7Smrg}
835fe5e51b7Smrg
836fe5e51b7Smrg#endif
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