1fe5e51b7Smrg/* mga_common.h -- common header definitions for MGA 2D/3D/DRM suite 2fe5e51b7Smrg * 3fe5e51b7Smrg * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 4fe5e51b7Smrg * All Rights Reserved. 5fe5e51b7Smrg * 6fe5e51b7Smrg * Permission is hereby granted, free of charge, to any person obtaining a 7fe5e51b7Smrg * copy of this software and associated documentation files (the "Software"), 8fe5e51b7Smrg * to deal in the Software without restriction, including without limitation 9fe5e51b7Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10fe5e51b7Smrg * and/or sell copies of the Software, and to permit persons to whom the 11fe5e51b7Smrg * Software is furnished to do so, subject to the following conditions: 12fe5e51b7Smrg * 13fe5e51b7Smrg * The above copyright notice and this permission notice (including the next 14fe5e51b7Smrg * paragraph) shall be included in all copies or substantial portions of the 15fe5e51b7Smrg * Software. 16fe5e51b7Smrg * 17fe5e51b7Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18fe5e51b7Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19fe5e51b7Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20fe5e51b7Smrg * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 21fe5e51b7Smrg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22fe5e51b7Smrg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23fe5e51b7Smrg * DEALINGS IN THE SOFTWARE. 24fe5e51b7Smrg * 25fe5e51b7Smrg * Converted to common header format: 26fe5e51b7Smrg * Jens Owen <jens@tungstengraphics.com> 27fe5e51b7Smrg * 28fe5e51b7Smrg */ 29fe5e51b7Smrg 30fe5e51b7Smrg#ifndef _MGA_COMMON_H_ 31fe5e51b7Smrg#define _MGA_COMMON_H_ 32fe5e51b7Smrg 33fe5e51b7Smrg/* 34fe5e51b7Smrg * WARNING: If you change any of these defines, make sure to change 35fe5e51b7Smrg * the kernel include file as well (mga_drm.h) 36fe5e51b7Smrg */ 37fe5e51b7Smrg 38fe5e51b7Smrg#define DRM_MGA_IDLE_RETRY 2048 39fe5e51b7Smrg#define DRM_MGA_NR_TEX_HEAPS 2 40fe5e51b7Smrg 41fe5e51b7Smrgtypedef struct { 42fe5e51b7Smrg int installed; 43fe5e51b7Smrg unsigned long phys_addr; 44fe5e51b7Smrg int size; 45fe5e51b7Smrg} drmMGAWarpIndex; 46fe5e51b7Smrg 47fe5e51b7Smrg/* Driver specific DRM command indices 48fe5e51b7Smrg * NOTE: these are not OS specific, but they are driver specific 49fe5e51b7Smrg */ 50fe5e51b7Smrg#define DRM_MGA_INIT 0x00 51fe5e51b7Smrg#define DRM_MGA_FLUSH 0x01 52fe5e51b7Smrg#define DRM_MGA_RESET 0x02 53fe5e51b7Smrg#define DRM_MGA_SWAP 0x03 54fe5e51b7Smrg#define DRM_MGA_CLEAR 0x04 55fe5e51b7Smrg#define DRM_MGA_VERTEX 0x05 56fe5e51b7Smrg#define DRM_MGA_INDICES 0x06 57fe5e51b7Smrg#define DRM_MGA_ILOAD 0x07 58fe5e51b7Smrg#define DRM_MGA_BLIT 0x08 59fe5e51b7Smrg#define DRM_MGA_GETPARAM 0x09 60fe5e51b7Smrg 61fe5e51b7Smrgtypedef struct { 62fe5e51b7Smrg enum { 63fe5e51b7Smrg MGA_INIT_DMA = 0x01, 64fe5e51b7Smrg MGA_CLEANUP_DMA = 0x02 65fe5e51b7Smrg } func; 66fe5e51b7Smrg 67fe5e51b7Smrg unsigned long sarea_priv_offset; 68fe5e51b7Smrg 69fe5e51b7Smrg int chipset; 70fe5e51b7Smrg int sgram; 71fe5e51b7Smrg 72fe5e51b7Smrg unsigned int maccess; 73fe5e51b7Smrg 74fe5e51b7Smrg unsigned int fb_cpp; 75fe5e51b7Smrg unsigned int front_offset, front_pitch; 76fe5e51b7Smrg unsigned int back_offset, back_pitch; 77fe5e51b7Smrg 78fe5e51b7Smrg unsigned int depth_cpp; 79fe5e51b7Smrg unsigned int depth_offset, depth_pitch; 80fe5e51b7Smrg 81fe5e51b7Smrg unsigned int texture_offset[DRM_MGA_NR_TEX_HEAPS]; 82fe5e51b7Smrg unsigned int texture_size[DRM_MGA_NR_TEX_HEAPS]; 83fe5e51b7Smrg 84fe5e51b7Smrg unsigned long fb_offset; 85fe5e51b7Smrg unsigned long mmio_offset; 86fe5e51b7Smrg unsigned long status_offset; 87fe5e51b7Smrg unsigned long warp_offset; 88fe5e51b7Smrg unsigned long primary_offset; 89fe5e51b7Smrg unsigned long buffers_offset; 90fe5e51b7Smrg} drmMGAInit; 91fe5e51b7Smrg 92fe5e51b7Smrgtypedef enum { 93fe5e51b7Smrg DRM_MGA_LOCK_READY = 0x01, /* Wait until hardware is ready for DMA */ 94fe5e51b7Smrg DRM_MGA_LOCK_QUIESCENT = 0x02, /* Wait until hardware quiescent */ 95fe5e51b7Smrg DRM_MGA_LOCK_FLUSH = 0x04, /* Flush this context's DMA queue first */ 96fe5e51b7Smrg DRM_MGA_LOCK_FLUSH_ALL = 0x08, /* Flush all DMA queues first */ 97fe5e51b7Smrg /* These *HALT* flags aren't supported yet 98fe5e51b7Smrg -- they will be used to support the 99fe5e51b7Smrg full-screen DGA-like mode. */ 100fe5e51b7Smrg DRM_MGA_HALT_ALL_QUEUES = 0x10, /* Halt all current and future queues */ 101fe5e51b7Smrg DRM_MGA_HALT_CUR_QUEUES = 0x20 /* Halt all current queues */ 102fe5e51b7Smrg} drmMGALockFlags; 103fe5e51b7Smrg 104fe5e51b7Smrgtypedef struct { 105fe5e51b7Smrg int context; 106fe5e51b7Smrg drmMGALockFlags flags; 107fe5e51b7Smrg} drmMGALock; 108fe5e51b7Smrg 109fe5e51b7Smrgtypedef struct { 110fe5e51b7Smrg int idx; 111fe5e51b7Smrg unsigned int dstorg; 112fe5e51b7Smrg unsigned int length; 113fe5e51b7Smrg} drmMGAIload; 114fe5e51b7Smrg 115fe5e51b7Smrgtypedef struct { 116fe5e51b7Smrg unsigned int flags; 117fe5e51b7Smrg unsigned int clear_color; 118fe5e51b7Smrg unsigned int clear_depth; 119fe5e51b7Smrg unsigned int color_mask; 120fe5e51b7Smrg unsigned int depth_mask; 121fe5e51b7Smrg} drmMGAClearRec; 122fe5e51b7Smrg 123fe5e51b7Smrgtypedef struct { 124fe5e51b7Smrg int idx; /* buffer to queue */ 125fe5e51b7Smrg int used; /* bytes in use */ 126fe5e51b7Smrg int discard; /* client finished with buffer? */ 127fe5e51b7Smrg} drmMGAVertex; 128fe5e51b7Smrg 129fe5e51b7Smrgtypedef struct { 130fe5e51b7Smrg unsigned int planemask; 131fe5e51b7Smrg unsigned int srcorg; 132fe5e51b7Smrg unsigned int dstorg; 133fe5e51b7Smrg int src_pitch, dst_pitch; 134fe5e51b7Smrg int delta_sx, delta_sy; 135fe5e51b7Smrg int delta_dx, delta_dy; 136fe5e51b7Smrg int height, ydir; /* flip image vertically */ 137fe5e51b7Smrg int source_pitch, dest_pitch; 138fe5e51b7Smrg} drmMGABlit; 139fe5e51b7Smrg 140fe5e51b7Smrg/* 3.1: An ioctl to get parameters that aren't available to the 3d 141fe5e51b7Smrg * client any other way. 142fe5e51b7Smrg */ 143fe5e51b7Smrg#define MGA_PARAM_IRQ_NR 1 144fe5e51b7Smrg 145fe5e51b7Smrgtypedef struct { 146fe5e51b7Smrg int param; 147fe5e51b7Smrg int *value; 148fe5e51b7Smrg} drmMGAGetParam; 149fe5e51b7Smrg 150fe5e51b7Smrg#endif 151